Design of Low Power, High PSRR Error Amplifier for Low Drop-Out CMOS Voltage Regulator

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Design of Low Power, High PSRR Error Amplifier for Low Drop-Out CMOS Voltage Regulator Dipendra Singh Patel1, Pramod Kumar Jain2, D.S. Ajnar3 Microelectronics & VLSI Design, Electronics & Instrumentation Dept., S.G.S.I.T.S. Indore, India 1

dspdipendra@gmail.com, 2prjain@sgsits.ac.in, 3ajnards@gmail.com

Abstract: This paper presents design of an improved Error amplifier (EA) for Low Drop-Out Voltage Regulator. The proposed circuit shows good behaviour as compared to the previous Error Amplifier. The Gain, Unity Gain Bandwidth, Phase Margin, CMRR and PSRR of an Error Amplifier is analysed. The proposed circuit is designed on UMC 180nm CMOS technology with supply voltage of 1.8Volts. All the simulation results are calculated through SPECTRE Simulator of cadence.

output noise of low dropout regulator is required to be quite low for the sake of not submerging the input signal.

Keywords: Amplifier, Error amplifier, Regulators, Low DropOut voltage electronics.

regulators,

System-on-chip

(SOC),

Analog

I. INTRODUCTION As the present market for portable electronic devices continues to expand around the world to desire for long battery life drives the search for efficient power management circuit architecture. The research in analogcircuit design is mainly focused in power management of various products, especially those relying on battery power.[1]-[4] Low drop-out voltage regulator is one of the important building block in battery operated portable electronic devices as well as industries and automation application. Presently the demand of portable and battery electronics product have forced this circuit to work under lower voltage condition, high voltage gain and also dropout voltage is low.[8] This strategy increase the battery life by controlling the power level delivered to each functional block through the use of power management circuit. The circuit must operate at low voltage and low current to maximize battery lifetime.

Low dropout regulator are one of the most critical power management module, as they can provide regulated low noise and precision supply voltage for noise sensitive analog blocks.[5]

Fig: 1 Block diagram of LDO regulator

Usually signal determines the minimum input signal that a circuit could manage; therefore a low noise power supply is critical for a system. In some systems the input signal is quite small such as cellular phone and RF circuits, so the 109

Fig:2 Structure of Generic CMOS LDO[10]

For all the communication devices such as mobile phone that have transmission and reception circuits operating at high frequency, the ripple noise of the power supply line gives bad influences on the stability at a transmission frequency and will result in a deteriorated voice or communication quality.[2] The objective of this error amplifier is to apply the practices and theories of the low voltage and low power voltage regulator. In this paper a well defined method of a CMOS two stage error amplifier has been generated. The design of this has been carried out from the scaling of the device parameter. As it is known that by maintaining scaling factor to minimum value can reduce the current, power consumption and area as well. Now an error amplifier has been defined in its negative feedback configuration, As it can provide the moderate gain as compared to open loop, but the problem in this case is the stability which will be reduced by using the compensation technique.[10] In this case the Miller compensation technique is executed in practical where the simplest frequency compensation technique employs the miller effect by connecting a compensation capacitor all across the high gain stage.

In this paper Error Amplifier and its designed consideration is mentioned in SECTION II. The SECTION III and SECTION IV show simulated results and Conclusion respectively.

II. ERROR AMPLIFIER AND DESIGN CONSIDERATION Basically low drop-out (LDO) regulator consists of three blocks. First block represents error amplifier second one is pass device and third one is feedback network which provide output to the input of first block which is error amp. In this paper our main concern is towards error NITTTR, Chandigarh

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

amplifier which is used in the first block of the regulator (LDO) to reduce the ripple noise voltage and enhance the Gain. The bias current of the error amplifier cannot be reduced as a result, a low power low dropout voltage regulator (LDO) having high power supply rejection ratio (PSRR) performance cannot be realized with a conventional LDO structure.[7]-[9] As we are familiar with the conventional low drop-out regulator (LDO) in which the dominant pole is located at very low freq of the output by which freq compensation can be obtained and better dynamic characteristics can be achieved.

For such circuit larger capacitor is required which occupied maximum area of chip, thus area of chip increases. In the designing of full on chip low drop-out regulator describe in the reference in which compensation capacitance used in minimum number. The schematic of proposed Error Amplifier shown below.

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Fig:4 Gain of EA

2. Phase margin and Unity Gain Bandwidth

Fig: 3 Proposed Error Amplifier

The Error Amplifier consists of two stages to increase the Gain. The transistor (M0,M1) is differential stage, transistor (M5,M8) shows current mirror to provide proper bias current to the differential stage, transistor (M3,M2) provides the biasing through the bias current source and transistor (M4,M7) are the second stage of Error Amplifier to enhance the Gain.

TABLE: 1 ASPECT RATIO OF MOS TRANSISTORS M0, M5.

M3, Transistors M7 M4 M1 M8 M2 Aspect 3 7 6 87 37.5 Ratio 0.5 .5 .5 .5 .5 (W/L)

Fig:5 Phase margin and UGB

3. CMRR of Error Amplifier CMRR for ERROR AMPLIFIER can be calculated by taking ratio of differential gain to the common mode gain.

The value of CMRR is determined by subtracting the differential input gain with common input gain in decibal(dB). The CMRR values obtained is 87.40dB.

The relation between load capacitance CL at output and compensation capacitance CC. CL≼ 2CC ... ..... ... .. .. .....eq (1) III. SIMULATION RESULTS For the proposed circuit, the analyse of Gain, Unity Gain Bandwidth, Phase Margin, CMMR and PSRR are obtained. All the simulation is done on SPECTRE Simulator of cadence tool. The simulation result shown below.

1. Gain of Error Amplifier

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Fig:6 CMRR test bench

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

range(Hz to MHz)

10

III. CONCLUSION The error amplifier implemented in 180nm CMOS process achieves an improved performance of over 64-dB GAIN, 77-dB PSRR and 87-dB CMRR. The circuit analysis and simulation results shown are obtained using CADENCE SPECTRE simulator within the frequency range of 10 Hz to 100 MHz The new circuit not only reduces ripple and noise of error amplifier, but also improve stability.

Fig:7 CMRR of EA 4. PSRR of Error Amplifier PSRR for the ERROR AMPLIFIER is defined as the ratio of output ripples with respect to the input ripples at large frequency range. PSRR is measured with both positive and negative power supply in decibel (dB). The PSRR value obtained is 77.54dB.

ACKNOWLEDGEMENTS This work has been carried out in SMDP-II, VLSI laboratory of the Electronics and Instrumentation Engineering Department of Shri G. S. Institute of Technology and Science, Indore, India. This SMDP-II, VLSI project is funded by Ministry of Information and Communication Technology, Government of India.

Authors are thankful to the Ministry for facilities provided under this project.

REFERENCES

Fig:8 PSRR test bench

Fig:9 The PSRR simulation result of proposed EA TABLE 2 Comparison of present results with earlier work done Reference Present Parameter work [3] [7] [10] Technology 0.18um 0.5um 0.5um 0.18um Supply voltage 1.8V 2.7V 3.5V 1.2V Dc gain 64.10dB 60dB 60dB N/A Phase margin 74° N/A 43 N/A GBW(MHz) 31.26 N/A 10.96 N/A CMRR(dB) 87.40 70 N/A N/A PSRR(dB) 77.54 40 71 65 Frequency 10-100 100N/A N/A

111

[1]. Ho-Joon Jang, Yong Seong Roh, Young-Jin Moon, Jeongpyo Park, and Changsik Yoo "Low Drop-Out (LDO) Voltage Regulator with Improved Power Supply Rejection" ,Journal of semiconductor technology and science, Volume 12,no.3,pp 313318 ,September 2012.

[2]. W.-J. Huang and S.-I. Liu "PSRR-enhanced low-dropout regulator", Electronics letters, Vol. 47, No. 1. pp 1-2 6th January 2011.

[3]. Xinquan Lai, Donglai Xu" An Improved CMOS Error Amplifier Design for LDO Regulators in Communication Applications", 7th WSEAS Int. Conf. on Electronics, Hardware, Wireless and Optical Communications, Cambridge, UK, pp 3234, February 20-22, 2008 [4]. Robert J Milliken, Josh Silva-Martinez "Full on chip CMOS voltage regulator", IEEE transactions on circuit and system-I, regular papers, volume 54,no.9, pp 1879-1889, September 2007.

[5]. GA. Rincon-Mora, "Current Efficient, Low Voltage, LowDropout Regulators." Ph.D. Thesis, Atlanta, GA: Georgia Institute of Technology, 1996.

[6]. Ramy Tantawy and Elizabeth J. Brauer "Performance Evaluation of CMOS Low Drop-Out Voltage Regulators", The 47th IEEE ,International Midwest Symposium on Circuits and Systems, pp 141-144 , 2004.

[7]. Rakesh Selvaraj, Shriram Kalusalingam "Design of error amplifier for LDO", Department of Electrical Engineering, Project report, Texas A&M University.

[8]. Jianping Guo, Ka Nang Leung "A 25mA CMOS LDO with 85dB PSRR at 2.5MHz" IEEE Asian Solid-State Circuits Conference (A-SSCC), pp 381-384 , 2013 [9]. Sanjay Pithadia and Scot Lester " LDO PSRR Measurement Simplified" Texas instrument Application report,pp 1-4 14–July 2009.

[10].Zared Kamal, Qjidaa Hassan, Zouak Mohcine, " High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications ", International Journal of Computer Applications, Volume 71– No.18, pp 7-14, June 2013.

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