Optimal Body Biasing Technique for CMOS Tapered Buffer

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Optimal Body Biasing Technique for CMOS Tapered Buffer 1,2,3

Harpreet Kaur1, Lipika Gupta2, Ajaypal Singh3 Department of Electronics and Communication, Chitkara University Himachal Pradesh, India

harpreet.kaur@chitkarauniversity.edu.in,lipika.gupta@chitkarauniversity.edu.in; ajaypal.singh@chitkarauniversity.edu.in

Abstract- This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.

Keywords: Tapering factor, CMOS inverter, PDP, RBB, FBB, Average power, Threshold voltage

I. INTRODUCTION As Buffer insertion is one of the popular technique to reduce the delay and driving high capacitive loads by logic CMOS Inverter. CMOS Tapered buffers are generally placed at regular intervals along on-chip or off-chip paths that seek signal restoration each time it is affected by the parasitic elements [3].

These circuits are mostly required which can drive the large capacitive load at high speed while not degrading the performance of previous stages in the chain of inverters [1]. This circuit provides amplified drain current at the output terminal and consists of chain of CMOS inverters with increasing width. Tapered Buffers usually based on fixed tapering factor.

Figure 1 shows an N-stage CMOS Tapered Buffer driving capacitive load and each inverter in the chain is having increasing width based on Tapering factor (F).

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Fig. 1 Tapered Buffer consisting of a chain of N inverters

Since there is Trade-off between Delay and power dissipation with the change in threshold voltage, hence for the purpose of signal restoration and to handle the on-chip delay and noise, buffer insertion technique has been modified. The power concerns related to buffering the signal have also received much attention because of the low power requirements of modern integrated systems.

Previous researchers [7, 8, and 12] have taken many approaches to solve different variants of the buffer insertion problem like technology dependant tapering factor, best number of stages for driving specific load capacitance and threshold voltage variations.

However, CMOS Tapered buffers themselves have certain switching time that contributes to signal delay. A large number of such buffers driving large capacitive loads can thus contribute to overall delay to signal propagation at output pin. Moreover buffer switching contributes to the total power dissipation and designing in DSM technologies; leakage power is a major problem. Due to that a long chain of CMOS inverters may consume sub-threshold leakage power even when they are not switching. Thus there is a need to evolve techniques that while reducing the overall delay, also consume less power, dynamic as well as static. Reduced power dissipation affects the reliability, packaging, cost and portability of the device; hence in this paper a low power design methodology is proposed which could results in the efficient design of the Tapered Buffers.

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e-ISSN: 1694-2310 | p-ISSN: 1694-2426

The organization of the paper is as follows: Section 2 shows an introduction to the Standard CMOS Tapered Buffer. Section 3 will focus on the proposed methodology used in the process. In Section 4 the proposal is validated with CADENCE simulations using ADE window. Section 5 includes the summary of simulation results and Finally Section 6 depicts the conclusions.

technology dependant parameters, the value of propagation delay of Buffer can be calculated using equation (2) as given in [1].

II. STANDARD CMOS TAPERED BUFFER With the continuous trend of Very Large Scale Integration (VLSI) technology the use of inverting and non – inverting buffers is to drive large fan out by logic gate so that they can deliver large current for fast response. The primary objective of a standard buffer is to reduce the path delay (RC delay) in combinational circuits therefore; buffer insertion is performed at the circuit level.

Where VDD is applied D.C voltage, VDO and IDO are the saturation drain voltage and saturation drain current at VGS = VDD, α is velocity saturation index and vt = Vth / VDD.

Tdelay = N VDD 1.125

ln

.

−

α

+

(2)

The total power dissipation in a CMOS tapered buffer can be calculated using equation (3) and its components are expressed separately. The expressions for three types of power are given using equations (4), (5) and (6) according to [4, 5].

PT = Pdyn + PS.C + Pstatic (i) Pdyn = CL * V2DD * f

(3) (4)

Where CL is capacitive load, VDD is VDC applied and f is the frequency of operation (ii) Pstatic = Istatic * VDD

(5)

Where Istatic is static current of MOS in idle state

Fig. 2 A Standard 3- stage CMOS Buffer

Figure 2 shows a standard 3-stage inverting Buffer driving capacitive load with applied VDD and Vpulse sources. The primary factors for the design of Standard Tapered buffer are tapering factor (increasing width of transistor in each stage) and number of stages of CMOS inverters in the chain. The optimal values of primary factors for implementing Buffer design play an important role [3]. The expressions related to Tapering factor and optimum number of stages used in the implementation of Buffer are mentioned in [1, 2] and are given below using equation (1).

ND =

(

/ ( )

)

where

F=

(1)

Here Cg is gate capacitance of minimum sized CMOS inverter and CL is load capacitance and F is technology dependant Tapering factor Enhanced short channel tapered buffer design equations are used for propagation delay and power dissipation as represented in [17]. Using primary and 169

(iii) Pavg(short-circuit) =

[k f (VDD- Vthn - |Vthp| )3] (6)

Where Vthn and Vthp are the threshold voltages of NMOS and PMOS and k is process dependant constant For simulating the schematics of standard and proposed Tapered Buffers using 180nm technology, VDD is taken as 1.8 V and Vpulse is of (0V to 1.8V) ranges with 50 MHz frequency. Load capacitor CL is taken as 84.6 fF and tapering factor is taken as 4.978.

III. LOW POWER PROPOSED METHODOLOGY Fixed Body Bias is such a design technique can be used to reduce the leakage to large extent in Tapered buffer designs. The forward body bias (FBB) improves the delay by reducing the threshold voltage Vth and the reverse body bias (RBB) is used to decrease the leakage current by increasing the threshold voltage Vth as given in [9,12].

By increasing the value of Vth while maintaining VDD constant, reduction in leakage power can be obtained [19]. And each performance parameter of NITTTR, Chandigarh

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Tapered Buffer can be analyzed according to the number of stages and tapering factor chosen. Hence, Reverse Body biasing strategy has been implemented with optimal values of tapering factor and no. of stages, for the proposed buffer design which simultaneously considers correlated issues of circuit speed and power dissipation, permitting the efficient design of CMOS Tapered buffer.

derived and then implemented in the first stage of Buffer chain.

Reduction of delay and power consumption is the main objective behind the design of proposed CMOS Tapered buffer. As shown in Figure 3, an optimal value of Reverse Body Bias has been used with NMOS (NM0) of the first stage in the Buffer chain. The proposed methodology helps to reduce short circuit power, sub threshold leakage power and finally average power of the circuit and capacitive load.

D.C analysis is performed to get VTC plot for the value of switching threshold voltage (VM) of an inverter.

It should be near to half of VDD because the propagation delay increases quickly as Vth is increased beyond 0.4 VDD and a high penalty in the speed has to be paid [16].

It is necessary to mention here that there is another advantage in not allowing the threshold voltage to increase beyond 0.4 VDD which is that logic level of the input signal will not be interpreted correctly [7]. Using ADE window in Virtuoso, the d.c analysis on the schematics of conventional and proposed schematics was carried to get the value of VM. Switching voltage of an inverter is relatively insensitive to variations in the width ratio (Wp/Wn) for same channel length [5].

Schematic models of standard Tapered buffer and proposed Tapered buffer are designed using optimal value of tapering factor in Virtuoso Editor. Schematic simulation is done using D.C, transient and tran-tran analyses in ADE window.

TABLE 1 Effect of Device ratio on the design of Tapered Buffer Wp/W Lp = Propaga Averag (VM ) in Averag n ratio Ln tion e Power D.C e of first (Lengt Delay of dissipat analysis Power inverte h of inverter ion dissipa r chann across tion of el) load VD.C source Fig. 3 Proposed 3-stage CMOS Buffer

Conflicting constraint on the design of Tapered buffer and can be named as design tradeoffs. Since increase in Vth reduces the speed.

Managing these effects, a trade-off between delay and average power-timing performances degradation can be found if a suited value of threshold voltage is considered. Still there is lot of research work required in this domain so that instead of using of extra VDD layer for the body biasing of NMOS, Adaptive body bias generators could be used for providing that particular value of body bias voltage for the first CMOS inverter [11].

IV. EXPERIMENTAL RESULTS OF ANALYSES PERFORMED USING ADE WINDOW The proposed aproach helps in the design of low power Fixed Body Biased buffers for not only maintaining the current driving capability of logic gate but also dissipating less power at optimal speed. In this paper, we showed how the optimal value of RBB is NITTTR, Chandigarh

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2µm/1µ m

180nm

9.19 ns

30.85 nW

813.79 mV

- 6.04 µW

2.5µm/ 1µm

180nm

9.17 ns

34.32 nW

841.58 mV

- 6.48 µW

It can be seen from Table 1 that power dissipation across load and VD.C source is less (with minimal penalty in delay) for (2µm/1µm) width ratio of CMOS inverter. Hence same width ratio is used in the first stage of Buffer chain.

It has been noticed by different researchers that the speed of operation, power dissipation, area utilization and reliable operation with full rail to rail operation are the performance criteria for a CMOS Tapered buffer for specific application. To get full rail to rail operation, the input output waveforms of the 3-stage Buffer are obtained by performing transient analysis over the period of 200 ns is shown in Figure 4. It can be seen in Figure 4 that 3-stage tapered Buffer is an inverting Buffer having least rise and fall time delays. The driving

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capability of Buffer is often high since it amplifies drain current after each stage.

Fig. 5 Tran-Tran Analysis of 3-stage proposed Buffer

The values observed in tran-tran analysis by plotting waveforms are recorded in Table 4.

Fig. 4 Transient Analysis of 3-stage proposed Buffer

The propagation delay, average power across load and average power dissipation of VD.C source is calculated using calculator option available in the waveform window of Virtuoso.

The calculated values using calculator for standard and proposed Buffer are then used for comparison of their performance parameters. After performing transient analysis, the drain current, sub-threshold leakage current and threshold voltage of NMOS of first stage are recorded in Table 2.

TABLE 2 Effect of increasing Vth on the performance parameters of NMOS in Buffer chain

Type of 3stage Tapered Buffer

Standard Buffer Proposed Buffer

Drain current of NMOS of first stage

Subthreshold leakage current of NMOS of first stage

Threshold voltage of NMOS of the first stage

14.84 pA

15.94 fA

527.93 mV

12.92 pA

13.88 fA

537.01 mV

It can be seen in Table 2 that for Vth= 537.01 mV, the power dissipation across load is least and the drain current has been reduced to 13% which could affect the delay of the circuit. Moreover sub-threshold leakage current of NMOS in the first stage of chain decreased by 12.9% for the proposed buffer which helps in further reduction in the leakage power.

The value of static power dissipation of the standard and proposed 3-stage Tapered Buffer is used for comparison by performing Tran-Tran analysis as shown in Figure 5.

171

V. SIMULATION RESULTS This proposed methodology could be helpful for optimizing the performance without varying no. of transistors or tapering factor of the standard circuit for the varying Vth. The threshold voltage of NM0 (NMOS of first stage in Buffer chain) is assigned a value that is in the range of (0.2 VDD - 0.4VDD) by using RBB of 15 mV. This range gives the highest reduction in power with minimal penalty in delay [8]. But, allowing the threshold voltage to set at optimal value of (0.3 times of VDD), results in the least average power dissipation across capacitive load as shown in Table 3. The effect of increasing the value of RBB on power dissipation and delay is recorded in Table 3. This table shows the combined results of performed analyses.

Body

TABLE 3 Effect of Reverse Body Bias on Vth of NMOS Vth of Propagation Average Average

Bias

NM0

voltage

delay (in ns)

Power

Power

(in

Dissipation

Dissipation

mV)

across

of

Load nW) 5 mV

534.87

10 mV

536.40

15 mV

537.01

20 mV

539.44

25 mV

540.95

9.37

(in

VD.C

source (in ÂľW)

19.01

83.40

9.37

20.52

83.38

9.37

2.27

83.69

9.37

3.98

83.69

9.37

14.61

83.48

Using Table 3 it can be seen that the average power dissipation is least for 15mV of Reverse Body Bias for the NMOS of first stage in 3-stage Buffer chain.

Table 4 shows the results obtained after simulation of standard and proposed 3-stage Buffers. Each parameter of performance criteria places different role in the optimization of proposed Buffer.

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TABLE 4 Effect of RBB on Performance parameters of Buffer

Performance Parameters

3-stage

3-stage RBB

Conventional

Tapered

Tapered

Buffer (With

Buffer

15 m RBB)

Static Power

833.58

consumption for Low

and

pW

and High levels of input

pW

pW

-83.70 µW

-83.64 µW

24.1 nW

4.3 nW

10.38 ns

10.37 ns

528 mV

537 mV

372.40

830.13 and

pW 372.39

pulse signal Average

power

dissipation of the VD.C source Average

Power

dissipation of load Propagation Delay st

Vth of NM0(I stage NMOS)

It has also been observed that in the proposed Buffer static power also gets reduced at circuit-level as compared to the standard Buffer. The simulation results obtained for comparison show that a slight increase in the threshold voltage has the substantial effect in reducing average power of capacitive load with only a minimal propagation delay penalty. As compared to standard design methodology of varying threshold voltage of MOS transistor, the proposed scheme led to overall power dissipation reduction across capacitive load by decreasing leakage current, while having almost same propagation delay.

VI. CONCLUSION It is shown that the proposed approach is better in terms of delay and power reduction compared to that of standard Tapered buffers. In this paper, we have introduced an efficient way for reducing average power dissipation across capacitive load without significant increase in other parameters, such as average power consumption and propagation delay. In fact, a reduction in leakage power consumption is also achieved. The proposed simple methodology shows that the Adaptive body biased buffer insertion is a good option in terms of low power consumption and for increasing driving capability of Tapered Buffer. Measurements, using CADENCE simulations, of both standard and proposed Buffers were done in 0.18µm technology, and also several buffers with different sizes were used in order to obtain the one with the best power-delay-product.

Experimental results show around 82.2% reduction in NITTTR, Chandigarh

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average power consumption across load and power across VD.C source has been reduced to 49.2%, while the propagation delay is almost same. Moreover it is observed that there is 12.9% decrease in sub-threshold leakage current of NMOS of first stage in the Buffer chain.

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[20] Mostafa, H.and Anis, M. ; Elmasry, M., “On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB)” , IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no.4, pp. 770-774, April,2012.

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[21] Sanjeev Maheshwari, Saurabh Sharma, Madhuri Garg, Rohit Agarwal, Vishal Singh, “Exploiting the Body of MOS Devices for High Performance Analog Design”, International Journal of Advanced Research in Computer and Communication Engineering, vol. 3, no. 2, pp.5695-5698,February 2014.

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