Layout and Design Analysis of Carry Look Ahead Adder using 90nm Technology

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Layout and Design Analysis of Carry Look Ahead Adder using 90nm Technology Anku Bala ME Student, National Institute of Technical Teachers’ Training &Research Chandigarh, India ankubala01@gmail.com

Abstract: Addition is the fundamental operation in any digital system. The propagation time is more in addition due to large time required for the carry bits.A carry look ahead adder improves the speed by reducing the time required to solve carry bits. It is mostly used in electronics devices. An efficient implementation of two bit carry look ahead adder is proposed using fully automatic and semi-custom design steps. This paper is a comparison of complexity of automatic generated design against semi-custom design. A two bit CLA adder was designed in 90nm low power high speed technology. The performance of the CLA is measured by comparing the results in terms of power dissipation and area efficiency.

Simulation results showed 56% gain in power and 28% in Area.

I. INTRODUCTION VLSI technology is used where we can design complex system like Analog or Digital circuit on single chip[1]. In devices for example Laptops, cellphones power consumption become major concern in designing. Due to limited power the circuitry involved must be designed such that they consume less power because large power consumption requires expensive cooling circuitry[2]. The major issue of concern is heat dissipation and power consumption in any circuit[3].Addition is the widely used arithmetic operation and also time consuming. Addition is the speed limiting factor to processors. As far as we are concern with high performance and speed of the process we have to increase the speed of the addition[4].

Adders are very significant components in digital systems because they are widely used in basic digital operations for example Subtraction, Multiplication and Division, hence increasing the performance of adder would advance the execution of binary operation inside a circuit[5].

High speed adders include the Carry look Ahead Adder, Carry select Adder, Carry Skip Adder and combination of these. In high speed adders the basic principle of CLA adder is dominant, only the delay of carry can be improved[6].Carry look ahead adder’s speed is usually determined by the lowest carry path delay. Its path is data dependent. Basic carry look ahead principle was developed by Weinberger and Smith [7]. In this paper, I represent two approaches one is fully automatic approach and the other is Semi-custom approach [8].

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These two approaches are executed using VLSI simulation tools. I made a comparison between automatic generated CLA adder and semi-custom using DSCH and Micro-wind that how we can reduce the area and power consumption. The power can be consumed and area can be reduced using Semi-custom design because the designer can create compact design which uses less area and less power for its working. Simulation is done with 90nm technology to determine area and power dissipation. The performance of CLA adder using semi-custom design is compared with Automatic generated CLA adder.

The rest of the paper is organized as section II describes the basic concept and building block equations for CLA and basic logic gates used in designing of CLA. Section III describes its block diagram and the circuit diagram using gates. Section IV describe the detailed simulation results and their discussion. The conclusion of the paper is in section V. II. CLA ADDER In this section basic design structure of CLA has been discussed. The CLA adder uses the concept of generating and propagating the carry bit [8]. Table 1 shows the addition of two 2 bit numbers and initial carry is taken as 1(high) and after addition the final carry is one.

Table No 1- Addition of two 2 bit CLA adder

C =1 A

A

1

0

B

B

1

1

C

S

S

1

1

0

2

3

6

The expression for carry propagate P as shown in equation (1), carry generate G in equation (2), sum expression S in NITTTR, Chandigarh EDIT-2015

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

equation (3) and carry out C in equation (4) is below. ⊕, . and +shows the Exclusive OR operation, AND operation and OR operation respectively [8].

P = A ⊕B

..(1)

G = A .B

..(2)

S =A ⊕B ⊕C

..(3)

C = [A ⊕ B ]. C + [A . B ]

..(4)

The logic equations describing the carry out signals generated per bit position shows that these signals are generated in parallel. It is apparent that each carry bit is generated independent of the previous carry and the sum bit depends on the value of the previous carry bit. In look ahead carry adder, carry is generated in parallel by using look ahead carry circuit. Look ahead carry circuit contains two level AND-OR circuit.

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

all one bit adder using CLA equations stated above is designed. One symbolhas been created and this symbol is used for next bit addition.

Fig.3 Block diagram of CLA adder

The basic block diagram using symbol created in DSCH is shown in fig 3. The symbol has three inputs A0, B0 and Cin and two outputs sum and carry. The symbol consists of XOR gate, AND gate and OR gate to generate the sum and carry bits. The expanded view of the symbolis shown in fig 4.

Fig. 4Expanded view of symbol

IV. LAYOUT RESULT & DISCUSSION Fig.1 CLA using Full adder

Fig 1 shows the CLA adder using two 1-bit full adders.

The output of full adder is carry propagate, carry generate and the sum of respective bits. The carry propagate and carry generate bits are given to the carry look ahead adder and the final carry is generated by CLA generator. The basic logic gates used in this CLA adder is Exclusive OR gate, AND gate and OR gate. The fig 2 shows CLA adder using logic gates. Ain and the bin are the bits to be added and cin is taken as any previous carry input and si, gi and pi is generated

In this section all the simulated results ofcarry look ahead adder using fully automatic and semi-custom design are given. When A0, B0 and Cin are high then the sum will be high and also the carry will be generated. Table 2 shows the truth table of binary addition.

Table 2: Truth Table

Ai

Bi

Ci

Sum

Carry

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Fig.2 CLA Adder using logic gates

III. CLA ADDER SCHEMATIC In fully automatic design approach, DSCH is used to create the transistor level circuit of CLA adder. In DSCH, first of NITTTR, Chandigarh EDIT -2015

Timing diagram of the CLA adder satisfying above truth table using fully automatic design step in DSCH is shown in fig 5.

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

approach is better. Here, by using semicustom approach the area has been very much reduced as compare to fully automatic. Fig 9 shows the simulation results of semicustom design, which is almost same as of fully automatic.

Fig.5 Timing diagram of fully automatic in DSCH

The next step in fully automatic design is to generate layout what has been done in DSCH by compiling Verilog file in micro-wind. The Verilog file is created from DSCH. It consists of information like no to transistors used, W/L ratio, connections etc. The auto generated layout of two bit CLA adder in micro-wind is shown in fig 6.

Fig. 9 Timing diagram of Semi-automatic

The comparison of CLA adder using fully automatic and semi-custom is done by channel length 90nm technology as shown in Table 3. Power dissipation, area is calculated and compared.

Table 3: Comparison of fully automatic and semicustom design Fig.6 Auto-generated layout in micro-wind

The simulation of Auto generated layout is shown in fig 7.

Parameters

Fully Automatic

Semi-custom

Power

215.3

95.2

685.3

195.5

(10

) )

Area (

Fig. 7 Timing diagram of automatic generated layout

In semi-custom design, the layout is made directly. NMOS and PMOS transistors are used to create gates and then combine the gates as per the equations used for CLA adder.

In this approach, one can reduce the area used for designing as well as power can be reduced.The semicustom layout of CLA adder is shown in fig 8.

Fig 10 shows the comparison graph of Area and Power in Semi-custom and Fully automatic.

1000

Semicustom

500

Fully automatic

0 Power Area

Fig. 10 Comparison of Area and Power

By comparing the area used in semicustom and fully automatic design, we can come to conclusion about which

V. CONCLUSION Comparative Performance Analysis of different approaches of CLA has been carried out by this work. Automatic design gives us high power consumption and large area but semicustom design gives low power consumption and small area occupied. The proposed Carry Look Ahead Adder was designed using semi-custom design and the power has been reduced upto 44% as compared to fully automatic and area has been also reduced upto 28 %.

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Fig.8 Semi-custom layout

EDIT-2015

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

REFERENCES [1] Shilpa Thakur, Rajesh Mehra, “CMOS Design And Single Supply Level Shifter Using 90nm Technology”, Conference on Advances in Communication and Control Systems 2013, pp-150-153, 2013.

[2] Richa Singh and Rajesh Mehra,“Power Efficient Design Of Multiplexor Using Adiabatic Logic”, International Journal of Advances in Engineering & Technology, Issue-1, vol-6, pp246-254, Mar 2013.

[3] Pooja Singh and Rajesh Mehra,“ Design Analysis of XOR Gates Using CMOS & Pass Transistor Logic”, National Student Conference On “Advances in Electrical & Information Communication Technology”AEICT-2014, pp 264-267.

[4] Costas Efstathiou, ZaherOwda, and YiorgosTsiatouhas, “New HighSpeed Multioutput Carry Look-Ahead Adders” IEEE Transactions on circuits and systems-II: Express briefs, VOL. 60, NO. 10, Issue 10, pp 667-671, Oct 2013.

[5] R.Uma, VidyaVijayan, M. Mohanapriya, Sharon Paul, “Area, Delay and Power Comparison of Adder Topologies” International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, pp 153-168, Feb 2012 [6] Javali, Ravikumar A,Ramanath J ; Mhetar, Ashish M ; Lakkannavar, Manjunath C, “Design of high speed carry save adder using carry lookahead adder” , IEEE International conference on Circuits, Communication, Control and Computing (I4C), ISBN 978-1-47996545-8, pp 33 – 36, Nov. 2014 [7]Andreas Herrfeld and SiegbertHentschkeInstitut fir PeriphereMikroelektronik, “Ternary Multiplication Circuits Using 4Input Adder Cells and Carry Look-Ahead” 29thIEEE International Symposium pp174-179.

[8] JagannathSamanta, Mousamhalder, Bishnu Prasad De, “Performance Analysis of High Speed Low Power carry Look Ahead Adder Using Different logic Styles”, International Journal of soft computing and engineering(IJSCE) ISSN:2231-2307, Volume-2, Issue-6,pp 80-88, Jan 2013.

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