Optimization for Minimum Noise Figure of RF Low Noise Amplifier in 0.18µm Technology by IJEEE (Elixir Publications)

Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Optimization for Minimum Noise Figure of RF Low Noise Amplifier in 0.18µm Technology Minaxi Dassi1 and Rajnish Sharma2 Department of Electronics and Communication, Chitkara University, Himachal Pradesh, India 1

minaxi.dassi@chitkarauniversity.edu.in rajnish.sharma@chitkarauniversity.edu.in

Abstract – Using a modified Cascode topology a 2GHz Low Noise Amplifier (LNA) has been implemented in Cadence Spectre RF tool on UMC 0.18µm technology to work under reduced power supply. After simulation it is found that at resonance frequency of 2GHz, the minimum noise figure is 2.5 dB and noise figure is 3 dB for a voltage gain of 17 dB. Key Words:-RF circuit design, Low Noise Amplifier, 0.18µm technology.

I. INTRODUCTION Today wireless communication is as ubiquitous as electricity. At present no wireless device is incorporated in our ovens and refrigerators, but it is envisioned that a wireless network will eventually be incorporated in our homes that will control every device and appliance. Flawless connections among our laptops, camcorders, cell phones, printers, digital cameras, TVs, microwave ovens, etc will be possible due to High-speed wireless links for example Wi-Fi and Bluetooth connections. The main reason for the recognition of wireless communication is the –decrease in the cost of electronics. Today’s cell phones offer many more functions and features: communication modes and many frequency bands, Wi-Fi, Bluetooth, storage, a digital camera, GPS, computing, and a userfriendly interface at about the same cost as those a decade ago. With the help of integration much more functional devices can be positioned on a single chip. The integration, in turn, is responsible for its steady rise to (1) innovations in RF architectures, circuits, and devices and (2) the scaling of VLSI processes in CMOS technology. With the higher integration levels there is improvement in the performance of RF circuits. For example, the speed of RF circuits for a given function has increased with the decrease in the power consumption. II. CHALLENGES IN RF DESIGN The design and implementation of transceivers and RF circuits remained very challenging irrespective of many decades of research work on microwave theory, RF and on RF ICs [1]. There are three reasons for this condition. Firstly, RF design draws upon a huge number of disciplines and requires a good understanding of fields that seems irrelevant to integrated circuits as shown in Fig 1. For more than half a century most of these fields have been under research and study, presenting a enormous knowledge required by a person to enter RF IC design.

Fig1: Various disciplines necessary in RF design [1]

Secondly, there are numerous trade-offs, summarized in the “RF design hexagon” as shown in Fig 2 that RF circuits and transceivers must deal with. For example, for a front end amplifier in order to decrease the noise we need to consume the greater power or sacrifice linearity. Power

Noise

Linearity

Frequency

Supply Voltage

Gain Fig. 2 RF design hexagon [1]

Third, there are new challenges to meet the demand for lower cost, higher performance, and greater functionality. In 1990s, the early work on RF IC design strove to integrate on a single chip only one transceiver with the digital baseband processor. On the other hand, today’s efforts aim to accommodate on a single chip multiple transceivers operating in various frequency bands for multiple wireless standards (e.g., Wi-Fi, Bluetooth, GPS, etc.) [2] and [3]. Earlier RF and analog designers had some freedom in the choice of their device and circuit topologies since the silicon chip area of single-transceiver systems was dominated only by the digital baseband processor. But in today’s designs, RF and analog sections need to be designed with much care regarding their area consumption. For example, on-chip spiral inductors were utilized in abundance in older systems, but they are now used only scarcely. In the communication system, Low noise amplifier is the NITTTR, Chandigarh

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Int. Journal of Electrical & Electronics Engg.

Vol. 2, Spl. Issue 1 (2015)

second element after antenna which is used to raise the strength of the weak information signal noise suppression. So, noise figure (NF) is the key issue of concern in this design. Matching of each block of the receiver is also an important issue in order to provide maximum power transfer at a particular frequency the matching is required. Furthermore, input and output matching to the source and load can maximize the gain. Input and output impedance matching is characterized by the input and output return loss. Since, it can affect the performance of the device. The gain should be large enough and the same time noise should be as less as possible. However, the gain of LNA should not be too high otherwise in the following stages, mixer is saturated. The LNA should present specific impedance at the input, e.g. 50 Ω to interface with the filter or antenna. III. NOISE OPTIMIZATION METHODS In low noise amplifier design, determination of the minimum noise figure is a common and well-understood procedure. Typically, a small-signal model of the amplifier is assumed, an expression for F is formed and differentiation leads to the unique conditions for optimized noise performance [3]. In the noise optimization techniques we seek the conditions that guarantee optimized noise performance for a specified fixed design parameter, such as gain or power consumption, under the condition of perfect input matching. Now, we fix the necessary design criteria and determine the appropriate small-signal model through the optimization procedure. Because the architecture permits selection of QL and LS independently, so we can optimize the noise performance that coincides with the input match. There are two approaches for the optimization of noise figure. The first assumes a fixed transconductance, Gm, for the amplifier. The second assumes fixed power consumption. We know the equation of noise figure is [4] = 1+

(1)

To illustrate these approaches, the expression for F in “(1)”, can be recast to make its dependance on power dissipation (PD). From “(2)”, it is clear that condition for constatnt Gm is equivalent to the condition of constatn ωT G =g Q = = = ( )

(2) To maintain a fixed ωT, we need to fix the value of ρ. Hence we will formulate F in terms of PD and ρ to facilitate both optimizations. The equation of F in terms of PD and ρ is given below = 1+ ( , ) (3)

In this equation the gate resistance and inductor losses to the noise factor have been neglected. In the above “(3)”, ( , ) is the ratio of two sixth-order polynomials of ρ given by ( ,

With,

( )

(

)

( ) = (1 + ) + ( ) = 2| |

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( )

(1 + )

(4)

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e-ISSN: 1694-2310 | p-ISSN: 1694-2426

( )=

( ) 1+ 5 2 Because F is a function of two variables, one can define contours of constant noise figure in and PD. “(3)” suggests that optimization of proceeds by minimizing with respect to one of its arguments, keeping the other one fixed. To fix the value of the transconductance, Gm, we need only assign a constant value to ρ. We know, =

(5)

The appropriate value for Gm is easily determined by substituting “(5)” in to the expression for as found in “(2)”. The value of Gm relates to ρ is =

(

(6)

)

Once ρ is determined, we can minimize the noise factor by taking ( , ) =0 (7) ( ) Which, after some algebraic manipulations result in ,

( ) = ( )

(8) The expression gives the power dissipation which yields the best noise performance for a given Gm under the assumption of matched input impedance. The value of QL is =

(

(9)

)

By comparing “(8)” to”(9)”, the optimum occurs when =

≥ 1.87

(10)

Hence the best noise performance for a given transconductance is achieved at some specific input. The of 1.87 is only valid for the long channel devices. For short channel lengths, where α < 1, we can expect the optimum QL to be somewhat larger. By substituting”(10)”in to “(1)”, we can determine that the minimum noise factor (neglecting inductor and gate losses) is =1+

1.33

| |+ 1+

≥1+

(11) The value of 1.33 is only valid for long channel devices; it may be three to four times larger in the presence of high electric fields. An alternate method of optimization fixes the power dissipation and adjusts ρ to find the minimum noise factor. If we assume that α < < 1, then P (ρ, PD) can be simplified to: (ρ, P ) = ( , (

+ 2| |

ρ +

(12)

This expression is minimized for a fixed PD when )

)

(13)

The solution of this equation under the assumption that α ≪ 1 is : ,

| |

1+ 1+|

(14)

By comparing “(14)” t0 “(9)”, it is that this value for ρ is equivalent to an optimum QL of 26

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=| |

1+ 1+|

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= 3.9

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

(15)

So it is clear that the optimum QL for fixed power dissipation is larger than the optimum QL for a fixed Gm. From these equations ,

= 1 + 2.4

â&#x2030;Ľ 1 + 1.62

(16)

Where the value of 1.62 is valid only in the long channel limit; the value will be somewhat larger for short- channel devices in velocity saturation. IV. TEST BENCH FOR SINGLE ENDED LNA AND SIMULATION RESULTS Transducer Power Gain (GT) It is defined as the ratio of the power delivered to the load and the power available from the source. =|

(17)

Operating Power Gain (GP) It is defined as the ratio of the power delivered to the load of the network and the power input to the network. = | | | | (18) Available Power Gain (GA) It is defined as the ratio of the power available from the network and the power available from the source. =| | (19) | |

Fig 4 Schematic for Single Ended LNA In CADENCE VIRTUOSO

Because the power available from the source is greater than the power input to the LNA network GP > GT. The closer the two gains are, the better the input matching is. Similarly, because the power available from the LNA network is greater than the power delivered to the load, GA > GT. The closer the two gains are, the better the output matching is. The test bench for single ended LNA is shown in Fig. 3 and the schematic for the same is shown in Fig. 4.

Fig 5 NF plot for single ended LNA

Fig 3 Test bench for Single Ended LNA

Fig 6 NFmin Plot for single ended LNA

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[7]

[8]

[9]

[9] [10]

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Jeonghoon Lee, Youngsik Kim, “A 1.8 Fully Differential CMOS Low Noise Amplifier with a special care for Mixer Input Stage”, IEEE SIRF, pp 178 – 181, 2006 Hafez Foud, Khaled Sharaf, Essael-Diwany and Hadia ElHennawy, “An RF CMOS modified Cascode LNA with Inductive Source Degeneration”, In Proceedings of nineteenth National Radio Science Conference, pp. 450-457, March 2002. W.R.Liou, C.A. Tsai, M.L. Yeh and G.E. Jan, “A 5.2 GHz low-voltage Low-Noise amplifier with 0.35µm CMOS technology”, International Journal Of Electronics, vol.91, No. 9, pp. 551-561, September, 2004. Pranjal Rastogi, J. Karthik and Rajnish Sharma, “Design of an RF CMOS LNA using 0.25 micron technology”, VDAT. Thomas H. Lee and S. Simon Wong, “CMOS RF Integrated Circuits at 5GHz and Beyond”, In Proceedings of IEEE, Vol.88, No.10, October 2000

Fig 7 GT, GP, GA plot for

Fig 8 VSWR PLOT for single ended LNA

V. CONCLUSION The single ended LNA is simulated in CADENCE VIRTUOSO environment and after certain iterations the value of noise figure is found to be 3 dB as shown in Fig 5 and using the noise optimization technique the minimum noise figure is found to be 2.5 dB as shown in Fig 6.The gain plots are shown in Fig 7 and in Fig 8 the VSWR plot is shown. References [1] Behzad Razavi, RF MICROELECTRONICS, 2nd ed., Prentice Hall Publications, [2] T. Yamawaki et al., “A 2.7-V GSM RF Transceiver IC,” IEEE J. Solid-State Circuits, vol. 32, pp. 2089–2096, Dec. 1997. [3] Derek K. Shaeffer and Thomas H. Lee, “A 1.5V, 1.5 GHz CMOS Low Noise Amplifier”, IEEE J. Solid-State circuits, Vol. 32, pp. 745-759, May 1997. [4] Trung-Kein Nguyen, Chung-Hwan Kim, Gook-JuIhm, MoonSu Yang and Sang-Gug Lee, “CMOS Low-Noise Amplifier Design Optimization Techniques”, IEEE Transactions On Microwave Theory And Techniques,Vol.52,No.5,pp.14331441,May 2004 [5] M. Sumanthi and S. Malarvizhi, “Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18 µm technology scale”, International Journal of VLSI design & Communication Systems ,Vol.2, No.2, pp.June 2011. [6] Tajinder Manku, “Microwave CMOS – Devices and Circuits”, IEEE Conference in Custom Integrated Circuits, pp. 59-66, 1998

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