Ijeee v1i1 06

IJEEE, Vol. 1, Issue 1 (Jan-Feb 2014)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

OPTIMIZATION: MVSIS V/S AIG REWRITING (ABC) Manish Kumar Goyal Deptt. Of Electronics Engineering, Govt. Polytechnic College, Alwar, Rajasthan, India manishbmgoyal@gmail.com

Abstract- For the optimization of given network, VHDL /Verilog code convert into BLIF / BLIF_MV (Berkeley Logic Interchange Format /Berkeley Logic Interchange Format for multi-valued network ) format with the help of VIS / Vl2mv tool of Berkeley. In this paper, we optimize on a number of standard industrial benchmark circuit by MVSIS and ABC tool. After optimization here used some technology mapping, then compare the result. Here we try to find which tool give optimal result of optimization.

Index Terms- And-Inverter graph (AIG), Direct Acyclic Graph (DAG), Hardware Description Language (HDL), VHSIC Hardware Description Language (VHDL) I. INTRODUCTION Optimization of binary or multi-valued logic networks using logic synthesis play an important role in a digital network system [1].

Network Toplogy Reading (VHDL/ Verilog - BV/MV)

BLIF / BLIF_MV Conversion (VIs / Vl2mv)

Technology Independent Optimization (SIS / MVSIS / ABC)

Application of Mapping Algorithm (SIS / MVSIS / ABC)

Result Analysis

Logic synthesis is used on a network which is derived by compiling HDLs, VHDL or Verilog. Then technology mapping performed for standard cell or programmable devices. Logic synthesis is also fruitful for hardware emulation, design complexity estimation, software synthesis, and fast preprocessing of the circuits before equivalence checking [2]. Figure-1 shows the process to get optimize result by MVSIS and ABC tool.

II. MVSIS MVSIS is a sequel program modeled of SIS. MVSIS is technology independent transformation of combinational as well as sequential logic system. It works on is such that all variables can be multi-valued, each with its own range [7].

MVSIS input formats can be 1. PLA or BLIF : For Binary functions and networks 2. BLIF-MV: For Multi-valued functions and networks And for FSMs and finite automata available

three options are

1. Using BLIF/BLIF-MV followed by “stg_extract�

2. Using modified KISS2 format 3. Using modified BLIF-MV format To analyze the performance of this tool, script is applied over 15 combinational MCNC benchmark circuit. In MVSIS script logic synthesis is a sequence of applying optimization steps i.e. SWEEP (For removing redundant nodes), ELIMINATE and RESUBSTITUTE (For finding better logic boundaries), FAST_EXTRACT (For discovering shared logic boundary) and SIMPLIFY and FULL_SIMPLIFY (For simplifying the node representation).[3] In the Table-1, the first column shows the 15 standard combinational MCNC benchmark circuit [4]. Next seven columns show the statics of the benchmark circuit before applying the standard script. Here, PI is the number of primary inputs; PO is the number of primary output, while Lits indicate the literals. The next section of the table shows, the reduced number of node, level, cubes, literals and literal(ff) after run MVSIS (script) over the benchmark.

Figure-1: Design Flow

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TABLE-1 STATICS OF BENCHMARK CIRCUIT BEFORE AND AFTER APPLYING THE MVSIS script

Bench-Mark Circuit Duke2 Rd84 Misex2 B12 Cordic Pdc Spla C432 C1355 C1908 T481 B9 Dalu Des K2

Circuit Statics PI PO Node 22 29 385 8 4 495 25 18 123 15 9 769 23 2 2079 16 40 2326 16 46 2237 36 7 355 41 32 949 33 25 798 16 1 1075 41 21 275 75 16 2609 256 245 2263 45 45 399

Level 8 9 6 9 12 17 18 29 44 55 11 20 59 10 4

Cubes 590 894 134 1214 3283 4203 4128 373 949 798 1555 351 3595 3957 1521

Lits 992 1442 246 1860 4969 8259 7961 567 1467 1245 2673 408 4541 8991 3176

Lits(ff) 992 1442 246 1860 4969 7364 7034 567 1467 1245 2673 408 4541 8991 3176

After Run MVSIS ( script) Node Level Cubes Lits 362 8 772 898 495 10 1115 1278 83 5 156 189 110 7 229 279 1500 13 3414 4163 3528 14 7821 10046 3424 13 7393 9173 173 19 341 442 220 10 428 684 274 18 566 795 783 11 1945 2314 98 6 175 220 743 15 1507 1962 3823 12 7758 9864 1368 10 2850 3409

Lits(ff) 890 1249 186 269 3909 9140 8578 390 678 771 2142 204 1805 9453 3366

TABLE-2 DEGREE OF REDUCTION IN NODE AND LITERAL

BenchMark Circuit Duke2 Rd84 Misex2 B12 Cordic Pdc Spla C432 C1355 C1908 T481 B9 Dalu Des K2

Circuit Statics Node 385 495 123 769 2079 2326 2237 355 949 798 1075 275 2609 2263 399

Literal 992 1442 246 1860 4969 8259 7961 567 1467 1245 2673 408 4541 8991 3176

After MVSIS (Script) Node Literal 362 898 495 1278 83 189 110 279 1500 4163 3528 10046 3424 9173 173 442 220 684 274 795 783 2314 98 220 743 1962 3823 9864 1368 3409

Table-2 shows the degree of reduction in benchmark circuit. Here B12 circuit have maximum degree of reduction in node as well as literal is 0.857 and 0.850 respectively. In some of the benchmarks, i.e. PDC, SPLA, DES and K2, number of node and literals are increased, but area is reduce

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Degree of reduction Node 0.060 0 0.325 0.857 0.278 (-)0.517 (-)0.531 0.513 0.768 0.657 0.272 0.644 0.715 (-)0.689 (-)2.429

Literal 0.095 0.114 0.231 0.850 0.162 (-)0.216 (-)0.152 0.220 0.534 0.386 0.134 0.461 0.562 (-)0.097 (-)0.073

as shown in the Table-3. Table-3 shows the degree of area reduction and delay reduction when benchmark circuits mapped with mcnc.genlib. And, also show area optimization with LUT (#K=5).

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TABLE-3 ANALYSIS OF AREA AND DELAY BEFORE AND AFTER OPTIMIZATION

BecnchMark Circuit Duke2 Rd84 Misex2 B12 Cordic Pdc Spla C432 C1355 C1908 T481 B9 Dalu Des K2

Mapping with mcnc.genlib Before MVSIS After MVSIS script script Area Delay Area Delay 978 9.3 896 9.3 1437 10.7 1249 11.2 205 6.2 186 6.6 1501 10.4 270 8.4 6384 14.3 3918 15.5 10209 17 9193 16.7 9534 16 8599 15.9 380 19.9 394 21.8 816 15.6 788 15.9 852 24.1 844 23 2524 13.3 2147 13.3 229 7.2 205 6.7 2828 24.6 1847 18 11362 11.6 9562 13.7 3646 11.8 3409 12.1

Degree of Area Reduction 0.084 0.131 0.093 0.820 0.386 0.100 0.098 (-)0.037 0.034 0.009 0.149 0.105 0.347 0.158 0.065

III. AIG REWRITING (ABC) An And-Inverter graph (AIG) is a direct acyclic graph (DAG). In which node has either 0 or 2 incoming edges. If a node will have no edge then it will primary input (PI) or if node has twoinput edges then it will two-input AND gate.

An edge become a normal input or complement of input.

Some node will primary output (PO). Another logic synthesis tool is ABC. In which And-Inverter Graphs (AIGs) can be rewrite for given network. Rewriting is a fast greedy algorithm[2]. This is used for minimizing the AIG size by iteratively selecting AIG sub-graphs rooted at a node and replacing them with smaller pre-computed sub-graphs, while preserving the functionality of the root node. rewriting algorithm is developed with following features: 1. Using 4-feasible cuts instead of two-level sub-graphs.

2. Restricting rewriting to preserve the number of logic levels.

3. Developing several variations of AIG rewriting to 4. Selectively collapse and refactor larger sub-graphs.

5. Balance AIG using algebraic tree height reduction

Delay Reduction

Mapping with LUT #k=5 Area Before Area After optimization optimization

Degree of reduction

0.0 (-)0.5 (-)0.4 2.0 (-)1.2 0.3 0.1 (-)1.9 (-)0.3 1.1 0.0 0.5 6.6 2.1 (-)0.3

220 275 42 299 647 1824 1839 80 68 114 410 42 382 1491 722

0.059 0.124 0.190 0.719 0.148 0.101 0.139 0.363 0.0 0.061 0.163 0.048 0.277 0.107 0.036

207 241 34 84 551 1639 1583 51 68 107 343 40 276 1332 696

In the AIG rewriting, the nodes are visited in a topological order. For each 4-input cut of a node, all precomputed sub-graphs of its NPN class are considered. Logic sharing between the new sub-graph and nodes already in the network is determined. First old sub-graph is dereference and the number of nodes, whose reference counts became 0, is returned [6]. These nodes will be removed if the old subgraph is replaced. Next, a new sub-graph is added while counting the number of new node and the node whose reference count went from 0 to a positive value. These nodes will add. The difference of the counter is the gain in the number of nodes if the replacement is done. The new node is de-referenced and the old node is referenced to return the AIG to its original state.

After trying all available sub-graphs for the given node, the one that leads to the largest improvement at a node is used. If there is no improvement and “Zero-Cost replacement� is enabled, a new sub-graph that does not increase the number of nodes is used. Table-4 shows the reduction in node with every iteration. Table-5 shows the reduction in area and delay when technology mapped by mcnc.genlib.

TABLE-4 REWRITING PERFORMANCE OF MCNC BENCH MARK

Bench Mark Circuit Duke2 Rd84 Misex2 B12 Cordic Pdc Spla C432 C1355 C1908

First Iteration (rwz) Node Gain Rewritten 274 57 224 71 45 12 632 246 1164 1785 2397 208 2195 165 99 31 220 100 125 31

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% Gain 10.59 9.97 10.17 25.13 64.37 4.16 3.46 14.62 19.53 7.54

Second Iteration (rwz) Node Gain % Gain Rewritten 221 30 6.24 213 30 4.68 36 4 3.77 401 114 15.55 310 125 12.65 2082 208 4.34 1904 219 4.76 65 14 7.73 59 18 4.37 74 8 2.11

Third Iteration (rwz) Node Gain Rewritten 203 19 201 22 36 1 342 67 242 69 1930 116 1767 109 48 9 54 0 70 2

% Gain 4.21 3.60 0.98 10.82 8.00 2.53 2.49 5.39 0.0 0.54

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T481 B9 Dalu Des K2

521 36 714 2003 1470

514 28 571 993 458

37.11 23.14 32.91 20.99 20.01

262 25 311 1128 1055

121 7 53 245 104

13.89 7.53 4.55 6.55 5.68

193 19 249 842 921

55 2 14 47 38

7.33 2.33 1.26 1.35 2.20

TABLE-5 ANALYSIS OF ABC WITH MCNC.GENLIB

Bench Mark Circuit Duke2 Rd84 Misex2 B12 Cordic Pdc Spla C432 C1355 C1908 T481 B9 Dalu Des K2

Before ABC script.scr Node Net Area Delay

After ABC script.scr Node Net Area

Delay

Degree of reduction Node Net Area

Delay

392 511 83 654 1970 3825 3712 185 218 296 920 99 1089 3687 1411

353 497 80 387 1139 3389 3269 152 200 288 753 87 848 3243 1236

9.3 11.3 5.8 10.2 14.7 16.4 15.9 20.5 14.1 24.3 13.6 7.0 20.8 12.2 12.1

0.099 0.027 0.036 0.408 0.422 0.114 0.119 0.178 0.083 0.027 0.182 0.121 0.221 0.120 0.124

(-)0.1 (-)1.6 0.4 0.2 (-)0.4 0.8 0.3 1.4 1.5 0.2 (-)0.3 0.8 3.6 0.5 0.3

959 1449 195 1786 6464 9558 9221 404 480 677 2558 216 2578 9423 3536

966 1452 195 1786 6465 9592 9250 405 816 902 2566 217 2808 9718 3581

9.2 10.7 6.2 10.4 14.3 17.2 16.2 21.9 15.6 24.5 13.3 7.8 24.6 12.7 12.4

830 1237 180 1011 2982 8665 8175 338 431 648 1993 181 1980 8210 2997

IV. ANALYSIS OF OPTIMIZATION This section compares AIG rewriting in ABC with logic synthesis in MVSIS on MCNC benchmark. Table-6 shows that Node reduction with MVSIS (script) and ABC (resyn2), and also shows that area and delay reduction of

835 1239 180 1011 2991 8694 8201 348 769 863 1999 182 2080 8518 3053

0.135 0.146 0.077 0.434 0.539 0.093 0.113 0.163 0.102 0.043 0.221 0.162 0.232 0.129 0.152

0.136 0.147 0.077 0.434 0.537 0.094 0.113 0.141 0.058 0.043 0.221 0.161 0.259 0.123 0.147

mapping of optimize benchmark, which shows it is better in ABC. ABC (resyn2) based on area optimization under delay constraints. Therefore in some benchmarks delay is increased as compare to MVSIS (script).

TABLE-6 COMPARISON BETWEEN MVSIS AND ABC

Bench Mark Circuit Duke2 Rd84 Misex2 B12 Cordic Pdc Spla C432 C1355 C1908 T481 B9 Dalu Des K2

Degree of Reduction in Node Area 0.060 0.084 0 0.131 0.325 0.093 0.857 0.820 0.278 0.386 (-)0.517 0.100 (-)0.531 0.098 0.513 (-)0.037 0.768 0.034 0.657 0.009 0.272 0.149 0.644 0.105 0.715 0.347 (-)0.689 0.158 (-)2.429 0.065

V. CONCLUSION AIG rewriting is an innovative technique for combinational logic synthesis. This experiment shows that AIG rewriting often leads to quality comparable or better than those afforded by the logic synthesis script in MVSIS. The extreme speed and good quality of the proposed algorithm might make the new flow useful in a variety of

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MVSIS Delay 0.0 (-)0.5 (-)0.4 2.0 (-)1.2 0.3 0.1 (-)1.9 (-)0.3 1.1 0.0 0.5 6.6 2.1 (-)0.3

Degree of Node 0.099 0.027 0.036 0.408 0.422 0.114 0.119 0.178 0.083 0.027 0.182 0.121 0.221 0.120 0.124

Reduction in ABC Area Delay 0.136 (-)0.1 0.147 (-)1.6 0.077 0.4 0.434 0.2 0.537 (-)0.4 0.094 0.8 0.113 0.3 0.141 1.4 0.058 1.5 0.043 0.2 0.221 (-)0.3 0.161 0.8 0.259 3.6 0.123 0.5 0.147 0.3

applications such as hardware emulation, estimation of design complexity, and equivalence checking.

REFERENCE [1]. ‘Optimization of Multi-Valued Multi-Level Networks’- M.Gao, J-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa and R. Brayton; 32nd IEE International Symposium on Multiple-Valued Logic (ISMVL’02

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[2]. ‘DAG-Aware AIG Rewriting – A Fresh Look at combinational Logic Synthesis’ – Alan Mishchenko, Satrajit Chatterjee, Robert Brayton; DAC 2006 [3]. ‘Minimization of Multiple Valued Functions in Post Algebra’ – Elena Dubrova, Yunjian Jiang, Robert Brayton [4]. ‘Logic Synthesis and Optimization Benchmarks User Guide- Version 3.0’ - Saeyang Yang [5]. ‘Multi-Valued Logic Synthesis’ Robert K Brayton, Sunil P Khatri [6]. ‘ Quick Look under the Hood of ABC – A Programmer’s Manual’ [7]. http://www.eecs.berkeley.edu

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