IJEEE, Vol. 1, Issue 4 (August, 2014)
e-ISSN: 1694-2310 | p-ISSN: 1694-2426
DESIGN & ANALYSIS OF MODIFIED SHANNON BASED LOW POWER CONSUMPTION FULL ADDER CELL 1
Rupali Gupta, 2Rajesh Mehra
1,2
Department of ECE, National Inst. Of Technical Teachers’ Training & Research, Chandigarh, India 1
rupaligupta2005@gmail.com, 2rajeshmehra@yahoo.co.in
Abstract—The basic building block of any computational circuit is adder which affects the performance of the system so there is a need for an adder with low power dissipation and small area. In this paper a high performance, low power dissipation full adder cell is designed using Shannon theorem. The hardware includes a four bit 2`s compliment adder/subtractor using proposed full adder. The adder is optimized using transistor sizing technique. Simulations were performed using Microwind3.1 VLSI CAD tool and schematic is generated by using DSCH3.1 CAD tool. After optimization for parameter analysis BSIM4 analyzer is used at 90nm deep submicron technology. Simulation results show a large improvement in power consumption and more than 50% improvement in transistor count than other existing full adder circuits. Index Terms- Adder cell, power dissipation, Shannon theorem, transistor count, VLSI. I. INTRODUCTION With the explosive growth of the use of portable and multimedia devices, laptops and mobiles and with the shrinkage of the size of electronic devices the demand of low power very large scale integration (VLSI) system has become very high. Since the increase in chip density increases the power consumption also. The power has become the major concern for research in the area of VLSI design. In recent trends a large no of portable devices needs small area, low power and high speed circuits. Addition is the fundamental arithmetic operation which is used in most of the data path circuits for different arithmetic operations like multiplication, division and ALU operations etc. Hence the adder design should be efficient enough to give the better results with respect to the quality design constrains like low power, small area and fast speed. In past decades full adder cell has been designed using many logic styles like PTL.MUX based, transmission gated logic style and CPL etc. Each logic style has its own merits and demerits in terms of delay and power. Among many logic styles pass transistor logic has several merits. In this style gate and source both propagates the signal with great functionality. PTL can be designed using nMOS or p-MOS only with reduced transistor count and area [1]. PTL have low interconnect capacitance so high speed can be achieved. In this paper full adder has been designed using PTL logic style and compared with the existing circuits. www.ijeee-apm.com
II. FULL ADDER ARCHITECTURE The basic cell component of any data path circuit is full adder. It is a digital circuit which performs the addition of two numbers i.e. one of the four basic arithmetic functions. According the application the number of the inputs may vary. So according to the no. of inputs there are two types of adders as Full adder and Half adder. The addition of two bits can generate a carry so a Full adder has three inputs as A, B and Ci and two outputs as Sum and Carry. Here Ci is the previous carry which may be generated from the addition of the previous two bits. It performs the addition of three inputs as Sum= A xor B xor C (1) Carry=AB+BC+CA (2) Figure 1 shows the gate level circuit of a full adder. The truth table of a full adder can be obtained from the binary arithmetic operations. A full adder can be implemented using CPL which uses n- MOS network for implementing the logic function. This logic style has least power consumption per gate during logic transition. The CPL has many drawbacks due to source follower action and body effect, limited fan out and high leakage power when not cross coupled.
Figure 1. Full Adder using half adder
The MCIT technique is developed by using Karnaugh map from the Boolean Expression for sum and carry signals from the standard truth table for the full adder circuit [2]. The Boolean expressions are given by equation (1) and (2).The full adder pass transistor are shown in figure 2 with A ,A`,B and B` as the pass transistor inputs and these are multiplexing control inputs. International Journal of Electrical & Electronics Engineering
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The sum is generated by using multiplexing technique with C and C` as the control input. For generation of carry the Shannon theorem is applied this circuit reduces the no. of nodes and also proves the solution for the problem of power guard by using the regular arrangement of transistor input nodes. Thus the proposed full adder circuit provides less power dissipation, fast speed and small PDP than existing circuits.
Figure 2. MCIT for a full adder circuit using logic gates Full Adder
A) Transistor Sizing To enhance the performance of a 1-bit full adder cell the reduction in power consumption is required so transistor sizing is a very important for efficient full adder design. The purpose of optimization is to reduce the PDP or power-delay product of the circuit. The polynomial method is utilized for transistor sizing. For sizing the width of the transistor of XOR and XNOR gate the heuristic approach is applied. The power and delay depends upon the transistor size which is relative to the transistor count [3]. By optimizing the transistor size the load capacitance of the circuit can be reduced also. In general the increase in transistor size causes increase in parasitic capacitance and charging current. On the other hand reduced transistor size reduces the speed of the circuit. Hence the main aim of the transistor sizing is to obtain minimum power dissipation under certain performance criterion. This technique is implemented on a modified Shannon based adder cell. III. PROPOSED FULL ADDER The proposed 1 bit full adder cell is designed using multiplexing technique for sum circuit and for carry circuit the Shannon theorem is applied. According to the Shannon theorem any logical expression can be divided in to two parts and by setting any particular variable as 1 and multiplying it by a variable and by setting that particular variable as 0 and multiplying it by inverse, the equation of carry can be condensed. The expression for sum and carry are given by equation 5 and 6 as Sum=(A xor B)C`+(A xor B)`C (5) Carry= (A xor B)C+(A xor B)`B (6)
Figure 4. Schematic of proposed modified Shannon full adder
The condensed expressions of sum and carry circuit gives the reduced transistor count as the carry circuit requires only two transistor. IV. RESULT AND DISCUSSION The proposed and existing full adder circuits are designed and simulated using CMOS technology with 90 nm feature size. The proposed and existing adders are designed using PTL and schematic is generated using DSCH3.1 CAD tool. The layout is analyzed by using BSIM4 analyzer. The schematic and timing diagram are shown in Fig 4 and 5. The proposed adder and existing adders are compared in terms of power dissipation and transistor count.. The proposed full adder has a short critical path and reduced transistor activity compared to the existing full adder cells. After the implementation of all full adders the width of the transistor is varied from .002nm to 100nm to get the power optimization. TABLE.1Comparison of full adder circuits in 90 nm technology 1 bit Full Power(ÂľW) Transistor Adder With Count optimization CMOSFA[4]
1.65
24
TGFA[4]
6.5
20
CPL[4]
3
24
HYBRID[3]
0.35
14
PROPOSED
0.07
14
Figure 3. Proposed Shannon based Full Adder using logic gate International Journal of Electrical & Electronics Engineering 14
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based adder shows better performance in terms of power dissipation than other existing adders. REFERENCES
Figure 5. Simulation results of proposed modified Shannon full adder
In this paper as an application a 4-bit 2`s compliment adder/subtractor has been using the proposed full adder cell. The adder/Subtractor circuit is simulated using DSCH 3.1 CAD tool at 90 nm technology.
Figure 6. Schematic of 4-bit 2`s compliment adder/subtractor
V. CONCLUSION An adder is the most important component of any arithmetic circuit. In this paper the modified Shannon adder is simulated in 90nm technology with BSIM model. Four adders CMOSFA, TGFA, CPL, HYBRID [3]-[4] are designed with transistor sizing and their performances are compared with the modified Shannon adder. The proposed full adder is used to design a 4 bit 2`s compliment adder/subtractor. Modified Shannon
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[1] C.Senthilpari, K.Diwakar, AjayKumar Singh, “Design of a low power high performance 8x8 bit multiplier using a shannon based adder cell”, Microelectronics Journal, vol.39, pp. 812-821, May 2008. [2] K.Nehru, A.Sanmugam,”A Shannon based low power Adder cell for Neural Network Training”, IACSIT International Journal of Engineering and Technology,vol.2, No.3, pp.258-262,June 2010 . [3] B. Sathiyabama, S. Malarkkan, “Low Power Novel Hybrid Adders For Data path Circuits In DSP Processor, Indian Journal on computer Science and Engineering”, vol.3, No.1, pp. 162-167, Feb-March , 2012. [4] Chang C.H, Gu J, Zhang M, “A review of 0.18-μm full adder Performances for tree structured arithmetic circuits”, IEEE Trans. Very Large Scale Integration System, vol. 13, pp. 686-695, 2005.
AUTHORS Mrs. Rupali Gupta- is pursuing her M.E. in Electronics and Communication Engineering from NITTTR, Chandigarh, India. She has done her B. Tech in Electronics and Communication Engineering from Institute of Integral Technology U.P., India. Her areas of interest are VLSI, Wireless Communication, Image processing, embedded system design. Her current research is also based on VLSI design. Er. Rajesh Mehra- is currently Associate Professor at National Institute of Technical Teachers’ Training & Research, Chandigarh, India. He is pursuing his Ph.D. from Punjab University, Chandigarh, India. He has completed his M.E. from NITTTR, Chandigarh, India and B.Tech. from NIT, Jalandhar, India. He has more than 16 years of academic experience. He has authored more than 100 research papers including more than 50 in Journals. His research areas of interest are VLSI Design, Embedded System Design and Advanced Digital Signal Processing. He is member of IEEE & ISTE.
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