Ijeee v1i4 05

IJEEE, Vol. 1, Issue 4 (August, 2014)

e-ISSN: 1694-2310 | p-ISSN: 1694-2426

AN EFFICIENT ROM-LESS DIRECT DIGITAL FREQUENCY SYNTHESIZER WITH LESSER HARDWARE COMPLEXITY 1

Gagandeep Singh, 2Harish Jindal

1

Institute of Engineering and Technology, Bhaddal, Punjab, India 2 Gulzar Institute of Engineering and Technology, Punjab, India 1

gagandeep82singh@yahoo.co.in

Abstract: Now days Frequency synthesizer is an systen for producing any of a scope of frequencies from a solitary settled time base or oscillator. They are found in numerous current gadgets, including radio recipients, cell phones, radiotelephones, walkie-talkies, CB radios, satellite beneficiaries, GPS frameworks, and so on.

Immediate Digital Synthesis (DDS) is a sort of recurrence synthesizer that utilize electronic systems for digitally making discretionary waveforms and frequencies from a solitary, altered source Frequency. A proficient Rom-less Direct Digital Frequency Synthesizer with lesser fittings multifaceted nature (ERDDFS) has a blended sign part i.e. it has both advanced and simple parts. The center of this paper is on outline, dissection and reenactment of ERDDFS, utilizing devices like Xilinx and Modelsim. Customary plans of high transmission capacity frequency synthesizers utilize the utilization of a stage bolted circle (PLL). ERDDFS gives numerous huge preferences over the DDFS and PLL approaches.

Keywords: Direct Digital Frequency Synthesis, An efficient Rom-less Direct Digital Frequency Synthesizer (ERERDDFS) Direct Digital Synthesis (DDS) , Phase Accumulator (PA) , phase locked- loop (PLL), BS(barrel shifter) I. INTRODUCTION A frequency synthesizer is an electronic framework for creating any of a scope of frequencies from a single time base or oscillator. They are found in numerous advanced gadgets, CB radios, satellite beneficiaries, GPS frameworks, and so on. Operations like frequency multiplication , frequency division, and frequency mixing can be combined using frequency synthesizer to produce desired output signal. The thought of DDFS was initially proposed by J.Tierney in 1971[1]. Direct Digital Synthesis (DDS) is an electronic system for digitally making subjective waveforms and frequencies from a single source frequency. Due to the advancement in VLSI technology and the Demand of modern communication systems, in direct digital frequency synthesizers have been widely used .Efficient rom-less Digital Frequency Synthesis (ERDDFS), so that why it is also known as Numerically Controlled Oscillator , is a strategy which use digital signal and simple signal transforming blocks to acquire waveforms which is periodic with time. An ERDDFS can retain quick frequency exchanging in little frequency steps, over a International Journal of Electrical & Electronics Engineering 16

wide band. An ERDDFS is utilized particularly for an exact, high frequency and a phase tunable yield. A standard ERDDFS structure is combine a phase a ROM/lookup table accumulator, reconstruction filter., a DAC and ERDDFS results are simulated in LSI (large scale integration) and they play an ever increasing role in clock generation and modulation. A major advantage of direct digital synthesizer (DDS) is that its output frequency, phase and amplitude can be controlled by digital processor control [2]. Other natural capacity of ERDDFS are the ability to set with pure frequency and phase resolution and found It is simple to include different modulation capacity in the ERDDFS by using different signal processing methods, because the signal is in digital form. By using the programming in the ERDDFS frequency hopping modulation formats, adaptive channel bandwidths and data rates are easily acquired. The use of digital functional blocks makes it possible to get a higher order of system integration. The ERDDFS uses a number of application , including cable modems, measurement equipments, arbitrary waveform generators, cellular base stations and wireless local loop base stations.

Fig.1 Block Diagram

.II. RELATED WORK

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A Frequency Synthesizer having lesser hardware complexity (ERDDFS) has a mixed signal part i.e. it has both digital and analog parts. ERDDFS digital part is also called Numerically Controlled Oscillator , which consists of a Phase Register, a Barrel shifter and a ROM. The analog part has Digital-to-Analog Converter and a filter. NCO is a digital computing block which renders digital word sequences in time at a given reference clock frequency, which thereafter are converted into analog signals to serve as a synthesizer. The barrel shifter generates the phase value sequence. Most interesting concepts that have been explored is based on polynomial approximation[3], in which the actual input phase sample is fed directly into an algorithm to construct the sine curve, rather than indexing the power-hungry bulky ROM. Following this concept, ROM-less ERDDFS have been reported based on a special phase conversion algorithm such as a Taylors series evaluation as in DDS architecture [4], used a combination of two carefully chosen polynomials to approximate the first sine quadrant. An exhaustive search was conducted to figure out the segment transition point that corresponds to the minimum approximation error. A simplified fourth-order polynomial architecture with low computational cost was introduced using only three multipliers. The squarer as well as the multiplier circuits were minimized, resulting in lower hardware implementation cost. The proposed ERDDFS was observed at the gate level.. The design was compared with an equivalent approach in terms of reduction of computation, speed, and power consumption.

A ROM-Less Direct Digital Frequency Synthesizer Based on Hybrid Polynomial Approximation [6] proposed fully monolithic PLL synthesizer .CMOS/SOI process technology. It includes a voltage controlled oscillator. A low-off-leakage-current charge pump is being used for open-loop FSK modulation.

designers who were already using graphical schematic capture software and specially-written software programs to document and simulate electronic circuits.

The Verilog designers wanted a language with syntax which is similar to the C language, which has already used for the development of engineering software. As we concern about Verilog, it is case-sensitive, and it has a basic preprocessor (though less sophisticated than that of other language), and equivalent control flow keywords (if/else, for, while, case, etc.), and compatible operator precedence. Syntactic differences include variable declaration Verilog requires many other minor differences like demarcation of procedural blocks (begin/end instead of curly braces {}), bit-widths on net/reg types, and. A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and communicate with other modules through a set of declared input, output, and bidirectional ports.

Internally, following thing : net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks, and instances of (sub-hierarchies) other modules a module may consist of the Sequential statements which are placed inside a begin/end block and executed in sequential order within the block. But the blocks themselves are executed concurrently, which qualify Verilog as a dataflow language. The concept of 'wire' in Verilog's is consists of both signal values by using a function of the strengths the source drivers. A set of statements in the Verilog language is synthesizable.

There are a lot of Verilog modules which conform to a synthesizable coding style, known as register-transfer level, which can be realized by synthesis software.

Which can algorithmically transforms the into a net list, through Verilog source an equivalent description which contain only of subscripted logic like (flip-flops, AND, OR, NOT, etc.) which are available in a particular VLSI technology.

III. PROPOSED WORK In electronic design industry and the semiconductor.

Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL, is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level of abstraction. It is also being used to the verify the mixed-signal circuits and analog Hardware description languages such as Verilog differ from software programming languages because they include ways of describing the propagation of time and signal dependencies (sensitivity). two assignment operators, are There which is a blocking assignment (=), and a non-blocking (<=) assignment.

The non-blocking assignment allows designers to describe a state-machine update without needing to declare and use temporary storage variables (in any general programming language we need to define some temporary storage spaces for the operands to be operated on subsequently; those are temporary storage variables).

Since these concepts are part of Verilog's language semantics, designers could quickly write descriptions of large circuits in a relatively compact and concise form.

At the time of Verilog's introduction to Verilog uses a tremendous productivity improvement for circuit

IV. IMPLEMENTATION RESULTS 1Results Analysis: 1.1. SIMULATION RESULT: The simulation results of test are given below : 1. Create Project:

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International Journal of Electrical & Electronics Engineering

2. Add item to region:

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1.Block diagram

3. Add File To Project: 2.Internal circuitary of block diagrams

4. Start Simulation: 3. Memory internal circuitry

5. Simulation results for top module:

4(a). Barrel shifter

4(b). Barrel shifter Schematic RESULTS from Xilinx: International Journal of Electrical & Electronics Engineering 18

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coverage is 100% there may be some errors which cannot be shown so in order to overcome this the new technology of System verilog i.e. OVM and UVM. In the coming future the Frequency Synthesizer can be done by using OVM and UVM. ACKNOWLEDGEMENT I am highly grateful to Mr. Harish Jindal Assistant Professor for giving me invaluable guidance in the field of intrusion detection and providing me the opportunity to carry out this work further. It was the essential encouragement that enables me to pursue my work in this field.

REFERENCES 5(a).control circuit internal

5(b) control circuit internal

V. CONCLUSION AND FUTURE DEVELOPMENTS Conclusion: As the functional verification decides the quality of the silicon, we spend 60% of the design cycle time only for the verification/simulation. In order to avoid the delay, we use the latest verification methodologies and technologies and accelerate the verification process. This project helps one to understand the complete design and verification flow.

Designing & Verification is done by Verilog HDL using Modelsim and Xilinx Tools to get simulated and synthesized outputs.

[1] T.C. LEE Wireless and Microwave Technology Conference (WAMICON), 2013 IEEE 14th Annual Date of Conference: 7-9 Page(s):1 – 3 E-ISBN : 978-1-4673-5535-3, April 2013.

[2] Direct Digital Synthesizers: Theory, Design and Applications- Jouko Vankka Boston ; London : Kluwer Academic Publishers, 2001.

[3] D. De Caro and A. G. M. Strollo, “High-performance direct digital frequency synthesizers using piecewise-polynomial approximation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 2, pp. 324–337, 2005.

[4] K.Hariharan, E.Benitta Hubert, K.V.O.Divyalakshmi,K.Shamalla and V.Abhai Kumar, ”Coherent Sinusoid Generation using Novel ERDDFS Architecture”, Internation Journal of Smart Home,Vol.6,No.1,January 2012.

[5] High Speed DACs and DDS Systems- Walt Kester, Online Available WWW: http://www.analog.com/UploadedFiles/Associated_Docs/3670 548256311702750332 4650252sect6.pdf. Accessed on 1 January, 2007.

[6] Kenneth A.Essenwanger, Victor S.Reinhardt, ’Sine Output DDSs A Survey Of The State Of The Art’, IEEE International Frequency Control Symposium(1998) [7] T. C. Lee and B. Razavi, "A stabilization technique for phase-locked frequency synthesizers", VLSI Symp. Dig. Tech.

Papers, pp.39 -42 2001 [8] Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converterMortezapour, S.; Lee, E.K.F. Solid-State Circuits, IEEE Journal of, Volume: 34 Issue: 10 , Oct. 1999 Page(s): 1350 –1359.

[9] New direct digital frequency synthesizer architecture for mobile transceivers Hegazi, E.M.; Ragaie, H.F.; Haddara, H.; Ghali, H. Circuits and Systems, 1998. ISCAS' 98. Proceedings of the 1998 IEEE International Symposium on, Volume: 3, 1998 Page(s): 647 -650 vol.3.

[10] Direct Digital Frequency Synthesizers, A Selected Reprint Volume IEEE Ultrasonics, Ferroelectrics and Frequency Control Society.

[11] M. Sodagar and G. R. Lahiji, “A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second-order parabolic approximation,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 9, pp. 850–857, 2001 [12] CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications -D.Sunderland, R.Strauch, S.Wharfield, H.Peterson, and C.Cole, IEEE J. Solid-state Circuits, vol. SC-19, pp 497-505, Aug. 1984.

FUTURE WORK This project used Verilog i.e., the technology used is direct test cases, for verification even though the www.ijeee-apm.com

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