Power Analysis of Si MOSFET and CNFET based Logic Gates

International Journal of Engineering, Management & Sciences (IJEMS) ISSN-2348 –3733, Volume-2, Issue-5, May 2015

Power Analysis of Si MOSFET and CNFET based Logic Gates Rishika Sethi, Gaurav Soni  Abstract- With the continuous trend of reducing feature size, and employing continuously smaller components on integrated circuits, new challenges arises on the way of silicon CMOS circuits and devices. Emerging “nanodevices” promise the possibility of increased integration density and reduced power consumption. The emerging devices, partially due to their extremely small dimensions, show large variations in their behavior. The variation shown by these devices affects their reliability and the performance of circuits made from them. After aggressive scaling, the bulk Complementary Metal Oxide Semiconductor (CMOS) technology is facing numerous challenges which have motivated the researchers to concentrate for other promising devices. Carbon Nanotubes with their superior properties, high thermal conductivities and high current drivability has emerged out as a potential alternative device to the bulk CMOS technology. Initially we have analyzed the key performance of a Carbon Nanotube Field Effect Transistor (CNFET) based inverter and NAND Gate and compared it with the CMOS for 32nm technology node. Both the inverters and NAND Gate are simulated in HSPICE platform and the results show improved performance of CNFET inverter and NAND gate in terms of power in comparison to CMOS inverter and NAND Gate.

This leads to a lack of control over static leakage, short channel effects and drain voltage induced barrier lowering [9]. In order to sustain Moore‟s law and to ensure further improvements in performance of field effect transistors and interconnects, it is necessary to look for an alternative of MOSFETs and Copper interconnects. CNTs are considered as most promising candidate for future CMOS circuits and interconnect because of their superior performance and size advantage [6].

II.

STRUCTURE OF NANOTUBES

A. Carbon nanotube CNTs are considered as most promising candidate for future CMOS circuits and interconnect because of their superior performance and size advantage. A CNT is a hollow cylinder constructed by rolling up a sheet of graphene.

Graphene is a single atomic layer of graphite which in turn is a crystalline form of carbon [6].

B. Chirality

Index Terms—: CNFET, nanodevices, CMOS I. INTRODUCTION

Silicon device scaling in future faces limitations. As the silicon industry moves into the 45nm node and beyond, increasing technology challenges will be imposed by silicon CMOS device scaling. Among the most important obstacles against further device scaling is the performance variation introduced by increased process variations as feature sizes shrink and the standby power dissipation Signal Transmission in Interconnect. Increased device density and device parametric variation, rising sub-threshold leakage current and gate tunnelling current and higher device temperatures all contribute to the power problem. As CMOS approaches the 25nm node, stochastic threshold variation caused by dopant implant position in ultra-small inversion regions will give rise to more than 100mV of threshold variation. The timing behaviour of devices is also greatly affected by spatial and temporal process parameter tolerance and voltage and temperature variation. Continued channel length reduction is prevented by the limitation to reduce gate insulator thickness.

Manuscript received February 20, 2015.

Rishika Sethi, Department of Electronics & Communication, Poornima University, Jaipur, India, (e-mail: rishika.sethi@poornima.edu.in).

Gaurav Soni, Department of Electronics & Communication, Poornima University, Jaipur, India, (e-mail: gaurav.soni@poornima.edu.in).

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The term chirality is used to classify the physical and electronic structure of carbon nanotubes. Chirality is used to describe the reflection symmetry between an object and its mirror image. A chiral object is an object that is not superimposable on its mirror image. CNTs that are superimposable on their mirror images are classified as A chiral CNTs. Achiral CNTs are further classified as:[6] 1. Armchair CNTs (n=m) 2. Zigzag CNTs (n=0 or m=0) CNTs that are not superimposable on their mirror images are classified a Chiral CNTs. The circumferential edge shape of different types of CNTs is shown in the fig.1

Figure 1: Carbon Nanotube types: A-Armchair; B-Zig-Zag; C-Chiral [6].

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Power Analysis of Si MOSFET and CNFET based Logic Gates

We can again make use of the established CMOS design infrastructure and CMOS fabrication process.  CNFETs have the excellent experimentally demonstrated device current carrying ability 

C. Single walled and Multiwalled Nanotubes Carbon nanotubes can be single walled or multi walled depending upon the number of shells forming the tubular structure. Single walled carbon nanotubes consist of single grapheme cylinder which can be either metallic semiconducting in nature. Multiwalled nanotubes (MWNTs) consist of concentric CNT cylinders which are held together

by Vander Waals forces. They contain both metallic and semiconducting cylinders. Presence of metallic tubes negates the semiconducting properties of the shells and hence MWNTs are usually avoided in electronics industry.

Elimination of the outermost shells is possible by passing huge amount of current down the outershells causing the breakdown of the shells. The Multi-Wall Carbon Nanotubes (MWCNTs) or Single Wall Carbon Nanotubes (SWCNTs) as shown in fig 2 [31].

To explore the role of CNTFETs in future integrated circuits (ICs), their performance should be evaluated and compared it with the metal oxide semiconductor field-effect transistor (MOSFET). Stanford University have developed a compact model that can be used to investigate the performances of carbon nanotube field-effect transistors (CNTFETs). This model accounts for practical issues such as scattering in the channel, electron-electron interactions, effects of source/drain extension regions, and charge screening.

III. ADVANTAGES OF CNFETS OVER TRADITIONAL MOSFETS The advantages of CNFETs making them ideal for nanoscale applications now can be easily recognized. 

 Figure 2: Structure of SWCNT (A) and MWCNT (B) [31]

D. Carbon nanotube field effect transistor 

CNTFET is the only field effect transistor that is projected to outperform the 11nm node ITRS target. CNTFETs intrinsic delay (CV/I) is very low. They show higher electron mobility compared to bulk silicon and provide better power-delay product. They possess excellent electrical properties such as high speed, compatibility with high-k dielectric layer, reduced short channel effects (SCEs). Moreover CMOS circuit blocks can be realized using CNTFETs since their operation principle is similar. The schematic of CNFET is shown in fig 3 [31].

 



One-dimensional carbon nanotube acting as channel reduces the scattering probability and offers ballistic transport resulting in high-speed devices.

The nanotube conducts essentially on its surface where no dangling bonds forming interface states are present. Hence, there is no need for careful passivation of the interface between the nanotube channel and the gate dielectric.

CNFET consumes less power than an equivalent Si device.

It has an ability to carry large current. CNTs can carry current density of the order 10 µA/nm Current levels in CNFET donot depend on channel length. Hence no channel length minimization probl em.

NCNFETs and PCNFETs are symmetrical which is ideal for CMOS structures [31]

All these unique properties suggest that CNFETs have potential to be a successful replacement of MOSFETS in nanoscale devices [31].

IV.

PARAMETERS REQUIRED

A. Chirality

Figure 3: CNFET cross section [9]

Carbon nanotube field effect transistor (CNTFET) is the best promising technology to replace the existing silicon technology due to following reasons: 

The operation principle and structure of devices are similar to CMOS devices.

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The chirality of carbon nanotube is defined using the vector C (the roll-up direction). The vector C is a combination of lattice vectors a1 and a2. It connects any two primitive lattice points of grapheme such that when folded into a nanotube the two points are indistinguishable [6] .



Where (n, m) are pair of integers known as the chiral

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International Journal of Engineering, Management & Sciences (IJEMS) ISSN-2348 –3733, Volume-2, Issue-5, May 2015 indices. the vector C is given as [6]: C=3

+3

and read port with 8 transistors. From HSPICE simulation, the authors have found the proposed technique saves dynamic power by reducing discharging frequency during write operation. Compared to 6T SRAM structure, the proposed 8T SRAM saves power up to 48% and obtains 56% wider SNM during read operation at the minimal cost of 2% leakage power and 3% delay increase. Finally authors have concluded that 3~7 times less dynamic power consumption, 11~17 times less leakage power consumption, 5~6 times faster read and write operations, and 1.6 wider SNM than the conventional designs[39].

= (3, 3)



Chiral a n g l e ( θ) d e s c r i b e s t h e t i l t a n g l e o f the hexagons with respect to the tubular axis. It is the angle between the chiral vector C and the primitive lattice vector a1 [6].



Translational vector (T) defines the periodicity of the lattice along the tubular axis. It is the smallest graphene lattice vector perpendicular to C. It can be computed from the othogonality condition [6].

C.T=0 B. Diameter of CNT Depending o n their band gap, the CNTs are either metallic or semiconducting. The band-gap of a carbon nanotube is inversely proportional to its diameter. The diameter of the CNT is determined by the chiral indices (n, m) as [6]:

= Here, a is lattice constant of grapheme (0.246 nm) C. Threshold Voltage of CNT In CNTFETs, the threshold voltage of the transistor is established by the diameter of the CNT. Therefore a multiple threshold design can be achieved by employing CNTs with different diameters in the CNTFET. The threshold voltage of CNTFET is determined by the CNT diameter as [6]:

Here Vπ is carbon π to π bond energy (3.033 e V), DCNT is diameter of CNT, q is electronic charge V.CNFET CIRCUITS USED BY THE RESEARCHERS [Young Bok Kim, et-al, 2008] has proposed a new 8T SRAM based on CNFET and also compared the performance of CMOS, FinFET and CNT based 6T and 8T SRAM. The authors have reviewed many research papers on CMOS, FinFET and CNFET, then they have observed that Carbon nanotube have superior properties, high thermal conductivities, and high current handling capacities, which proved it to be a promising alternative device to the conventional CMOS. The new SRAM cell cuts off the feedback connection between the two back-to-back inverters in the SRAM cell when data is written and separates the write

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[Sheng Lin,et-al, 2010] proposed a highly stable and low-power 6T static RAM (SRAM) cell using carbon nanotube FETs that utilizes different threshold voltages for best performance. In the proposed SRAM cell, n-type and ptype transistors have different chiralities, that means a dualwhich is best to replace silicon in nanoscaled transistors. They presented the design of the concept addressing the realistic design challenges and issues such as performance, static noise margin (SNM), power consumption, and tolerance to process, power supply voltage, and temperature (PVT) variations. The results obtained From H-Spice Simulations that the SPR of the CNTFET 6T SRAM cell is four times higher than its CMOS counterpart, hence attaining low power, high stability, and low delay within the comprehensive metric provided by the SPR under write conditions. Finally authors have concluded that the proposed dual-diameter CNTFET SRAM cell has a better SPR under write operation than its CMOS counterpart cell and has significant lower sensitivity to PVT variations [34].

[Anuj Pushkama, et-al, 2010] has presented the MOSFET like CNTFET based 6T SRAM design. The authors have studied about both Si MOSFET and CNTFET, they have found that Carbon Nano Tubes(CNTs) have immense potential in dictating the future VLSI devices due to their great electrical, thermal properties, high mechanical stability, current carrying capacity and later's electromigration concerns at high temperature. The SRAM design uses the smallest transistors possible and is also susceptible to reliability issues and process variation, making it an ideal benchmark circuit to compare the two technologies.

Authors have used HSPICE to simulate the structure of the SRAM designs implemented by using 16nm CMOS technology nodes and Stanford University CNTFET. The results showed that there is a 52.7% increase in SNM of the memory cell. Meanwhile, the cell becomes 5% faster. Finally authors have concluded that NTFET is more suitable for circuit design rather than MOSFETs [29] [N.Somorjit Singh, et-al, 2013] has presented the MOSFET like CNTFET based 3T and 4T based DRAM design. After study Si MOSFET and CNTFET, authors have found that Carbon Nano Tubes(CNTs) have better potential in dictating the future VLSI devices due to their great electrical, thermal properties, high mechanical stability, current carrying capacity and later's electromigration concerns at high temperature. The operation of the three-transistor DRAM cell and its peripheral circuitry is based on a two-phase

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Power Analysis of Si MOSFET and CNFET based Logic Gates

nonoverlapping clock scheme. All "data read" and "data write" operations are performed during the active 2 phase, i.e., when PC is low. Authors have used HSPICE to simulate the structure of the DRAM designs implemented by using Berkely- 32nm PTM technology nodes and CNTFET Parameter by Stanford University. The results showed that the power dissipation, leakages power is better performance in 3T DRAM CNTFET than 4T DRAM, but delay has comparatively less delay time in 4T DRAM [27].

[Shimaa I. Sayed, et-al, 2013] have compared the performance of basic logic gates using CMOS and pure CNFET with hybrid configurations. Authors have reviewed many research papers and observed that Carbon nanotube (CNT) based technology has significant potential to replace silicon technology. Single-walled carbon nanotubes sensing circuits due to their superior transport properties and CMOS (complementary metal oxide semiconductor) technology is better in switching speed specially for NMOS. So the authors have take advantage of the high mobility transport in p-type CNTFETs and combine them with high-performance conventional n-type MOSFETs, and achieved the best overall performance in a hybrid configuration.

From HSPICE Simulation results shown that the performance of the hybrid PCNFET-NMOS configuration is better than that of the pure CMOS in terms of noise margin (32.8% higher) and power consumption (60% lower) and therefore (2.5% lower )in PDP. The performance of PCNFET-NMOS is the same of pure CNFET for noise margin, 65% lower in power consumption and 2% lower in PDP. Finally authors have concluded that the proposed Hybrid1 has the best overall performance in designing logic circuits [35].

[Priyanka Saha, et-al, 2014] has have presented a comparative circuit level analysis between conventional C MOS, fully depleted SOI/SON and CNFET devices. The authors have reviewed several research papers and found that due to scaling theory, bulk silicon device technology faced the power explosion of chips so the authors have used future devices like SOI/SON/CNFET, for developing a power efficient, high performance 4x4 1T DRAM cell array. In the 4x4 1T DRAM cell array memory organizations have memory cell arrays with sense amplifiers and column/row decoders are present. Any data can be read from or written into the cell array by proper selection of row and column address. The word line (WL) acts as the horizontal select line that enables single row of cells depending upon the row decoder input whereas the bitline is used to connect the cells in a single column to I/O circuit. From HSPICE Simulation results, the analysis shows an improvement of 41% for SOI, 49.9% for SON and 54.9% for CNFET circuits in terms of average power consumption. From concerning average delay the result gives an effective improvement of 43.9% for SOI, 55.35% for SON and 70.16% for CNFET circuits compared to MOSFET circuits. Finally authors have concluded that CNFET based 1T DRAM cell array is the much better option and the most advantageous in terms of performance parameters [33].

VI. CNFET CIRCUITS, PARAMETERS AND RESULTS

Circuit

Parameters

Results

Table 1: Circuits, and parameters used by the researcher Channel length =32nm  3-7 times less dynamic power Consumption Chirality-(19,0),  11-17 times less Pitch =10nm leakage power VFbn, VFbp=0.0ev Consumption,  5-6 times faster read MFP =200nm and Write Operation Power supply =0.9 than CMOS design room temperature CNFET based 6T SRAM Cell [39],[29], [34]

 It becomes 5% faster than Si MOSFET.

Channel length =32nm technology node= 16nm CMOS Pitch =4 nm

% INCREASE OF SNM in the memory cell.

VFbn, VFbp=0.0ev



MFP =200nm Power supply =0.9 Dcnt= 1.2 to 1.8nm work function cnt= 4.5ev Channel length =32nm Chirality-(16, 19, 0)

 Significant improvement in power consumption and area .

Vth= 289mv SNM=206.3mv Power supply =0.9 room temperature Vdd= 0.9V Vth= 0.293 volt Diameter= 1.487V

CNFET based Inverter, NAND gate, XOR gate [7][35]

 It consumes less power than CMOS.

Chirality=(19.0) Channel length = 32nm N=10, S= 20 nm Vdd= 0.9V Vth= 0.293 volt Diameter= 1.487V Chirality=(19,0) Channel length = 32nm N=10, S= 20 nm PMOS:NMOS=2:1 (W/L ratio)



It shows reduction in dynamic power Consumption and better PDP

technology node 32nm Chirality=(19.0) Vth= 0.293 volt Diameter= 1.487V Channel length = 32nm

The table 1 shows the description of CNFET based Circuits, parameters used by the various researchers respeectively with their results.

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International Journal of Engineering, Management & Sciences (IJEMS) ISSN-2348 –3733, Volume-2, Issue-5, May 2015 An experiment of Si MOSFETbased Inverter is performed by using HSPICE. The input / output characteristics obtained is shown in Figure. 4. The supply voltages considered for the experimentation are 0.9V for 32nm technology. The input is taken in the form of a pulse and output of the Si MOSFET based inverter circuit is shown in figure above. The output waveform is simulated under the process of transient analysis at 32nm technology

Chirality=(19,0) Pitch=30nm (Tox) = 4.0nm (Vfbn) = 0.0ev (Lceff) = 200.0nm Mfp In P+/N+ Doped Cnt = 15.0nm Cnt Work Function = 4.5ev.

Vdd= 0.9v

CNFET Based 3t And 4t Dram [27],[33]

Chirality=(19.0) Vth= 0.293 Volt Diameter= 1.487v Channel Length = 32nm

 Power Dissipation, Leakages Power Is Less In 3t Dram Cntfet Than 4t Dram.  But Delay Time Is Less In 4t Dram.

 The Average Delay Is Improvement Of 43.9% For Soi,M 55.35% For Son And N 70.16% For Cnfet Circuits Compared To Mosfet Circuits.

Figure 4: Transient Response of Si MOSFET based Inverter

VII. SIMULATION AND RESULTS The below Table 2 shows that CNFET and Si MOSFET Parameters which was used in the HSPICE simulation of nverter and NAND Gate. This parameters was extracted from ITRS [13] and M.tech. Thes is [6].

Table 2: CNFET & Si MOSFET Circuit’s parameter

S. No

Si MOSFET parameter

1

Technology node

2

CNFET parameter

Value

32nm

Channel Length

32nm

Vdd

0.9V

Vdd

0.9V

3

W&L (NMOS)

L=32nm W= 64nm

(n1,n2)

(19,0)

4

W&L (PMOS)

L=32nm W= 192nm

DCNT

1.487nm

Load capacitance

20fF

Vth

5 6

Value

Pitch

Figure 5: Transient Response of CNFET based Inverter

Average power obtained is shown in below Table:

0.293V 20nm

No. of 7 3 Tubes Note: All the values are taken from M.tech Thesis and ITRS [ 13]. 

An experiment of CNFET Tbased Inverter is performed by using HSPICE. The input / output characteristics obtained is shown in Figure. 5. The supply voltages considered for the experimentation are 0.9V for 32nm technology. The input is taken in the form of a pulse and output of the CNFET based inverter circuit is shown in figure above. The output waveform is simulated under the process of transient analysis at 32nm technology

Si MOSFETand CNFET based Inverter

S. No

Technology node

1

32nm

2

32nm

Average Power from= 0.0000E+00 to= 1.2000E-08

Device Si MOSFET Inverter CNFET Inverter

8.5964E-07 Watt 8.0742E-09 Watt

 Si MOSFETand CNFET based NAND Gate

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Power Analysis of Si MOSFET and CNFET based Logic Gates

Average power obtained is shown in below Table :

An experiment of Si MOSFET based NAND Gate is performed by using HSPICE. The input / output characteristics obtained is shown in Figure. 6. The supply voltages considered for the experimentation are 0.9V for 32nm technology. The input is taken in the form of a pulse and output of the Si MOSFET based NAND Gate circuit is shown in figure above. The output waveform is simulated under the process of transient analysis at 32nm technology.

Technology node 32nm 32nm

Average Power from= 0.0000E+00 to= 1.2000E-08

Device Si MOSFET NAND Gate CNFET NAND Gate VIII.

2.9983E-07 Watt 1.1003E-08 Watt

CONCLUSION

This Paper investigated the performance of the CNTFET technology based Inverter and NAND Gate and compared it with the existing silicon MOSFET technology using HSPICE. Simulation results have shown that CNT technology offer low power performance. Thus the performance analysis of CNFETs and its comparative studies show that it can obviously be a viable option for future and superior technology for applications to circuit designs. Thus a replacement of traditional MOSFET technology as they are emerging as excellent candidates for building highly energy- efficient future electronic systems.

ACKNOWLEDGMENT

Figure.6: Transient Response of Si MOSFET based NAND Gate

An experiment of CNFET based NAND Gate is performed by using HSPICE. The input / output characteristics obtained is shown in Figure.7. The supply voltages considered for the experimentation are 0.6V for 32nm technology. The input is taken in the form of a pulse and output of the CNFET based NAND Gate circuit is shown in figure below. The output waveform is simulated under the process of transient analysis at 32nm technology.

Figure 7: Transient Response of CNFET based NAND Gate

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I would like to express my deep gratitude and thanks to Prof.

Mahesh Bundele (Coordinator, Research), Poornima University for giving me an opportunity to work under his guidance for review of research papers and his consistent motivation & direction in this regard. I would also express my sincere thanks to Mr. Gaurav Soni (Asst.Professor, ECE), Poornima University for their guidance and support

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Rishika Sethi, received the bachelor degree in Electronics and Communication Engineering from Govt. Engineering College, Jhalawar (Rajasthan). She is currently working as Research scholar at Poornima University. Her area of interest is Carbon Nanotube.

Gaurav Soni, Presently working as Head of Department- Department of Electronics & Communication Engineering and Department of Electrical Engineering at Poornima University, Jaipur. He is having an experience of seven years. His area of interest includes Electromagnetic field theory, Electronic devices and circuits, Network on Chip (NOC), Nanoelectronics and Bioelectronics. He has authored a book titled Radar & TV Engineering

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