Power Analysis of Si MOSFET and CNFET based Logic Gates

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International Journal of Engineering, Management & Sciences (IJEMS) ISSN-2348 –3733, Volume-2, Issue-5, May 2015

Power Analysis of Si MOSFET and CNFET based Logic Gates Rishika Sethi, Gaurav Soni  Abstract- With the continuous trend of reducing feature size, and employing continuously smaller components on integrated circuits, new challenges arises on the way of silicon CMOS circuits and devices. Emerging “nanodevices” promise the possibility of increased integration density and reduced power consumption. The emerging devices, partially due to their extremely small dimensions, show large variations in their behavior. The variation shown by these devices affects their reliability and the performance of circuits made from them. After aggressive scaling, the bulk Complementary Metal Oxide Semiconductor (CMOS) technology is facing numerous challenges which have motivated the researchers to concentrate for other promising devices. Carbon Nanotubes with their superior properties, high thermal conductivities and high current drivability has emerged out as a potential alternative device to the bulk CMOS technology. Initially we have analyzed the key performance of a Carbon Nanotube Field Effect Transistor (CNFET) based inverter and NAND Gate and compared it with the CMOS for 32nm technology node. Both the inverters and NAND Gate are simulated in HSPICE platform and the results show improved performance of CNFET inverter and NAND gate in terms of power in comparison to CMOS inverter and NAND Gate.

This leads to a lack of control over static leakage, short channel effects and drain voltage induced barrier lowering [9]. In order to sustain Moore‟s law and to ensure further improvements in performance of field effect transistors and interconnects, it is necessary to look for an alternative of MOSFETs and Copper interconnects. CNTs are considered as most promising candidate for future CMOS circuits and interconnect because of their superior performance and size advantage [6]. II.

STRUCTURE OF NANOTUBES

A. Carbon nanotube CNTs are considered as most promising candidate for future CMOS circuits and interconnect because of their superior performance and size advantage. A CNT is a hollow cylinder constructed by rolling up a sheet of graphene. Graphene is a single atomic layer of graphite which in turn is a crystalline form of carbon [6]. B. Chirality

Index Terms—: CNFET, nanodevices, CMOS I. INTRODUCTION

Silicon device scaling in future faces limitations. As the silicon industry moves into the 45nm node and beyond, increasing technology challenges will be imposed by silicon CMOS device scaling. Among the most important obstacles against further device scaling is the performance variation introduced by increased process variations as feature sizes shrink and the standby power dissipation Signal Transmission in Interconnect. Increased device density and device parametric variation, rising sub-threshold leakage current and gate tunnelling current and higher device temperatures all contribute to the power problem. As CMOS approaches the 25nm node, stochastic threshold variation caused by dopant implant position in ultra-small inversion regions will give rise to more than 100mV of threshold variation. The timing behaviour of devices is also greatly affected by spatial and temporal process parameter tolerance and voltage and temperature variation. Continued channel length reduction is prevented by the limitation to reduce gate insulator thickness. Manuscript received February 20, 2015. Rishika Sethi, Department of Electronics & Communication, Poornima University, Jaipur, India, (e-mail: rishika.sethi@poornima.edu.in). Gaurav Soni, Department of Electronics & Communication, Poornima University, Jaipur, India, (e-mail: gaurav.soni@poornima.edu.in).

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The term chirality is used to classify the physical and electronic structure of carbon nanotubes. Chirality is used to describe the reflection symmetry between an object and its mirror image. A chiral object is an object that is not superimposable on its mirror image. CNTs that are superimposable on their mirror images are classified as A chiral CNTs. Achiral CNTs are further classified as:[6] 1. Armchair CNTs (n=m) 2. Zigzag CNTs (n=0 or m=0) CNTs that are not superimposable on their mirror images are classified a Chiral CNTs. The circumferential edge shape of different types of CNTs is shown in the fig.1

Figure 1: Carbon Nanotube types: A-Armchair; B-Zig-Zag; C-Chiral [6].

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