Implementation of floor planning algorithm in java by IJRTER

Implementaion of Floorplanning Algorithm in Java Prof. Ashwini M. Desai 1, Rahul C. Kodaganur 2, Dr. Uday V.Wali 3 1,2,3

Dept. of Electronics and Communication Engineering, K.L.Eâ&#x20AC;&#x2122;s Dr. M.S. Sheshgiri College of Engineering and Technology Belagavi, Karnataka

Abstractâ&#x20AC;&#x201D; Electronic Design Automation (EDA) has become more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. Floor Planning is an important step in the VLSI Design. In this paper we discuss the graphical user interface we have developed to solve the floor planning problem. Eclipse IDE was used for development of the tool and the language used is Java. A probabilistic algorithm is used to obtain the optimized floorplan. In our work the goodness of a solution is measured by the area of bounding rectangle which encloses all the modules. Keywordsâ&#x20AC;&#x201D; floorplanning; optimization; physical design; EDA tools; probabilistic algorithm; I. INTRODUCTION Electronic Design Automation (EDA) has become more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Floor planning is one of the important steps in physical design of VLSI circuits. Physical design is the process of transforming a circuit into a layout. Due to the increasing number of components, circuit complexity, requirement of low power, high speed, compact and fine details for the fabrication, manual design of circuits is not possible. Hence the design is carried out with the help of the computers. Depending on the need for human intervention, the different phases in the design are partially or fully automated. The automation has led to increase in chip performance, decreased in turnaround time, area and power. Physical design consists of partitioning, floor planning and routing. Floor planning is the process of arranging different modules of a particular circuit on the layout surface. The modules have a definite shape and also have locations for the terminals. Placement of modules without considering area and interconnect length may result in performance degradation. Since the space on a wafer is very expensive, the chip area must be used very efficiently to increase performance, yield and decrease cost and power consumption. Thus floor planning is a very important step in the VLSI design. In floor-planning, the information of a set of modules including their areas and interconnection is considered and the goal is to plan their positions to minimize the total chip area and interconnect cost. In the floor planning phase, the modules are positioned on the layout surface in such a way that no blocks overlap and that there is enough space left to complete the interconnections. The input for the floor planning is a set of modules, a list of terminals (pins for interconnections) for each module and a net list, which describes the terminals which have to be connected. Here we have used a probabilistic algorithm to optimize the floor plan. A probabilistic algorithm, in addition to input takes a source of random numbers and makes random choice during the execution. The outputs may change even for the fixed input [4]. The main advantage of the algorithm is that it is simple and fast i.e. the algorithm can be implemented very quickly and the requirement of computational resources is very less.

International Journal of Recent Trends in Engineering & Research (IJRTER) Volume 02, Issue 0X; Month - 2016 [ISSN: 2455-1457]

II. LITERATURE SURVEY Power density of microprocessors is increasing with every new process generation resulting in higher maximum chip temperatures. The high temperature of the chip greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling solutions significantly more expensive. Consequently, the placement of architectural blocks, or a particular floorplan selected for a given chip, can considerably affect the maximum temperature of the chip [1]. The input to the floor planning problem is a set of rectangular blocks that represent, circuit modules in a layout, and co-ordinates of these modules. The area occupied by the set of these modules can be represented as the cost; this gives the measure of floorplan quality. The algorithm we have used falls under the category of probabilistic algorithms category. There are several types of algorithms for floor planning; some of them are given below. Constructive algorithms are used to form some initial floorplan which can be improved by using other floorplanning algorithm. Constructive algorithms are used as pre-processing algorithm for floorplanning. The input to a constructive algorithm is a set of circuit components and output is a set of floorplan and modified net-list. Iterative algorithms: An iterative algorithm executes steps in iterations. It aims to find successive approximation in sequence to reach a solution. They are most commonly used in linear programs where large numbers of variables are involved. Deterministic algorithms: It is an algorithm which, given a particular input, will always produce the same output, with the underlying machine always passing through the same sequence of states. Deterministic algorithms are by far the most studied and familiar kind of algorithm, as well as one of the most practical, since they can be run on real machines efficiently. Probabilistic algorithms: A probabilistic algorithm is an algorithm where the result and/or the way the result is obtained depend on chance. These algorithms are also sometimes called randomized algorithms. In our case we have used a probabilistic algorithm. The figure 1.1 shows the initial floorplan and figure 1.2 shows a near optimal floorplan with reduced the bounding area

fig 1.1 Initial Floorplan

fig 1.2 Near-optimal Floorplan

III. IMPLEMENTATION Eclipse IDE was used in the development of the tool and coding is done in Java. Initially the GUI was created with the drawing area and the buttons and later the action listeners were added to the buttons. A screenshot of the GUI with a predefined example is shown in fig 3.1. There are a total of four predefined examples in the tool and a clear button which clears the drawing area and stops the

International Journal of Recent Trends in Engineering & Research (IJRTER) Volume 02, Issue 0X; Month - 2016 [ISSN: 2455-1457]

algorithm execution. The ‘Run’ button starts execution of the algorithm; in addition to that we also have a check box, which lets the user to choose whether or not to display the cost of the solution at the end of iteration. A. The Algorithm In order to start execution of algorithm an example is selected and ‘Run’ button is clicked. The number of iterations required is initialized in a variable, the areas of all the modules is added and then square root of the resulting sum is taken, so that it gives the measure of the side of a bounding square in which all the rectangular modules would fit perfectly. Since, all of the modules are not squares they would not fit perfectly in the bounding square we have calculated. Therefore another twenty percent is of the length of side is added to it. After this step, starting from the top left corner the modules are placed one after the other from left to right until the rightmost side of a module exceeds the measure of the side that we have calculated in the previous step. If a module exceeds the side, then it is placed below the first left top module such that it doesn’t overlap with any other modules. Even if there are overlaps during placement of modules, the algorithm checks where the overlap has occurred and then the modules are moved such that the overlap is eliminated. After the placement of all modules the algorithm checks if there is any free area left in between the modules, and then it attempts to eliminate the free area by moving the modules close to each other, thus reducing the area of bounding rectangle. 1. Initialize data set and control variables 2. y = 0; x = 0; 3. Select a random module and place at (x,y) and mark it as placed 4. x = x + width of module placed in 3. 5. If x > Wmax, find ymax = y + max(height of modules placed in 3) 6. y = ymax, x = 0. 7. repeat 3 till all modules are exhausted. 8. Compact the layout in x and y, calculate the cost and save. 9. Clear mark from all modules. 10 Repeat 2 if number of iterations is less than required. 11. Select the layout with minimal area among all saved layouts. After the first step cost is calculated and assumed to be the best cost, then the same step is iterated but, with some random logic which is dependent on our probabilistic algorithm. Cost is calculated after every iteration, and is compared with the best cost, if the new cost has lesser bounding area than the best cost then the solution is stored as the best solution and its corresponding cost is updated in the best cost. After all the iterations are completed then the best solution is displayed on the drawing area.

fig 3.1 GUI showing a predefined example

International Journal of Recent Trends in Engineering & Research (IJRTER) Volume 02, Issue 0X; Month - 2016 [ISSN: 2455-1457]

IV. RESULTS The execution of the algorithm starts after clicking the Run button at the bottom. The screenshots of solutions with display message after the iteration is shown in the following figures. Iteration 1: After Iteration 1 the Area = 42924 this is set to be the best cost and all the costs corresponding to further solutins are compared with this cost. Iteration 37: After the 37th iteration area = 39396, and we can see that the free space inside the bounding rectangle is almost negligible. Iteration 40: In the final iteration area = 53126, the optimal floor plan was obtained in the 37th iteration, hence it will be displayed in the drawing area along with its cost as bestfit. After the completion of all iterations the execution of algorithm is completed, but 37 th iteration had the least cost with area = 39396. This is shown in the fig 3.7

fig 3.3(a) First Iteration fig 3.3(b): Iteration 37

fig 3.3 (c)Final Iteration

fig 3.3(d) Bestfit

V. CONCLUSION AND FUTURE WORK A. Conclusion The EDA tool to optimize the floorplan was successfully implemented. The tool was designed and implemented using the Eclipse IDE. The language used for coding was Java. Near optimal solution was obtained using our probabilistic algorithm, by randomly placing the modules one after the other inside the bounding rectangle.

International Journal of Recent Trends in Engineering & Research (IJRTER) Volume 02, Issue 0X; Month - 2016 [ISSN: 2455-1457]

B. Future Work The tool we have developed implements floor planning, which only considers the modules. The tool can be further developed to also consider the terminals of the modules and optimize the bounding area as well as optimize the length of interconnect. The tool may also be further extended to implement functionalities such that, the user can input the constraints to the algorithm, and input the dimensions of the modules according to their requirement. Modification can also be done to the tool so that it can be applied for many other complex optimization problems where near optimal solution is acceptable. REFERENCES 1. 2. 3. 4.

Yongkui Han and Israel Koren, “Simulated Annealing Based Temperature Aware Floorplanning”, Journal of Low Power Electronics Vol. 3, 1–15, 2007 N. A. Sherwani “Algorithms for VLSI Physical Design Automation”, Kluwer Academic Publishers, 3rd edition, 1999. Tung-Chieh Chen and Yao-Wen Chang, “Modern Floorplanning Based on Fast Simulated Annealing” Richard M. Karp “An introduction to randomized algorithms”, Discrete Applied Mathematics 34 (1991) 165-201