Low power high performance 10t full adder for low voltage cmos technology using dual threshold volta

Low Power High Performance 10T Full Adder for Low Voltage CMOS Technology Using Dual Threshold Voltage Surbhi Kushwah1, Shipra Mishra2 1

2

M.Tech. VLSI Design, NITM College Gwalior M.P. India 474001 Asst. Prof. VLSI Design., NITM College, Gwalior, M.P. India 474001

Abstract:Reduction in leakage power has become an important concern in low-voltage, lowpower, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s).The intention of this paper is to reduce leakage power and leakage current of 1-bit Full Adder while maintaining the competitive performance with few transistors are used (transistors count 10). A new high performance 1-bit Full Adder based on new logic approach is presented in this paper. Recent research has revealed that with the gradual shrinking of device sizes, the leakage power dissipation is becoming more and more dominant, and it is likely to become comparable to switching power dissipation in future generation VLSI circuits. This has motivated us to develop suitable techniques for the reduction of leakage power dissipation in dynamic CMOS circuits, a problem which has not been addressed by any researcher. This paper proposes a technique for containing the leakage power using two threshold voltages (dual-VT) in the realization of circuits. Necessary care has been taken such that the dual-VT dynamic circuits can be kept in standby mode and dissipate small leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes Keywords—Low power,Full adder, Dual-Vt technology, CMOS, leakage power.

I. INTRODUCTION Leakage power has become a top topic for IC designers. Leakage power is the result of unwanted sub-threshold current in the transistor channel when the transistor is turned off. This sub-threshold drives the leakage power, strongly influenced by variations in the transistor threshold voltage V T (the voltage applied to the gate electrode that turns on the transistor). Also the leakage power dissipation is roughly proportional to the active area of a circuit. As technology scaling progressed through, subthreshold leakage current constituted an important factor of the total power consumption of CMOS circuits. As CMOS technology continues to scale, the supply voltage (VDD) falls with each generation and contributes the power consumption. However, the transistor threshold voltage (Vt) should be reduced at the same rate to maintain adequate gate overdrive, which in turn allows the enable circuit performance to improve by about 30% in each generation. However, lower Vt causes transistor sub-threshold leakage currents to increase exponentially; and hence the bit-line active leakage currents of register files also increase exponentially and the noise immunity of the bit-lines is dramatically reduced. Alternative bit-line circuit techniques are required to curtail this trend and combine good noise immunity with high performance [1]. Many techniques were proposed to limit the impact of sub-threshold leakage. Dual-Vt design was introduced as a technique that assigns Vt,L to critical path transistors and Vt,H to some noncritical path transistors, taking care not to generate new critical paths in the process [2].

II. FULL-ADDER A one bit full adder takes two one bit inputs and adds them together. To make a full adder, it also needs to consider a carry in and carry out flag. Thus a one bit full adder takes three 1bit inputs and contains two one bit out puts. The first inputs are the two bits are to be added together, @IJRTER-2016, All Rights Reserved

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International Journal of Recent Trends in Engineering & Research (IJRTER) Volume 02, Issue 08; August - 2016 [ISSN: 2455-1457]

respectively A and B [3]. The third input is a carry in flag. This flag specifies whether or not a previous addition occurred which contained a carry out. The first output is the 1 bit result of the addition. The second output is carry out flag which specifies if the result of the addition was larger than the 1 bit result.

Logic Information Ports of Full adder are as follows  Input A – 1 bit B – 1 Bit C – 1 Bit Output Sum – 1 Bit Carry- 1 Bit 

Gates Xor gate1: A^B Xor gate1: Xor gate1^B And gate1: A.B And gate2: Xor gate1.C Or gate1: and gate1 | and gate2 Block Diagram The basic block for above statement can be given as below: 

Figure. 1. Full Adder

III. DUAL-VT TECHNIQUE OF FULLADDER All High leakage power consumption has become an issue in CMOS technology. We here designing a 1 bit full adder using 10T technology. The dual Vt technique is proposed to efficiently suppress the leakage power. Dual threshold CMOS is a static technique that exploit the delay slack in non-critical paths to reduce leakage power. It provides both high and low threshold voltage (Vth) transistors in a single chip that are used to deal with the leakage problem [4]. Fabrication process can achieve a different Vth device by varying different parameters. Changing the channel doping profile, increasing the channel length, changing the body bias, and using a higher gate oxide thickness are examples of fabrications parameters that can be changed to achieve high Vth transistor. Each parameter has its own trade-off in terms of process cost, effect on different leakage components, and short channel effects. High Vth transistors suppress the subthreshold current, while low Vth transistors are used to achieve high performance. For a logic circuit, the transistors in non-critical paths can be assigned high Vth to reduce subthreshold leakage current, while the performance is not sacrificed by using low Vth transistors in the critical paths

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International Journal of Recent Trends in Engineering & Research (IJRTER) Volume 02, Issue 08; August - 2016 [ISSN: 2455-1457]

Figure. 2.One bit Full adder

IV. THE PROPOSED 10T FULL ADDER The circuit of 10T Adder is a one-bit full adder core has three inputs (A, B, and carry in Ci) and two outputs (sum S and carry out Co). The Adder cell is made of five CMOS inverters that are connected as shown in Figure 2. Input A is directly connected to inverter first while input B is connected second and third inverter [5]. Second inverter PMOS drain and third inverter NMOS drain are connected first inverter output while second inverter NMOS drain and third inverter drain are connected directly input A. Second inverter output is connected fourth inverter input and input Ci is given in inverter fifth. There is interesting, the power supply VDD connected first inverter only. All transistors have minimum length (LMIN =45nm according to used Technology), while their widths are typically propose parameters.

Figure. 3.Schematic Diagram of 1- bit full adder

The value of WP1 and WP2 defines PMOS transistors width and WN1 and WN2 defines the NMOS driver transistors width use in first inverter CMOS Invertors. Based on CMOS 0.45-nm process technology,[6] the proposed full adder is proven to have the minimum power consumption and less power-delay product by Cadence simulation comparing with other prior literature.

V.

OPTIMISATION OF POWER AND DELAY OF 10T FULL ADDER BY DUAL THRESHOLD NODE Here , first the 10 transistor full adder circuit is simulated with 45nm channel length i.e. submicron channel with high threshold MOSFET in P-net and N-net. Then following results are obtained :

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International Journal of Recent Trends in Engineering & Research (IJRTER) Volume 02, Issue 08; August - 2016 [ISSN: 2455-1457]

Figure.4. 1-bit Full Adder using Dual Vth

Figure.5.Output Waveform of 1-bit Full Adder using Dual Vth

Figure .6.Leakage Current Waveform of Full Adder using Dual Vth

Designing low-power VLSI systems has become an important performance aim because of the fast growing technology in mobile computation and communication field [7], . There is one basic

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International Journal of Recent Trends in Engineering & Research (IJRTER) Volume 02, Issue 08; August - 2016 [ISSN: 2455-1457]

approach to reduce power consumption of circuits in scaled technologies. One approach is reducing the dynamic power consumption during the active mode operation of the device and the other is the reduction of leakage current during the standby mode The power consumption of a CMOS digital circuit can be expressed as in equation (1) and equation (2).

P= Pdynamic + Pshort + Pleakage ……………………. (1) P= f.C.Vdd2 + α f.Ishort.Vdd + Ileak. Vdd…..…….. (2) Where f is the clock frequency, C is the average switched capacitance per clock cycle, Vdd is the supply voltage, The current ISC in the second term is due to the direct path short circuit current which arises when both the NMOS and PMOS transistors are simultaneously active, conducting current directly from supply to ground [8] .Finally, leakage current Ileak, which can arise from substrate injection and sub-threshold effects, is primarily determined by fabrication technology considerations.

Supply voltage reduction is a widely accepted methodology for reducing dynamic power, but it has an adverse effect on circuit performance. To maintain high performance, the threshold voltage Vt must also be scaled down that causes an exponential increase in the sub-threshold leakage.. Static power dissipation is the power dissipated by the circuit when it is in sleep mode or standby mode. Average leakage power is given by equation (3). …………………. (3) Where Ileak is the leakage current that flows in a transistor when it is in off state. This static power dominates dynamic power especially in deep submicron circuits and also in circuits that remains in idle mode for a long time like cell phones [9].

Next, the same circuit is simulated with 45nm channel length with low threshold and high threshold MOSFET inP-net and N-net respectively [10]. Then following results are obtained as follows.

Figure .7. 1-bit Full Adder using Dual Vth

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International Journal of Recent Trends in Engineering & Research (IJRTER) Volume 02, Issue 08; August - 2016 [ISSN: 2455-1457]

Figure.8. Output Waveform of 1-bit Full Adder using Dual Vth

Figure.9. Leakage Current Waveform of Full Adder using Dual Vth

VI. ESTIMATION OF LEAKAGE CURRENT USING DUAL VT A 1-Bit Full Adder based on Dual Vth technique have been proposed. The analysis of the simulated results confirms the feasibility of the Dual Vth technique in full adder design and shows that there is reduction of 80 to 85 percent in the value of power dissipation parameter as compared to CMOS technique at supply voltage of 0.7V. Dual Vth adders have not a marginal increase in area & delay compared to the CMOS adders. Reduction of both active power and standby leakage power without area and delay penalty makes a Dual Vth technique a good candidate of high performance and low power applications. For mobile systems, since the system may be idle for a long time, the standby leakage power cannot be ignored. Dual Vth is a promising technique for reduction of both active and standby leakage power. Overall, we achieved the lowest power dissipation. Table 1.1 shows the simulation summary of various parameters.

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Parameters

Cmos Based Full Adder 45nm

(Pmos hvt & Nmos lvt )1-Bit Full Adder usingDual VT 45nm

(Pmos lvt & Nmos hvt) 1-Bit Full Adder Using Dual VT 45nm

Technology Used Supply Voltage Frequency Used Access Time Delay Efficiency Leakage Power Leakage Current

0.7V 0.05GHz

0.7V 0.05GHz

0.7V 0.05GHz

20ns 9.14ns 30% 35.36µW 14.24nA

20ns 2.24ps 70 % 5.509pW 928.3fA

20ns 2.04ps 80 % 4.54pW 919.7fA

VII. CONCLUSIONS It can be seen that the highest speed of operation i.e. Minimum delay is achieved by circuit with low threshold MOSFET in P-net and N-net. However, it has moderate power consumption and excessively high leakage power consumption. Again, the speed of operation is lowest i.e. Maximum delay is achieved by the circuit with high threshold MOSFET in P-net and N-net. Moreover, highest average power consumption is there . However, it has very low leakage power consumption. Finally, the speed of operation is Modest i.e. intermediate delay is achieved by the circuit with high and low threshold MOSFET in Nnet and P-net respectively. Moreover, it has lowest average power consumption and very low leakage power consumption.So, it can be sucessfully concluded that considering all design constraints, circuit with high and low threshold MOSFET in N-net and P-net respectively REFERENCES 1.

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