A Power Efficient, High Speed Reduction Technique using Domino Logic

IJSTE - International Journal of Science Technology & Engineering | Volume 3 | Issue 12 | June 2017 ISSN (online): 2349-784X

A Power Efficient, High Speed Reduction Technique using Domino Logic Ms. Jyoti Chaudhary Ideal Institute of Technology, Ghaziabad, AKTU, Lucknow, India

Ms. Juhi Jain Ideal Institute of Technology, Ghaziabad, AKTU, Lucknow, India

Abstract Domino logic based OR gate is proposed in this paper. Domino logic is the power reduction technique for the large circuit which uses NMOS only. In this paper we studied Previous domino logic OR gate depending on previous work. Proposed design, which is introduce new domino logic OR gate with power reduce technique and delay. We provide direct discharging path for the circuit while working. New design gives 74%reduction in power and 31% reduction in delay. Complete circuit is simulated using TSMC 90nm technology by applying 1v vdd.

Keywords: Dynamic gates, evaluation phase, pre-charge phase and robustness ________________________________________________________________________________________________________ I.

INTRODUCTION

The area reduction and high performance advantages have made dynamic logic circuits a main implementation option for high performance circuits such as microprocessors. This performance advantage comes at the cost of high power dissipation. The domino logic is constructed by adding an inverter at the output of the dynamic gate. The basic construction of an (n-type) domino logic gate is shown in Fig 1.

Fig. 1: Basic Domino Logic Structure

The pull-down network (PDN) is constructed exactly as in complementary CMOS. When CLK =0, the Dynamic Node shown in figure 1 will be pre charged to Vdd as pmos is on. If CLK =1, the Dynamic Node is conditionally discharged based on the input values and the pull-down topology. The charge leakage at the dynamic node is compensated by using PMOS keeper transistor. Noise robustness of the domino logic can be improved by upsizing the PMOS keeper transistor which makes the keeper more conducting and thereby tries to maintain the charge at the Dynamic Node.

Domino cells also have a speed advantage as they avoid contention when the cells switch, In addition to being able to achieve better output drive strength for input loading. In order to understand this, the input to a static cell drives both PMOS and NMOS transistors. Any input transition that causes the cell to switch logical states results in a PMOS transistor being turned off and an NMOS transistor being turned on, or vice versa. Since the inputs to the cell have finite rise and fall times, this means that during the transition period both the PMOS and the NMOS transistors are weakly on. This contention between the two transistors increases the input voltage level at which the cell switches. By increasing or decreasing the ratio of the PMOS to NMOS transistor size It is possible to speed up the rise or fall transition of a static cell. This, however, leads to the alternate transition becoming slower. Since both transitions are equally important in static cells, it is difficult to gain very much by skewing a particular transition. For this reason, the switching point of most static cells tends to be close to half the supply voltage level

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A Power Efficient, High Speed Reduction Technique using Domino Logic (IJSTE/ Volume 3 / Issue 12 / 012)

(Vdd). For domino cells only the rising transition is critical. No contention exists between PMOS and NMOS transistors, if an input rise causes the evaluation node of the domino cell to discharge.

In this paper we have proposed a new domino logic circuit scheme for improving power, delay, and power-delay product. The remaining paper is organized as follows. Section ІІ presents the problem definition related to domino logic. Section ІІІ presents previous work related to domino logic. Section ІV presents new proposed domino logic circuit scheme and simulation results and comparisons are discussed in section V, conclusion is presented in section VІ.

II. PROBLEM DEFINITION Charge sharing between nodes in the pull down network and the dynamic node can unintentionally reduce the voltage of the dynamic node enough to switch output Buffer.

The addition of the output inverter makes domino gates non-inverting. One can often design around this limitation, but some circuits cannot be implemented solely using domino logic unless both polarities (true and complement) of the inputs are available. If both polarities of inputs are available then we can generate both polarities of internal signals with two domino gates so subsequent stages will have both polarities of their inputs available too.

III. RELATED BACKGROUND WORK

Fig. 2: Previous work domino logic scheme

The Previous work domino logic scheme is shown in Fig.2 In this circuit current mirror circuits are used in stack in place of footer transistor. If any noise signal occurs at M1 it will be leak to ground via M4 and M5 is Purpose of current mirror circuits. Transistors M3 and M4 also forms current mirror, due to both current mirror circuits gate to source voltage of NMOS pull down network decreases rapidly. This effect is called as stacking effect. The purpose of M4 and M5 in the Previous work circuit to create stacking effect, due to which voltage drop across M2 reduces .The presence of current mirrors in the Previous work circuit causes increase in delay. To overcome this problem size (W/L ratio) of PDN should be increased.

Because of stacking effect circuit dissipates power and becomes less noise robust. In this previous work circuit there will be voltage drop in evaluation phase due to stacked current mirrors. Due to negative Vgs, there will be exponential reduction in sub All rights reserved by www.ijste.org

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A Power Efficient, High Speed Reduction Technique using Domino Logic (IJSTE/ Volume 3 / Issue 12 / 012)

thresh Previous current in the circuit. In order to improve power-delay product more and more, size of PMOS transistor should be four times that of NMOS transistor in inverter circuit at the output node. Purpose of transistor Mp3 is to provide strong Vdd to the lower PMOS Mp2, Because PMOS transistor are used to provide strong one logic to the circuits IV. PROPOSED DOMINO LOGIC CIRCUIT

Fig. 3: Proposed domino logic circuit

Proposed design working is same as previous domino logic circuit. But is dissipating more power and giving large delay. So for power reduction and delay reduction we give direct path for discharge of output. We use nmos2, nmos5, nmos7 for one discharge path and nmos1, nmos3, nmos5 as other discharge path. As this path gives less delay than previous work we can remove M7 and M6 transistor which further reduce power, delay and ultimately PDP of proposed circuit.

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A Power Efficient, High Speed Reduction Technique using Domino Logic (IJSTE/ Volume 3 / Issue 12 / 012)

V. SIMULATION RESULTS AND WAVEFORM

Fig. 4: Proposed Domino Logic Circuit

Fig.4 shows simulation result for proposed design. Here we use TSMC 90nm technology file for simulation purpose.

Furthermore we compare power delay and PDF for different voltages. Also we compare PDP for different NMOS width.

W of NMOS 180n 240n 300n 360n 420n 480n

Table – 1 Previous work domino logic scheme results SupplyVoltage 1v 0.9v 0.8v 0.7v 0.6v Power (nW) 333.74 121.66 179.05 73.592 72.895 Delay(ps) 172.88 245.60 441.41 867.73 2046.9 PDP (10^-18) 57.695 29.879 79.036 63.858 149.21 Table – 2 Proposed domino logic circuit results SupplyVoltage 1v 0.9v 0.8v 0.7v 0.6v Power (nW) 87.054 68.576 53.466 40.826 30.258 Delay(ps) 120.88 173.22 302.20 628.76 1338.3 PDP (10^-18) 10.523 11.879 16.157 25.670 40.495 Table – 3 PDP comparision varing width of NMOS PDP (10^-19) Previous work domino logic PDP (10^-19) Proposed domino logic 576.95 134.36 407.62 118.38 322.22 110.57 276.03 105.40 249.85 103.01 234.29 101.71

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A Power Efficient, High Speed Reduction Technique using Domino Logic (IJSTE/ Volume 3 / Issue 12 / 012)

VI. CONCLUSION Decreasing technology trends demands circuitry which consume less power and gives less delay in circuit. Domino logic is very useful scheme used in digital circuit for power reduction and delay reduction purposed. Here proposed design of OR gate gives less power, less delay than previous work which makes us to use it in full adder, multiplexer application. Tanner EDA tool use to simulate our new proposed design using TSMC 90nm technology and obtain result gives large improvement in power delay and PDP. REFERENCES [1] [2] [3] [4] [5] [6] [7]

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