2D Gaussian Filter for Image Processing Application on FPGA

IJSTE - International Journal of Science Technology & Engineering | Volume 3 | Issue 06 | December 2016 ISSN (online): 2349-784X

2D Gaussian Filter for Image Processing Application on FPGA Tarun Tyagi M. Tech. Student Department of Electronics Engineering Ideal Institute of Technology, Ghaziabad

Vishal Mishra Assistant Professor Department of Electronics Engineering Ideal Institute of Technology, Ghaziabad

Abstract This paper presents implementation of 2D Gaussian filter for image processing. The Gaussian filter is a 2D convolution operator which is used to smooth images and remove noise. The software results are carried out on MATLAB R 2013b while hardware implementation has been written in Verilog HDL. The significance of this filter is realized when it was implemented on FPGA kit.

The unit is area and delay optimized on hardware kit.

Keywords: Gaussian Filter, FPGA, Image Enhancement, Filtering ________________________________________________________________________________________________________ I.

INTRODUCTION

Nowadays, the concepts of digital image processing are being applied in different fields such as medicine, astronomy, geography, industry, etc. These fields often require results in real-time, and efficiency in the implementation of digital image processing is imperative. In this paper, the authors present the state-of-the-art research on the subject and propose a methodology for implementation of a 2D Gaussian Filter on an FPGA. II. CONVENTIONAL 2D GAUSSIAN FILTER IMPLEMENTATION A gray scale image is represented by a matrix of pixels with values ranging from 0 to 255. In this design we are using a 256 x 256 image for gaussian filtering. For storing image of 256 x 256 size in Block RAM (BRAM) of FPGA, it requires the image to be converted into a vector of 65536 elements. The input to BRAM should be of the format ‘ .coe ’ file. The following are the steps followed for executing the design.

1) Our base image will be lena_256.jpg. Using Matlab, we add gaussian noise to image. The code can be found in adding noise. m. The output image is lena_noise.jpg 2) Second step is convert image to text containing 65536 elements. The code can be found in image2text.m.

Input file lena_noise.jpg Output file is lena_gauss256.txt 3) The convert .txt file to. coe file manually. Output file is lena_gauss256.coe 4) Load the lena_gauss256.coe file to BRAM memory using Xilinx Design Suite 5) Here we start the verilog coding Quantized Gaussian kernal =

We will first load the image to img register. Then we do image processing, more precisely Gaussian filtering of image and store the result in img_gauss register. While simulating using Isim, A text file named img_gauss_filter.txt will be generated containing the coefficients of filtered image.

The text file can be converted to image by Matlab coding. Use gaussfilter.m file. Gaussian filter will smoothen the image, but it cannot remove the noise.

III. MODIFIED 2D GAUSSIAN FILTER IMPLEMENTATION The difference is in step 5.

Quantized Gaussian kernal = 1/16 * [0 11 0] Horizontal Quantized Gaussian kernal2 = 1/16 * [0 11 0 ] Vertical We will first load the image to img register. Then we do image processing, more precisely Gaussian filtering of image and store the result in img_gauss register.

All rights reserved by www.ijste.org

96

2D Gaussian Filter for Image Processing Application on FPGA (IJSTE/ Volume 3 / Issue 06 / 018)

Here we use separate gaussian mask for horizontal and vertical arithmetic operations. First we apply horizontal gaussian mask and then vertical gaussian mask. While simulating using Isim, A text file named img_gauss_filter_modified.txt will be generated containing the coefficients of filtered image.

IV. FPGA IMPLEMENTATION    

For NxN size Guassian filter Base design requires N2 mutliplications and N2 - 1 Additions per pixel Modified Design requires 2N mutliplications and 2N - 2 additions per pixel Thus the hardware area required for computation is reduced.

V. DEVICE UTILIZATION Conventional Design

Fig. 2: Device Utilization for Conventional Design Modified Design

Fig. 3: Device Utilization for Modified Design

All rights reserved by www.ijste.org

97

2D Gaussian Filter for Image Processing Application on FPGA (IJSTE/ Volume 3 / Issue 06 / 018)

VI. RTL SCHEMATICS BASE DESIGN

Fig. 4: RTL Schematic for Conventional Design Modified Design

Fig. 5: RTL Schematic for Modified Design

VII. SIMULATION RESULTS Base Design

Fig. 6: Simulations for Base Design

g1-g9 are gaussian kernel coefficients, p1-p9 are image pixels, When check_ok becomes 1, the execution is completed and img_gauss_filter.txt file is generated.

All rights reserved by www.ijste.org

98

2D Gaussian Filter for Image Processing Application on FPGA (IJSTE/ Volume 3 / Issue 06 / 018)

Modified Design

Fig. 7: Simulations for Modified Design

g1-g3 are gaussian kernel coefficients, p1-p3 are image pixels. When check_ok becomes 1, the execution is completed and img_gauss_filter_modified.txt file is generated.

VIII. RESULTS

Fig. 8(a): Original Image

Fig. 8 (b): Image with Gaussian noise

Image after Gaussian Filtering

Fig. 9(a): Base Design

Fig. 9(b): Modified Design

All rights reserved by www.ijste.org

99

2D Gaussian Filter for Image Processing Application on FPGA (IJSTE/ Volume 3 / Issue 06 / 018)

IX. CONCLUSION The algorithm was modified and applied on Lena image to prove its worth. The FPGA implementation of the 2D Gaussian filter proves its vitality for the image processing i.e. image smoothing. The algorithm can be further modified and tried and several images to make it universal.

REFERENCES [1]

D. AIghurair and S. S. AI-Rawi, "Design of Sobel operator using Field Programmable Gate Arrays," in 2013 The International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE). IEEE, May 2013, pp. 589-594. [Online]. Available: [2] http://ieeexplore.ieee.orgflpdocs/epic03/ wrapper.htm?amumber=6557341 [3] V. Sriram and D. Kearney, "A FPGA Implementation of Variable Kernel Convolution," in Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007). University of South Australia: IEEE, Dec. 2007, pp. 105-110. [Online]. Available: [4] http://ieeexplore. ieee.org/xpls/abs_aU.jsp?amumber=4420 148 [5] Z. Guo, W. Xu, and Z. Chai, "Image Edge Detection Based on FPGA," in 2010 Ninth International Symposium on Distributed Computing and Applications to Business, Engineering and Science.

IEEE, Aug. 2010, pp.

169-171.

[Online].

Available: http://ieeexplore.ieee.org/ Ipdocs/epic03/wrapper.htm?amumber=557240 1 [6] K. Ramana Reddy, "Implementation of pipelined sobel edge detection algorithm on FPGA for High speed applications;' in 2013 International Conference on Emerging Trends in Communication, Control, Signal Processing and Computing Applications (C2SPCA). IEEE, Oct. 2013, pp. 1-5. [Online], Available: [7] http://ieeexplore.ieee.orgllpdocs/epic03/wrapper.htm?amumber=6749364 [8] S. Khorbotly and F. Hassan, "A modified approximation of 2D Gaussian smoothing filters for fixed-point platforms," 2011 IEEE 43rd Southeastern Symposium on System Theory, pp. 151-159, Mar. 2011. [Online]. Available: http://ieeexplore.ieee.orgflpdocs/epic03/ wrapper.htm?amumber=5753797 [9] R. E. W. Rafael C. Gonzalez, Digital Image Processing using MATLAB, 2009, vol. 24, no. 11.

[10] D. G. Bailey, Design for Embedded Image Processing on FPGAs, 2011.

[11] D. Lowe, "Object recognition from local scale-invariant features," in Proceedings of the Seventh IEEE International Coreference on Computer Vision. IEEE, 1999, pp. 1150-1157 vol.2. [Online]. Available: http://ieeexplore.ieee.org/lpdocs/epi c03/wrapper. htm ?am umber= 790410

All rights reserved by www.ijste.org

100