Double Tail Comparator

IJSTE - International Journal of Science Technology & Engineering | Volume 4 | Issue 2 | August 2017 ISSN (online): 2349-784X

Optimized Design of Modified Double-Tail Comparator M. Usharani Department of Electronics & Communication Engineering Velammal Engineering College Chennai-6000066, India

P. Narmathashri Department of Electronics & Communication Engineering Velammal Engineering College Chennai-6000066, India

Abstract The need for ultra-low-power, space economical and high speed analog-to-digital converters is pushing toward the utilization of dynamic regenerative comparators to maximize speed and power potency. During this project, associate analysis on the delay of the dynamic comparators are going to be given and analytical expressions are derived. From the analytical expressions, style’s will get associate intuition concerning the most contributors to the comparator delay and totally explore the trade-offs in dynamic comparator design. supported the given analysis, a brand new dynamic comparator is projected, wherever the circuit of a traditional double tail comparator is changed for low-power and quick operation even in tiny offer voltages. While not complicating the look and by adding few transistors, the feedback throughout the regeneration is reinforced, which ends up in remarkably reduced delay time. Post-layout simulation leads to a 250 µm CMOS technology ensure the analysis results. It’s shown that within the projected dynamic comparator each the facility consumption and delay time are considerably reduced. the most clock frequency of the projected comparator will be hyperbolic to a pair of.5 and 1.1 gigahertz at offer voltages of one.2 and 0.6 V, whereas overwhelming one.4mW and 153 µW, severally.

Keywords: Comparator, CMOS, Double Tail ________________________________________________________________________________________________________ I.

INTRODUCTION

Comparator is one in all the elemental building blocks in most analog-to-digital converters (ADCs). several high speed ADCs, like flash ADCs, need high-speed, low power comparators with little chip space. High-speed comparators in ultra-deep sub micrometer (UDSM) CMOS technologies suffer from low offer voltages particularly once considering the very fact that threshold voltages of the devices haven't been scaled at a similar pace because the offer voltages of the fashionable CMOS processes [1]. Hence, planning high-speed comparators is more difficult once the availability voltage is smaller. In different words, in an exceedingly given technology, to realize high speed, larger transistors area unit needed to compensate the reduction of offer voltage, that conjointly implies that additional die space and power is required. Besides, low-tension operation leads to restricted common-mode input vary, that is vital in several high-speed ADC architectures, like flash ADCs. several techniques, like offer boosting ways [2], [3], techniques using body-driven transistors [4], [5], current mode style [6] and people victimisation dual-oxide processes, which might handle higher offer voltages are developed to meetthe low-tension style challenges. Boosting and bootstrapping area unit 2 techniques supported augmenting the availability, reference, or clock voltage to handle input-range and switch issues. These area unit effective techniques, however they introduce reliableness problems particularly in UDSM CMOS removes the brink voltage demand such body driven MOSFET operates as a depletion-type device.

Based on this approach, in [5], a 1-bit quantizer for sub-1V modulators is planned. Despite the benefits, the body driven semiconductor unit suffers from smaller transconductance (equal to gmb of the transistor) compared to its gate-driven counterpart whereas special fabrication method, like deep n-well is needed to possess each nMOS and pMOS transistors operate within the body-driven configuration. Excluding technological modifications, developing new circuit structures that avoid stacking too several transistors between the availability rails is preferred for low-tension operation, particularly if they are doing not increase the circuit quality. In [7] [9], extra electronic equipment is additional to the standard dynamic comparator to boost the comparator speed in low offer voltages. The planned comparator of [7] works right down to an offer voltage of zero.5 V with a most clock frequency of 600 megacycle and consumes eighteen W. Despite the effectiveness of this approach, the result of part mate within the extra electronic equipment on the performance of the comparator ought to be thought-about. The structure of double-tail dynamic comparator initial planned in [10] relies on planning a separate input and cross coupled stage. This separation allows quick operation over a large common-mode and provide voltage vary [10].

In this paper, we tend to planned dynamic comparator each the ability consumption and delay time area unit considerably reduced. The most clock frequency of the planned comparator is hyperbolic to two.5 and 1.1 gigahertz at offer voltages of one.2 and 0.6 V, whereas overwhelming one.4 mW and 153 µW, severally.

II. DESIGN OF THE PROPOSED MODIFIED DOUBLE-TAIL COMPARATOR Fig. 1 demonstrates the schematic diagram of the planned dynamic double-tail comparator. Owing to the higher performance of double-tail design in low-tension applications, the planned comparator is intended supported the double-tail structure. The most

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Optimized Design of Modified Double-Tail Comparator (IJSTE/ Volume 4 / Issue 2 / 022)

plan of the planned comparator is to extend Vfn=fp so as to extend the latch regeneration speed. For this purpose, 2 management transistors (Mc1and Mc2) are accessorial to the primary stage in parallel to M3=M4 transistors however in an exceedingly crosscoupled manner

(a) (b) Fig. 1: Schematic diagram of the proposed dynamic comparator. (a) Main idea. (b) Final structure.

III. RESULTS AND DISCUSSION The operation of the planned comparator is as follows (see Fig. 2). Throughout reset section (CLK = zero, Mtail1 and Mtail2 area unit off, avoiding static power), M3 and M4 pulls each fn and fp nodes to VDD, thence junction transistor Mc1 and Mc2 area unit discontinue. Intermediate stage transistors, MR1 and MR2, reset each latch outputs to ground. Throughout decision-making section (CLK = VDD, Mtail1, and Mtail2 area unit on), transistors M3 and M4 put off. What is more, at the start of this section, the management transistors area unit still off (since fn and fp area unit concerning VDD). Thus, fn and fp begin to drop with completely different rates in keeping with the input voltages. Suppose VINP > VINN, therefore fn drops quicker than fp, (since money supply provides a lot of current than M1). As long as fn continues falling, the corresponding pMOS management junction transistor (Mc1 during this case) starts to show on, propulsion fp node back to the VDD; thus another management junction transistor (Mc2) remains off, permitting fn to be discharged utterly. In alternative words, in contrast to standard double-tail dynamic comparator, within which Vfn/fp is simply a perform of input junction transistor transconductance and input voltage distinction (9), within the planned structure as before long because the comparator detects that for example node fn discharges quicker, a pMOS junction transistor (Mc1) activates, propulsion the opposite node fp back to the VDD. So by the time passing, the distinction between fn associated fp (Vfn/fp) will increase in an exponential manner, resulting in the reduction of latch regeneration time (this are going to be shown in Section III-B). Despite the effectiveness of the planned plan, one in all the points that ought to be thought-about is that during this circuit, once one in all the management transistors (e.g., Mc1) activates, a current from VDD is drawn to the bottom via input and tail junction transistor (e.g., Mc1, M1, and Mtail1), leading to static power consumption. To beat this issue, 2 nMOS switches area unit used below the input transistors [Msw1 and Msw2, as shown in Fig. 5(b)]. At the start of the choice creating section, attributable to the very fact that each fn and fp nodes are pre-charged to VDD.

Fig. 2: Transient simulations of the proposed double-tail dynamic comparator

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Optimized Design of Modified Double-Tail Comparator (IJSTE/ Volume 4 / Issue 2 / 022)

For input voltage distinction of _Vin = five mV, Vcm = 0.7 V, and VDD = zero.8 V. (during the reset phase), each switches area unit closed and fn and fp begin to drop with completely different discharging rates. As before long because the comparator detects that one in all the fn/fp nodes is discharging quicker, management transistors can act in an exceedingly thanks to increase their voltage distinction. Suppose that fp is propulsion up to the VDD and fn ought to be discharged utterly, thence the switch within the charging path of fp are going to be opened (in order to forestall any current drawn from VDD) however the opposite switch connected are going to be closed to permit the whole discharge of fn node in to fn thus there words, the operation of the management transistors with the switches emulates the operation of the latch.

IV. CONCLUSION In this work, we tend to bestowed a comprehensive delay analysis for clocked dynamic comparators and expressions were derived.

2 common structures of typical dynamic comparator and traditional double-tail dynamic comparators were analyzed. Also, supported theoretical analyses, a replacement dynamic comparator with low-tension low-power capability was planned so as to enhance the performance of the comparator. Post-layout simulation ends up in zero.18-μm CMOS technology confirmed that the delay and energy per conversion of the planned comparator is reduced to a good extent compared with the traditional dynamic comparator and double-tail comparator.

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