Design and Implementation of AMBA APB Bridge with Low Power Consumption

IJSTE - International Journal of Science Technology & Engineering | Volume 4 | Issue 2 | August 2017 ISSN (online): 2349-784X

Design and Implementation of AMBA APB Bridge with Low Power Consumption Sandeep Jagre M. Tech Student Department of Electronics & Communication Engineering TCST, Bhopal, India

Dr. Neelesh Gupta Head of the Dept.

Department of Electronics & Communication Engineering TCST, Bhopal, India

Prof. Nishi Pandey Assistant Professor Department of Electronics & Communication Engineering TCST, Bhopal, India

Abstract The aim of the dissertation is to put in force AMBA-APB (Advance Microcontroller Bus Architecture-Advance Peripheral Bus) Bridge with efficient deployment of gadget assets. For this, simulation and synthesis of the complex bridge interface is designed which could offer minimum electrical power strength consumption and high frequency band width among AMBA high performance or speedy or high velocity buses like ASB and low active APB buses. For designing any type of IC three main criteria’s are speed, power and area. Clock is a first-rate situation in designing of any digital sequential gadget. Clock skew is generated when the distinction in clock signal arriving time between two adjacent register. One of the strategies to limit clock skew is master slave flip-flop. So in this dissertation work we used flip-flop as a memory element with master slave concept which is based on the finite state machine. Advanced Peripheral Bridge with clock skew reduction technique is enforced within the thesis the usage of Verilog HDL. For the simulation and synthesis motive, design usage summary and power details Xilinx’s-ISE design suite, model 14.1 has been used. Power record is added for developing better know-how of the energy utilization in any gadget.

The power document offers the electricity consumption precise. Hence, the whole clocks energy intake is of 0.35 mW, general hierarchy strength consumption of 0.13 mW and general on chip logical strength consumption of 0.040 W had been extracted from Xilinx X-Power analyser device when APB Bridge is designed beneath the proposed design technique.

Keywords: AMBA, AHB, APB, Soc (System on Chip), Clock Skew, FSM ________________________________________________________________________________________________________ I.

INTRODUCTION

Now a days the main challenge of designing an IC are Speed, Power and Area. There are lot of techniques to reduce this parameters.

Basically system on chip style numerous elements of computer or different electronic system are mounted onto one chip. A widely known on chip buses are referred to as advanced microcontroller bus architecture plays an important role in system on chip. AMBA conception is introduced initial time by ARM therefore it's a registered of ARM Ltd. one in every of the appliance of AMBA buses is fashionable transportable mobile devices like (Smartphone, hard Disk) during which a variety of application specific integrated circuits (ASIC) and system on chip (SOC) with its application processors are used. Additionally AMBA style Specification provides a platform to the designer that is sort of freelance to technology and therefore the technique organizes the varied peripherals like UART, Keypads, and PIO in SOC style. AMBA specification provides a typical for interaction and communication. Advanced Microcontroller Bus design (AMBA) specification defines an on chip communication commonplace for planning high performance embedded microcontroller processors or systems. Advanced Microcontroller Bus design specifications offer technology freelance resolution for communication between master and its slaves.

Fig. 1: Advance Microcontroller Bus Architecture (AMBA) Plan.

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Design and Implementation of AMBA APB Bridge with Low Power Consumption (IJSTE/ Volume 4 / Issue 2 / 006)

II. SYSTEM DESIGN Metastability and Clock Skew Minimization Approach Metastability in electronics is the ability of a digital electronics system to persist for an unbounded time in an unstable equilibrium or metastable state. In metastable states, the circuit may be unable to settle into a stable '0' or '1' logic level within the time required for proper circuit operation. Actually metastability is occurs because of setup and hold violation. For reducing metastability we use faster flip-flop, lowering the clock frequency and data speed. Difference in clock signal arriving time between two sequentially adjacent register is called clock skew. There are two types of clock skew is generated in sequential circuits are positive clock skew and negative clock skew. When the source register or flip-flop is clocked first then the clock skew is called positive clock skew.

When the destination register or flip-flop is clocked before the source register then the clock skew is called negative clock skew.

Clock skew performs an important role in sequential circuit’s clock timing calculations. The master slave flip-flop overcomes the problem of metastability. It consists of two edge triggered flip-flops. The flip-flops are triggered at different levels of clock pulse edges.

D

D

Q

D

Master CLK

CLK

Q_bar

Q

Q

Slave CLK

Q_bar

Q_bar

Fig. 2: Master Slave D Flip Flop Configuration

Advance Peripheral Bus (APB) In Advanced Microcontroller Bus Architecture, APB Bridge is very important part which is shown in Figure 1. APB Bridge performs different type of operations. The operations are data, address and control signal latching for the peripherals. As like AHB, APB has no pipelined protocol. Therefore, APB interfaces the peripherals that have low bandwidth. This will reduce the low power consumption and also interface complexity.

APB Block Diagram

Fig. 3: Block Diagram of APB

The APB Slave input Signals are PADDR, PWRITE, PCLK, PRESETn, PWDATA and PSEL, PRDATA, PENABLE are output signals.

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Design and Implementation of AMBA APB Bridge with Low Power Consumption (IJSTE/ Volume 4 / Issue 2 / 006)

III. SIMULATION RESULT FOR DESIGN For implementation purpose of AMBA(Advanced Microcontroller Bus Architecture) APB(Advanced Peripheral Bus) Bridge with its various blocks like master-slave flip flop, state machine, project decoder and other blocks Verilog Hardware Description Language is used. Simulation has done by using Xilinx ISE Design Suite version 14.1. This will generate waveform in different phenomenon. Xilinx is also used for the logic synthesis and extraction of design utilization summary. For Power analysis purpose Xilinx XPower analyzer tool have been used to find power factors in different domains and total on chip power. The Clock frequency for simulation of APB design is considered 50 MHz.

Fig. 3: Technology RTL view of AMBA APB (Advanced Peripheral Bridge)

Fig. 4: Simulation Result of Proposed AMBA APB Bridge with master slave flip flop approach

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Design and Implementation of AMBA APB Bridge with Low Power Consumption (IJSTE/ Volume 4 / Issue 2 / 006)

Fig. 5: Simulation result of AMBA APB Bridge with master slave flipflop approach (contd..)

Fig. 6 Simulation result of AMBA APB Bridge with master slave flipflop approach (contd..)

Fig. 7: Comparison Chart between Previous and Proposed Methodology in term of Power Consumption in mW.

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Design and Implementation of AMBA APB Bridge with Low Power Consumption (IJSTE/ Volume 4 / Issue 2 / 006)

As we can see from the figure 5 the comparison chart between previous methodology (Three bit Ripple Counter Approach) and proposed methodology (Flip-Flop Master-Slave Approach) in term of total clock domain and total hierarchy power consumption in mW.

Fig. 8: Comparison Chart between Previous and Proposed Methodology in term of Total on Chip Power Consumption in W.

As we can see from the figure 6 the comparison chart between previous methodology (Three bit Ripple Counter Approach) and proposed methodology (Flip-Flop Master-Slave Approach) in term of Total on Chip Power Consumption in W. IV. CONCLUSION In this paper the designing of AMBA (Advanced Microcontroller Bus Architecture) APB (Advanced Peripheral Bus) Bridge has done by using Verilog Hardware Descriptive Language with memory element master slave flip flop which is based on finite state machine. The objective of the thesis became to design an APB bridge with green device sources approach for minimizing the clock skew. Also strength reports are included with the proposed layout. For simulation purpose Xilinx ISE Design Suite version Xilinx 14.1 has used and also used for synthesis. For Power simulation purpose Xilinx XPower analyzer tool has been used. Clock frequency for APB simulation has taken 50 MHz. Table - 1 Power Report Comparison between Proposed approach (master-slave flip-flop) and previous APB Bridge approach Power Reports of Proposed AMBA APB Bridge Power Reports of Previous AMBA APB Bridge with reset Frequency(MHz) with master-slave flip- flop approach (W) controller and three bit ripple down counter approach (W) Total clock domain = 0.00035 Total clock domain = 0.00038 50 Total Hierarchy domain = 0.00013 Total Hierarchy domain = 0.00057 Total On-Chip Power = 0.040 Total On-Chip Power = 0.113

The difference between power reports of clock domain, hierarchy domain and total on-chip has been observed with master slave flip-flop approach.

The differences can be observed as:  Total clock domain power under proposed design approach is reduced by 10.26% than the previous bridge design with reset controller conditions and three bit ripple counter approach.  Total Hierarchy power under proposed design approach is reduced by 77.2% than the previous bridge design with reset controller conditions and three bit ripple counter approach.  Total on chip power under proposed design approach is reduced by 64.6% than the previous bridge design with reset controller conditions and three bit ripple counter approach.

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