DSM Based low oversampling using SDR transmitter

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303

DSM Based low oversampling using SDR transmitter Saranya.R Me (Vlsi Design) Department Of Ece, Vandayar Engineering College,

Mr.B.Arun M.E., Assistant Pofessor, Department Of Ece, Vandayar Engineering College,

Saranya2266ms@gmail.com

er.arunbala@gmail.com

Abstract:The oversampling recruitment is a limiting factor in high frequency application such as software defined radio. This project is a high frequency processing and low oversampling ratio. A single bit semi parallel processing is proposed in this paper.

Using this single bit PDSM Architecture, high speed, high complexity computations are executed in parallel. The single bit DSM is to build an RF transmitter that includes a one bit quantifier with two level switching power amplifier for high linearity and high efficiency. Performance analysis by using the MATLAB simulations by reducing the oversampling ratio by same signal to noise ratio.

The DSM implemented on field programmable gate array and using a signal code division m u lt ip le a c c e s s s ig n a l. This project will give bandwidth of the low oversampled signal increased four times without increasing frequency. Finally they can be achieved signal to noise ratio is very low and also oversampling ratio is small.

Keywords— Delta sigma modulator, PDSM, SDR, oversampling.

——————————  —————————— in a DSM discourages its employment in today’s computeintensive applications, such as software defined radio (SDR) Oversampling is Sigma-Delta (S-D) modulation based systems..Software-Defined Radio (SDR) refers to the analog-to digital (A/D) conversion technology is a cost technology wherein software modules running on a generic effective alternative for high resolution (greater than 12 bits) hardware platform consisting of DSPs and general purpose converters which can be ultimately integrated on digital signal microprocessors are used to implement radio functions such as processor ICs. The increasing use of digital techniques in generation of transmitted signal (modulation) at transmitter communication and audio application has also contributed to and tuning/detection of received radio signal (demodulation) at the recent interesting cost effective high precision A/D receiver. By using the proposed low-oversampling DSM, converters. A requirement of analog-to-digital (A/D) interfaces envelope signals in wireless applications, e.g., orthogonal is compatibility with VLSI technology, in order to provide for frequency-division multiplexing (OFDM) and code division monolithic integration of both the analog and digital sections multiple access (CDMA), can be modulated to two-level on a single die. Since the S-D A/D converters are based on signals. These signals can then be amplified with a switchdigital filtering techniques, almost 90% of the die is mode power By using the proposed low-oversampling DSM, implemented in digital circuitry which enhances the prospect envelope signals in wireless applications, e.g., orthogonal of The compatibility. Additional advantages of such an frequency-division multiplexing (OFDM) and code division approach include higher reliability, increased functionality, multiple access (CDMA), multiple access (CDMA), can be and reduced chip cost. Those characteristics are commonly modulated to two- level signals. These signals can then be required in the digital signal processing environment of amplified with a switch-mode power amplifier (PA.) today. Conventional high-resolution A/D converters, such as successive approximation and flash type converters, operating at the Nyquist rate(sampling frequency approximately equal to twice the maximum frequency in the input signal), often do not make use of exceptionally high speeds achieved with a scaled VLSI technology. These Nyquist samplers require a complicated analog low pass filter (often called an antialiasing filter) to limit the maximum frequency input to A/D, and sample-and hold circuitry. On the other hand, S-D A/D converters use a low resolution A/D converter (1-bit

I.INTRODUCTION

quantizer), noise shaping, and a very high oversampling rate (64 times for the DSP56ADC16). OVERSAMPLING has become a popular technique for data conversion. The outstanding linearity of delta-sigma modulators (DSMs) is the main reason for popularity of these modulators in modern electronic components such as data converters , frequency synthesizers, and switched-mode power supplies. linearity comes at the cost of a large oversampling ratio and, therefore, need for high-speed processing. The oversampling requirement

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INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 2. BLOCK DIAGRAM OF DSM

Fig 2: Block diagram of D Fig:2 block diagram DSM 3.EXISTING SYSTEM Several research works have utilized the concept of multirate signal processing to reduce the oversampling ratio. A Hadamard transform was used [10] [11] to decompose the input spectrum into several sub-bands, which were then applied to separate DSMs, whose outputs were subsequently recombined. This work used two DSMs per output bit, which is inefficient in terms of the die area when implemented using radio frequency integrated circuits (RFIC) technology. The structure is related to that of an M-path digital filter [ll]. On each channel, the analog input sequence z[n] is modulated by an analog f l sequence w,[n], AC modulated, decimation filtered, and modulated by a digital *1 sequence uT[n]. The outputs of the M channels are summed to produce the IIACADC output y[n]. The part of the IIACADC that contains the analog modulators and the AC modulator is referred to as the 17nC modulator. The part of the IIACADC that includes the decimation filters, digital modulators, and the channel summers is referred to as the decoder. The N(z). the output of the oversampling IIACADC can be viewed as the sum of an overall signal component and an overall quantization error component.An area-efficient architecture was developed by combining multiple DSMs in parallel, along with analog preprocessing of the input signal and digital postprocessing of the output signals. By using interconnected modulators working in parallel with each running at the same clock, a new Parallel processing DSM (PDSM) was proposed. A Time Interleaved Sigma-Delta architecture was used in to increase bandwidth of the converter with a lower hardware complexity.

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Fig:3 The oversampling ∏∆∑A/D converter architecture(Hadamard transform)

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 registers. multiplexed from the two pre-calculated values available in the registers. is to make an or S can be driven with the two-level output of PDSM. The calculation of ya(i) requires y(i-1) from the last ya calculation. depicts a hardware implementation of a PDSM, based on (14) to (18). The Once y[n] is ready, the second part is multiplexed from the two precalculated values available in the registers. is to make an RF transmitter which includes a one-bit quantizer delta sigma and two-level switching power amplifier, which results in a high linearity. One of the most favorable applications of the proposed single-bit PDSM is to make an RF transmitter which includes a one-bit quantizer delta sigma and two-level switching power amplifier, which results in a high efficiency.

4. PROPOSED SYSTEM In this paper, an alternative approach, also based on parallel processing, is described. Here, however, multiple DSMs are not used. The proposed PDSM implements combined and simplified processing steps for n sequential clocks of a regular DSM (n closed loop computations.) A PDSM that combines n closed loops generates n bits per clock cycle. In fact the highest sampling frequency of the proposed PDSM is now shifted to one multiplexer, which is the same as the sampling frequency of the traditional single-bit DSM. The other processing element of PDSM work n times slower compared to traditional bit DSM The other processing element of PDSM work n times slower compared to traditional single-bit DSM.

Fig 5 Typical implementation of PDSM Fig 4:Digital implementation of PDSM

For regular DSM, the sampling frequency of the input signal and clock frequency of the DSM are typically equal(the is value is fs for previous section.) Now, suppose the sampling frequency of the input signal is fs while the clock frequency of the DSM is fs, which may not be equal .Further more assume that f s > fs and, for simplicity of analysis, fs/fs is a positive integer value, N. The architecture is an extension of the thirdorder and four-unrolled PDSM shown in Fig. 5. It shows that N processor elements calculate N outputs in parallel. One processor calculates the states of the registers for the cycle N+1. The frequency of input sampling and for processing elements is fs. The PDSM output rate, which is equivalent to the PDSM throughput and output multiplexer selection frequency, is f s. f s can be called the effective frequency of PDSM, which considers parallel processing. The first part is dependent on the signal values of a2, a5, a7 and x at time n and can be processed at time n. The second part depends on y[n], which is processed by PE1, and its process is started at time n. The second part is a two-level value, and its two possibilities can be pre-calculated and stored in two

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The main advantage of PDSM is to achieve higher SNR output signal using lower processing frequency compared to a regular DSM. One of the most favorable applications of the proposed single-bit PDSM is to make an RF transmitter which includes a one-bit quantizer delta sigma and two-level switching power amplifier, which results in a high efficiency and high linear transmitter. A two -level switching Power Amplifier Class D, E, F, F-1 or S can be driven with the twolevel output of PDSM. The unrolling factor of the implemented PDSM was selected to be four. The PDSM and DSM were fed by CDMA signals with bandwidths of 1600 kHz and 400 kHz, respectively. The clock frequencies (sampling frequency) of the DSM and PDSM were 25 MHz. As shown in Fig. 14, with the help of parallel processing, the PDSM allows for an increase of the modulation bandwidth by a factor of 4 compared to DSM, while maintaining a comparable noise shaping performance. The power consumption of power amplifier in a PDSM based transmitter is of the order of 10 Watt.

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 Therefore power consumption of PDSM is negligible compared to total power consumption of the transmitter. The multi-stage noise shaping (MASH) structure is also an alternative delta sigma structure which is simple for implementation and it isunconditionally stable.

Fig 8: Filter using reduced noise

5. OUTPUT

Fig 6 :Transmit signal with noise

Fig 9: Reduced SNR

Fig 7: Transmitting signal with high SNR 15

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 synthesis,‖ IEEE Transactions Very Large Scale Integrated (VLSI) Systems, vol. 17, no. 6, pp. 793–802, Jun. 2009.

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Fig 10: Bandwidth

CONCLUSION The delta-sigma modulation with a smaller oversampling rate. We proposed architecture uses the concept of parallel processing to achieve the effect of oversampling without the need for a high sampling frequency. The proposed structure has been validated through MATLAB simulation. Simulation results show that for a DSM with OSR = 256, the proposed structure is able to fold the required OSR 16 times while maintaining the same signal to noise (SNR) ratio. Increase the bandwidth of output signal four times without increasing the processing frequency.

REFERENCES [1] Y. Wang, ―A class-S RF amplifier architecture with envelope delta-sigma modulation,‖ IEEE Radio and Wireless Conference, pp. 177-179, 2002.

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