Analysis of leakage current calculation for nanoscale MOSFET and FinFET

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 4 ISSUE 2 – APRIL 2015 - ISSN: 2349 - 9303

Analysis of leakage current calculation for nanoscale MOSFET and FinFET Kayalvizhi A1 1

2

Ramya N2

iTRP Engineering College, ECE Ramyanatesan2010@gmail.com

TRP Engineering College, ECE, Kayalkavi1992@gmail.com

Abstract—This paper presents logic level estimators of leakage current for nanoscale digital standard cell circuits. Here the proposed estimation model is based on the characterization of internal node voltages of cells and the characterization of leakage current in a single Field-Effect Transistor (FET). Finally the estimation model allowed direct implementation of supply voltage variation impact on leakage current and output voltage drop (loading effect).The technique is feasible for implementation in Hardware Description Language (HDL) and HDL cell models supporting leakage estimation at simulation time.

Index Terms— FET, HDL, Leakage current, Standard cell ——————————  ——————————

1 INTRODUCTION

T

HE leakage current especially important in burst mode, type integrated circuits where most of the time the system is in idle or sleep mode.

No computation takes place during sleep mode. For example, a cell phone will be in the standby mode for most of the time where the processor is idle. With the leakage current during the idle mode, power will be continuously drained with no useful work being done. There are different mechanisms that contribute to leakage power. These include sub-threshold leakage, the gate leakage, and BTBT leakage [2]. Hence leakage current has become a dominant factor in the design of VLSI circuits. The Leakage current appeared recently as a main factor of power dissipation. This is because, the move from micro-technology to nanotechnology, which has as significant changes and scales in SPICE parameters such as threshold voltage, length of the gate, the gate dioxide thickness and supply voltage, all of these results in a dramatic decrease of the leakage current value .

The goal of low power design for battery powered devices is for extend the battery service life while meeting performance requirements. Reducing power dissipation is a design goal, even for non portable device since excessive power dissipation results in increased packaging and cooling costs as well as potential reliability problems. This approach powerful for the logic level HDL modeling of leakage circuits, capable of obtaining good accuracy of leakage estimation.

2 BACKGROUND AND RELATED WORKS In nanoscale digital circuits, several leakage phenomena of FET devices can contribute to total static power dissipation, depending on the specific technological, such as a MOSFET, FinFET. In digital CMOS below 65-NM node, the gate leakage, the sub threshold leakage, and body leakage have been recognized as the dominant types [2] and are the focus of estimation/ reduction techniques. The various leakage types of FET devices behave differently from each other with temperature and circuit level countermeasures, so that it is of interest to individually estimate the impact of each type of a given circuit design.

A very accurate characterization of leakage current of a single FET is straightforward; this is not the case for connecting transistors of generic digital cells, due to two effects affecting node voltages and therefore the actual current flowing in the devices: the stacking effect and the loading effect. The former occurs whenever transistors are stacked in a drain–source series connection, and strongly affects all leakage components due to the substantial change in the node voltages [1].

In FinFET designs, physical device-level models of leakage are available [4], showing that the sub threshold current is dominant over the gate and body current. In [6], a thermal model for FinFETbased NAND, NOR, and inverter has been presented, for predicting thermal runaway, considering dynamic and static power, the latter based on a previous model of the sub threshold leakage in doublegate FETs.

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 Kayalvizhi A is currently pursuing masters degree program in VLSI Design in TRP Engg College,Tamilnadu, E-mail: kayalkavi1992@gmail.com  Ramya N is assitant professor in Electronics and Communication Engineering in TRP Engg College, Tamilnadu, E-mail: ramyanatesan2010@gmail.com

3 METHODOLOGY This approach presents Logic-level estimators of the leakage current, in nanoscale standard cell based designs.

Very accurate characterization of the leakage current in a single FET is straightforward.

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INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 4 ISSUE 2 – APRIL 2015 - ISSN: 2349 - 9303 This is not the case for connecting transistors of generic digital cells, due to two effects affecting node voltages and therefore the actual current flowing in the devices: the stacking effect and the loading effect. The sub threshold leakage current flowing through a stack of series-connecting transistors reduces when more than one transistor in the stack is turned off. This effect is known as the stacking effect. Loading effect as the change in the leakage of a logic gate due to its input and output loading.

3.1 Procedures for leakage calculation The single device static current characterization, the node voltages line characterization of the circuit structures composing the cells, and the voltage drop loading effect characterization, the procedure for obtain the leakage current drawn by any cell in a design is as follows.

1) From the input pattern, in the characterization database of the cell, we recover the voltage line associated the internal nodes of the pull-up and pull-down circuit structures.

2) From the input pattern, the resize factor of the cell, the total equivalent width of the load, and the VDD value, we find the output voltage drop δV due to loading effect.

3) Apply the actual voltage value VDD − δV to the voltage line of the internal nodes of the OFF pull-up/pull-down network, and find the actual internal node voltages.

4) We apply the actual voltage value +δV to the voltage line of the internal nodes of the pull-down/pull-up network, and find the actual internal node voltages.

Leakage estimation techniques Tested the accuracy of the method against SPICE simulations of single cells, for each basic cell type and resize factor, and for each possible input pattern. The different accuracy among input patterns can be described to internal voltage values. The average leakage current estimated with respect to all input patterns.

In complex circuits, the loading effect often exhibits compensation between positive and negative leakage modification in different cells. It is essential that an estimation technique be capable of accurately capturing those design cases where such compensation does not occur. Thus, to demonstrate the effectiveness of the approach in modeling the loading effect, we focused in a set of critical net lists, specifically designed to show a considerable loading effect due to the disproportion of the fan out with respect to the driver size.

In a circuit composed of multiple cells, the estimation algorithm sums up the leakage contributions of all cells considering the loading effects, whereas in SPICE simulations and measure the total static current flowing through the supply voltage generator connecting to the circuit under test.

Generate a vector of pseudorandom values of the technological parameters affected by variations. For intra cell transistor mismatch analysis, variations in node voltages should be characterized with respect to the joint pseudo random variations of single transistors, which results in a more complex implementation of the procedure but it does not imply any modification to the leakage calculation scheme. The technique is feasible for implementation in a Hardware Description Language (HDL) environment.

The loading effect on a digital cell driving a high logic value on its output node OUT connecting to the input nodes of other digital cells. Given a cell driving a set of other cells, it is possible to estimate the voltage drop δV caused by the loading effect, for both high and low logic output voltage. Fig.1 shows the corresponding equivalent circuit. Qp models the pull-up network in the driving cell, while Q1…QN are the transistors in the driven cells directly connecting to node OUT. For simplicity, assume, Q1…QN being all n-type devices; the same analysis can be carried on distinguishing a set of n-type and a set of p-type driven devices and leading to the same conclusion. The voltage drop δV generally behaves nonlinearly with VDD. To accurately calculate the voltage drop, we chose to characterize it at different supply voltages.

Vdd

QP

QN

Q1

3.2

3.3 Calculation output voltage drop

OUT

GND Fig. 1. Equivalent circuit for voltage drop calculation

5 RESULTS AND DISCUSSION The characterization of internal node voltages in all the pull-up/pulldown circuit structures that compose a cell library can be easily done as a function of the actual voltage swing.

Vdd A

B C GND Fig. 2. Stacks of three N-type transistors

The internal node voltage characterization is needed for circuit structures, including stacked transistors, which occur in generic cells.

The characterization can be easily extending to series-connecting transmission-gate structures.

Each circuit structure was simulated using a DC sweep, in 30 °C and 100 °C, for VDD = 0.1–1.0 V with 0.1 V steps, for all input patterns.

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INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 4 ISSUE 2 – APRIL 2015 - ISSN: 2349 - 9303 Trans.Electron Device, vol. 54, no. 12, pp. 3186–3194.

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Fig. 3. FinFET characteristics

4

CONCLUSION

This logic-level model allows the accurate estimation of leakage current in nanoscale digital standard cell circuits. The analysis of voltages in the internal nodes of standard cells shows a practically linear depending in the output voltage swing and Several tests have been carried out in a full cell library in dedicated circuit cases for loading effect analysis and in Multicell circuit cases at different supply voltages. To test the accuracy of the method against SPICE simulations of single cells, for each basic cell type and resize factor and for each possible input patterns. FinFET circuits used in low power design in digital circuit.

ACKNOWLEDGMENT The author wish to thank N. Ramya and Dr.P. Thiruvalarselvan for fruitful discussions.

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