Effective Area and Power Reduction for Low-Voltage CMOS Image Sensor Based Applications

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY

VOLUME 3 ISSUE 1 –JANUARY 2015 - ISSN: 2349 - 9303

Effective Area and Power Reduction for Low-Voltage CMOS Image Sensor Based Applications B.GOMATHI1

D.VEERA VANITHA2

1

Avinashilingam Institute for Home Science and Higher

2

Avinashilingam Institute for Home Science and Higher

Education for Women-University,

Education for Women-University,

Department of Electronics and Communication Engineering,

Department of Electronics and Communication Engineering,

Gomathi.sri91@gmail.com

vanitha.svc@gmail.com

Abstract— This paper presents a novel CMOS image sensor (CIS) based on 45nm processing technology. It includes a single inverter time-to-threshold pulse width modulation circuitry, capable of operating under very low supply voltage. Conventional CMOS image sensors implemented using 130nm processing technology had many advantages. But in order to incorporate additional processing circuitry, the device density increases which results in degradation in the speed of operation. Scaling of physical MOS device dimensions improves both speed and density. The leakage associated with scaling could be eliminated by re-designing the circuit. As result area and power consumption could be reduced, which is demanded by portable imaging equipments.

Index Terms— CIS, nm, time-to-threshold, PWM. 

1 INTRODUCTION Area and power minimization is considered as a primary challenges in wireless sensing systems. The size of the sensor plays a major role in portable image sensor based equipments.

A CIS based on pulse width modulated output is adopted in this

The sensor should have high Signal-to-Noise ratio (SNR), low

paper. This technique uses a CMOS inverter as a comparator.

dark current, high sensitivity, reduced noise and smaller pixel

Instead of a more conventional ADC a time-to-threshold

size. The shrinking of pixel size should not impart the quality of

conversion technique is implemented. This paper is formulated as

the image. A high quality image is desired after all the processing

follows. Section II provides a brief explanation about the related

techniques. The miniaturization of pixel size was also limited

work. Section III illustrates the existing work. Section IV

noise effects and leakage current. To overcome the problems

introduces the proposed work which is followed section V,

associated with shrinking digital pixel sensor was introduced. It

experimental results and comparison finally section VI provides

includes on-pixel Analog to Digital converter (ADC) and

the concluding remarks.

achieves a higher SNR.

IJTET©2015

139

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY

VOLUME 3 ISSUE 1 –JANUARY 2015 - ISSN: 2349 - 9303 2 RELATED WORK

conversion becomes necessary. Other ADC’s have clear

The CMOS image sensor based on several analog to digital

limitation if number of pixels increase further. Here an 8-bit ADC

converters is considered. Orit Skorka et.al proposed generally

was adopted. It reduces the level of random noise and improves

image sensors are based on analog pixel. It is converted to digital

the dynamic range as well [6].

data at chip level in CMOS image sensor. The conversion is done because digital data exhibits higher immunity towards noise [1].

Jimin cheon et.al illustrates that noise becomes a significant problem in image sensors. It should be resolved before readout.

While using single slope ADC, with correlated double sampling by taking transient noise into account it results in thermal noise and its simulation is time very long. Hence meaningful noise estimation results cannot be obtained [2]. To reduce noise effect kazuya kitamura et.al introduced a CMOS image sensor with column parallel two stage cyclic ADC. This technique is associated with very short conversion time which enables a faster readout. Also, this technique lowers the power consumption because of its parallel and pipelined structure [3]. But in some cases this cyclic structure imposes a problem in the power consumption because of its high gain amplifier. Hence an alternative

method

approximation

was

which

adopted.

uses

It

switched

is

the

successive

power

technique

3 EXISTING SYSTEM The system is implemented using standard 130nm CMOS process. Based upon the incident illumination intensity the photocurrent created by the charge carriers results as voltage in the Photo Dioide (PD) node. The voltage at PD node triggers the inverter for time-to-threshold modulation as shown in figure 2. It produces an output whenever the signal reaches a threshold value.

The output is in the form of digital pulses in order to withstand the noise issues. The entire system architecture is shown in figure 1. In sub-micrometer technology, the inverter ensures stability under low supply voltage and minimal threshold variation. Under high illumination the voltage drop becomes faster and the discharge becomes slower under low illumination. The output of the inverter which is driven by the column line is mapped depending on the voltage at PD node.

P1.1

implemented by mi-seok et.al. This is used to reduce the area and

used should not increase the temperature of the sensor array, if temperature increases the dark current causes fixed pattern noise (FPN) which is undesirable. It limits the dynamic range of the

Row Buffer

pixel size becomes a major concern. The conversion technique

Row Decoder (reset/enable)

technique in order to achieve high pixel density. Shrinking the

enable Control Signal Generator

power simultaneously [4]. Seunghyun lim et.al illustrated a

P1.n

reset

Pm.1

Pm.n

reset enable

pixel. Column shared cyclic ADC is a better solution for this case.

It includes a built in variable gain amplifier and operates under

Column Buffer

1.5V supply [5]. The dynamic range could be enhanced by widening the bandwidth and incorporating a self offset cancellation scheme.

It eliminates the FPN created due to

comparator offset. Its output is similar to the amplified logarithmic response of human eye. In order to simultaneously

n-bit Counter

Time-to-Threshold Converter (TTC) DOUT

Counter Clock Row Readout Counter

To Application Circuitry

increase the frame rate and resolution high speed analog to digital Fig. 1. Time-to-Threshold architecture

IJTET©2015

140

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY

VOLUME 3 ISSUE 1 –JANUARY 2015 - ISSN: 2349 - 9303 The individual driver circuit is shown below.

Column_line<1>

Column_line<0>

VDD reset M2 M4

M3

Column line

M1

Column_line<0>

Column_line<N>

Column_line<1> Column Buffer

Column_line<N>

Column Buffer

CNT<0> CNT<0>

D Q D Q

D Q

D Q

D Q

D Q

enable

Fig. 2. Pixel architecture of 130nm CMOS process

3.1 CMOS Inverter as Comparator

CNT<n>

A photodiode is used to receive the light intensity. Initially the CNT<n>

D Q D Q

D Q

D Q D Q

D Q

operation starts with the assertion of reset signal. The reset signal is set to logic ‘0’ and enable is set to logic ‘1’. Based upon the incident illumination intensity the node charges towards VDD. The

DOUT_1 DOUT_1

DOUT_N

DOUT_2 DOUT_2

DOUT_N

incoming voltage is compared with the threshold voltage of the inverter. Based on this comparison a binary output is produced. In

Fig. 3. Schematic diagram of TTC Block

order to realize the 8-bit digital data the outputs driven by the column line is passed to the time-to-threshold converter (TTC).

4 PROPOSED SYSTEM The system is implemented using standard 45nm CMOS process.

3.2 Time-to-Threshold PWM Architecture

As the technology progress, the device density becomes higher.

The output from each column is fed as input to the TTC.

But increase in size and power consumption is not desired. Hence

The architecture of TTC includes a set of n-bit counters and D flip-

in order to reduce both, the processing technology is scaled down

flops as shown in figure 3. This structure produces an output

in the proposed system and the design is altered accordingly

whenever the signal reaches a threshold value. The counter is

which is shown in figure 4. This architecture also includes a

synchronized with a rising edge of the clock signal, which is

CMOS inverter which is driven by the voltage at PD node for

distributed to a set of n-bit registers. The column line output from

time-to-threshold modulation. The output driven by the column

the pixel is the input for D flip-flops which retains its output until the

line is fed to the TTC and mapped accordingly. The proposed

next column line is triggered. This system operates under 1.3V as a

system has the ability to work under a very low supply voltage of

four transistor structure with a power consumption of 36µW.

0.8V and as an area reduced two transistor structures with a power consumption of 3.7µW.

141 IJTET©2015

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY

VOLUME 3 ISSUE 1 –JANUARY 2015 - ISSN: 2349 - 9303

M1 M2 PD

Column line

VDD

enable

Fig. 6. Analysis of an individual unit-130nm

Fig. 4. Pixel architecture of 45nm CMOS process

5 SIMULATION RESULTS The simulation results for existing and proposed system is presented and the comparison is provided in the table 1. Figure 5

The differences between operating voltage, power and area for the existing and proposed system is given.

The comparison table is shown below.

explains the 8-bit output for a CIS implemented in 130nm

TABLE1

processing technology. Figure 6 explains the response of an

Results Comparison

individual pixel.

S.No.

System

Operating

Power

Area

Voltage 1.

Existing

1.3V

36µW

4T

2.

Proposed

0.8V

3.7µW

2T

Figure 7 explains the 8-bit output obtained using 45nm processing technology and figure 8 explains the response of an individual pixel. The output remains same for both processing technology.

Fig. 5. Analysis for 130nm array of pixels

The reduction in area and power could be realized by analyzing figure 6 and 8.

IJTET©2015

142

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY

VOLUME 3 ISSUE 1 –JANUARY 2015 - ISSN: 2349 - 9303 REFERENCES [1] Orit Skorka and Dileepen Joseph, ‘CMOS digital pixel sensors: technology and applications’ Electrical and computer Engineering, University of Alberta, Edmonton, AB, Canada, January 2014.

[2] Jimin cheon, student member, IEEE, Gunhee han, Member IEEE, ‘Noise analysis and simulation method for a single-slope ADC with CDS in a CMOS image sensor’ IEEE transactions on circuits and systems, Vol. 55, No.10, November 2008.

[3] Kazuya kitamura, Toshihisa Watabe, Takehide Sawamoto, Fig. 7. Analysis for 45nm array of pixels

Tomohiko Kosugi, Tomoyuki Akahori, Tetsuya lida, Keigo isobe, Takashi Watanabe, Hiroshi Shimamoto, Hiroshi ohtake, Satoshi Aoyama, Shoji Kawahito, Norifumi Egami Member IEEE, ‘A 33 mega-pixel 120 frames-per-second 2.5 watt CMOS image sensor with column parallel two stage cyclic analog to digital converters’ IEEE transactions on electron devices, Vol. 59, No.12, December 2012.

[4] Min-seok shin, Jong-Boo Kim, Min-Kyu Kim, Yun-Rae Jo, Oh-Kyong Kwon Student Member IEEE, ‘A 1.92 mega-pixel CMOS image sensor with column parallel low power and area efficient SA ADC’ IEEE transactions on electron devices, Vol 59, No.6, June 2012.

[5] Seunghyun lim, Jimin Cheon, Youngcheol Chae, Wunki Jung,

Fig. 8. Analysis of an individual unit-45nm

student Member IEEE, ‘A 1/3.4 inch 2.1-Mpixel 240 frames/s

6 CONCLUSION The proposed

architecture using standard

Dong-Hun Lee, Seogheon Ham, Dongsoo Kim, Gunhee Han

45nm CMOS

technology is a highly robust design. It has the ability to operate under 0.8V. This structure provides different pulse widths based on the level of luminance. This design is highly compatible and facilitates the rapid growth in device density. It does not require a conventional ADC which is desired by low-power portable

CMOS image sensor’ IEEE Journal of solid state circuits Vol. 46, No. 9, September 2011.

[6] Cheng-Hsiao lai, Ya-Chin King, Shi-Yu Huang Member IEEE, ‘A 1.2V 0.25µm clock output pixel architecture with wide dynamic range and self offset cancellation’,

IEEE sensors

journal, Vol. 6, No.2, April 2006.

imaging systems such as On-chip autonomous wireless security cameras and disposable medical cameras.

IJTET©2015

143