Effective Area and Power Reduction for Low-Voltage CMOS Image Sensor Based Applications

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INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY

VOLUME 3 ISSUE 1 –JANUARY 2015 - ISSN: 2349 - 9303

Effective Area and Power Reduction for Low-Voltage CMOS Image Sensor Based Applications B.GOMATHI1

D.VEERA VANITHA2

1

Avinashilingam Institute for Home Science and Higher

2

Avinashilingam Institute for Home Science and Higher

Education for Women-University,

Education for Women-University,

Department of Electronics and Communication Engineering,

Department of Electronics and Communication Engineering,

Gomathi.sri91@gmail.com

vanitha.svc@gmail.com

Abstract— This paper presents a novel CMOS image sensor (CIS) based on 45nm processing technology. It includes a single inverter time-to-threshold pulse width modulation circuitry, capable of operating under very low supply voltage. Conventional CMOS image sensors implemented using 130nm processing technology had many advantages. But in order to incorporate additional processing circuitry, the device density increases which results in degradation in the speed of operation. Scaling of physical MOS device dimensions improves both speed and density. The leakage associated with scaling could be eliminated by re-designing the circuit. As result area and power consumption could be reduced, which is demanded by portable imaging equipments.

Index Terms— CIS, nm, time-to-threshold, PWM. 

1 INTRODUCTION Area and power minimization is considered as a primary challenges in wireless sensing systems. The size of the sensor plays a major role in portable image sensor based equipments.

A CIS based on pulse width modulated output is adopted in this

The sensor should have high Signal-to-Noise ratio (SNR), low

paper. This technique uses a CMOS inverter as a comparator.

dark current, high sensitivity, reduced noise and smaller pixel

Instead of a more conventional ADC a time-to-threshold

size. The shrinking of pixel size should not impart the quality of

conversion technique is implemented. This paper is formulated as

the image. A high quality image is desired after all the processing

follows. Section II provides a brief explanation about the related

techniques. The miniaturization of pixel size was also limited

work. Section III illustrates the existing work. Section IV

noise effects and leakage current. To overcome the problems

introduces the proposed work which is followed section V,

associated with shrinking digital pixel sensor was introduced. It

experimental results and comparison finally section VI provides

includes on-pixel Analog to Digital converter (ADC) and

the concluding remarks.

achieves a higher SNR.

IJTET©2015

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