Performance Analysis of Input Vector Monitoring Concurrent Built In Self Repair and Diagnosis

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INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 4 ISSUE 1 – APRIL 2015 - ISSN: 2349 - 9303

Performance Analysis of Input Vector Monitoring Concurrent Built In Self Repair and Diagnosis S. Gurunagalakshmi1

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S. Ravanaraja2 Kalasalingam University, ECE Department sravanaraja@gmail.com

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Anna University, ECE Department, Guru.coolbreeze@gmail.com

Abstract—Built-in self test (BIST) techniques constitute an attractive and practical solution to the problem of testing VLSI circuits and systems. Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the circuit without imposing a need to set the circuit offline to perform the test. These schemes are evaluated based on the hardware overhead and the concurrent test latency (CTL). CTL means that the time required for the test to complete, whereas the circuit operates normally. In this brief, we present a novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM like structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the proposed scheme is shown to perform significantly better than previously proposed schemes with respect to the hardware overhead and CTL tradeoff. The proposed method also performs novel BISD and BISR schemes based on the fail pattern identification and also binary matrix lossless compression scheme to compress the test patterns in test cubes. Index Terms— BIST-Built In Self Test, CBU- Concurrent BIST Unit, CUT- Circuit Under Test, TPG- Test Pattern Generator. ——————————  ——————————

1 INTRODUCTION

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UILT In Self Test(BIST) techniques constitute a class of schemes that provide the capability of performing at-speed testing with high fault coverage, whereas at the same time they relax the reliance on expensive external testing equipment. therefore they constitute an attractive solution to the problem of testing VLSI devices[2]. BIST techniques are typically classified into offline and online. In offline BIST the normal operation of the CUT is stalled in order to perform test. The use of offline Built-In Self Test (BIST) technique interrupts the normal operation of the circuit under test. So the performance of the circuit gets degraded. The BIST circuit can be operated in two modes. They are named as normal mode and test mode. During test mode, the inputs generated by a test generator module are applied to the inputs of the circuit under test (CUT) and the responses are captured into a response verifier (RV). Therefore, to perform the test, the conventional operation of the CUT is stalled consequently, the performance of the system in which the circuit is included, is degraded. Input vector monitoring concurrent BIST techniques [3], [11] have been proposed to avoid this performance degradation. These architectures, test the CUT concurrently with its normal operation by exploiting input vectors appearing to the inputs of the CUT; if the incoming vector belongs to a set called active test set, the RV is enabled to capture the CUT response. The CUT has n inputs and m outputs and is tested exhaustively; hence, the test set size is N = 2n. The technique can operate in either normal or test mode, depending on the value of the signal labeled T/N. During normal mode, the vector that drives the inputs of the CUT (denoted by d[n:1] in Fig. 1) is generated from the normal input vector (A[n:1]). A is also given as input vector to a concurrent BIST unit (CBU), where it is compared with the active test set. If it is

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found that A matches one amongst the vectors in the active test set, we are saying that a hit has occurred. In this case, A is removed from the active test set and the signal response verifier enable (rve) is issued, to enable the m-stage RV to capture the CUT response to the input vector [2]. When all input vectors have performed hit, the contents of RV are examined. During test mode, the inputs to the CUT are generated by the CBU outputs denoted TG[n:1]and driven to the CUT inputs. The concurrent test latency (CTL) of an input vector monitoring scheme is the mean time (counted either in


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