Performance Analysis of Input Vector Monitoring Concurrent Built In Self Repair and Diagnosis

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 4 ISSUE 1 – APRIL 2015 - ISSN: 2349 - 9303

Performance Analysis of Input Vector Monitoring Concurrent Built In Self Repair and Diagnosis S. Gurunagalakshmi1

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S. Ravanaraja2 Kalasalingam University, ECE Department sravanaraja@gmail.com

1

Anna University, ECE Department, Guru.coolbreeze@gmail.com

Abstract—Built-in self test (BIST) techniques constitute an attractive and practical solution to the problem of testing VLSI circuits and systems. Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the circuit without imposing a need to set the circuit offline to perform the test. These schemes are evaluated based on the hardware overhead and the concurrent test latency (CTL). CTL means that the time required for the test to complete, whereas the circuit operates normally. In this brief, we present a novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM like structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the proposed scheme is shown to perform significantly better than previously proposed schemes with respect to the hardware overhead and CTL tradeoff. The proposed method also performs novel BISD and BISR schemes based on the fail pattern identification and also binary matrix lossless compression scheme to compress the test patterns in test cubes.

Index Terms— BIST-Built In Self Test, CBU- Concurrent BIST Unit, CUT- Circuit Under Test, TPG- Test Pattern Generator.

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1 INTRODUCTION

B

UILT In Self Test(BIST) techniques constitute a class of schemes that provide the capability of performing at-speed testing with high fault coverage, whereas at the same time they relax the reliance on expensive external testing equipment. therefore they constitute an attractive solution to the problem of testing VLSI devices[2]. BIST techniques are typically classified into offline and online. In offline BIST the normal operation of the CUT is stalled in order to perform test. The use of offline Built-In Self Test (BIST) technique interrupts the normal operation of the circuit under test. So the performance of the circuit gets degraded. The BIST circuit can be operated in two modes. They are named as normal mode and test mode. During test mode, the inputs generated by a test generator module are applied to the inputs of the circuit under test (CUT) and the responses are captured into a response verifier (RV). Therefore, to perform the test, the conventional operation of the CUT is stalled consequently, the performance of the system in which the circuit is included, is degraded.

Input vector monitoring concurrent BIST techniques [3], [11] have been proposed to avoid this performance degradation. These architectures, test the CUT concurrently with its normal operation by exploiting input vectors appearing to the inputs of the CUT; if the incoming vector belongs to a set called active test set, the RV is enabled to capture the CUT response. The CUT has n inputs and m outputs and is tested exhaustively; hence, the test set size is N = 2n.

The technique can operate in either normal or test mode, depending on the value of the signal labeled T/N. During normal mode, the vector that drives the inputs of the CUT (denoted by d[n:1] in Fig. 1) is generated from the normal input vector (A[n:1]). A is also given as input vector to a concurrent BIST unit (CBU), where it is compared with the active test set. If it is

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found that A matches one amongst the vectors in the active test set, we are saying that a hit has occurred. In this case, A is removed from the active test set and the signal response verifier enable (rve) is issued, to enable the m-stage RV to capture the CUT response to the input vector [2]. When all input vectors have performed hit, the contents of RV are examined. During test mode, the inputs to the CUT are generated by the CBU outputs denoted TG[n:1]and driven to the CUT inputs. The concurrent test latency (CTL) of an input vector monitoring scheme is the mean time (counted either in

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 4 ISSUE 1 – APRIL 2015 - ISSN: 2349 - 9303 number of clock cycles or time units) required to complete the test while the CUT operates in normal mode. Increasing the hardware overhead can decrease the concurrent test latency.

2 PROPOSED METHOD Let us consider a combinational CUT with n=5 input lines, as shown in Fig. 2; hence the possible input vectors for this CUT are 2n. The proposed scheme is relies on the thought of monitoring a window of vectors, whose size is W, with W = 2w, where w is an integer number w < n. Every moment, the test vectors belonging to the window are monitored, and if a vector performs a hit, the RV is enabled. The number of bits of the input vector are separated into two distinct sets comprising w and k bits, respectively, such that w + k = n. The k (high order) bits of the input vector show whether the input vector belongs to the window under consideration. The w remaining bits show the relative location of the incoming vector in the window under consideration. If the incoming vector belongs to the current window and has not been received throughout the examination of the current window, we say that the vector has performed a hit and the RV is clocked to capture the CUTâ&#x20AC;&#x2122;s response to the vector. When all vectors that belong to the current window have reached the CUT inputs, we proceed to examine the next window. The module implementing the thought is shown in Fig. 2.

outputs of the decoder are equal to one. When comparator (cmp) is disabled (and tge is not enabled) all outputs are disabled. When tge is disabled and cmp is enabled, the module operates as a normal decoding structure.

The architecture of the proposed scheme for the input vector has the size of n = 5, k = 2, and w = 3, is shown in Fig. 2. The module labeled logic in Fig. 2 is shown in Fig. 3. It comprises W cells (operating in a fashion similar to the SRAM cell), a sense amplifier, two D flip-flops, and a w-stage counter (where w = log2W). The overflow signal of the counter drives the tge signal through a unit flip-flop delay. The signals clk_ and clock (clk) are enabled during the active low and high of the clock, respectively. In the sequel, we have assumed a clock that is active during the second half of the period, as shown in Fig.3. In the sequel, we describe the operation of the logic module, presenting the following cases: 1) reset of the module; 2) hit of a vector (i.e., a vector belongs in the active window and reaches the CUT inputs for the first time); 3) a vector that belongs in the current window reaches the CUT inputs but not for the first time; and 4) tge operation (i.e., all cells of the window are filled and we will proceed to examine the next window). During normal mode, the inputs to the CUT are driven from the normal inputs. The n inputs are also driven to the CBU as follows: the w low-order inputs are driven to the inputs of the decoder; the k high-order inputs are driven to the inputs of the comparator. When a vector belonging to the current window reaches the inputs of the CUT, the comparator is enabled and one of the outputs of the decoder is enabled. During the first half of the clock cycle (clk_ and cmp are enabled) the addressed cell is read; because the read value is zero, the w-stage

BIST circuit operates in one out of two modes, normal, and test, depending on the value of the signal T/N. When T/N = 0 (normal mode) the inputs to the CUT are driven by the normal input vector.

The inputs of the CUT are also driven to the CBU as follows: the k (high order) bits are driven to the inputs of a k-stage comparator; the other inputs of the comparator are driven by the outputs of a k-stage test generator TG. The comparator compares both combination of bits and returns a value. The proposed scheme uses a modified decoder and a logic module based on a static-RAM (SRAM)-like cell, as will be explained shortly. The m_dec module for w = 3 operates as follows. When a test generator enable (tge) is enabled, all

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INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 4 ISSUE 1 – APRIL 2015 - ISSN: 2349 - 9303 counter is triggered through the NOT gate with output the response verifier enable (rve) signal. During the second half of the clock cycle, the left flip-flop (the one whose clock input is inverted) enables the AND gate (whose other input is clk and cmp), and enables the buffers to write the value one to the addressed cell.

In order to test these systems, each unit must be tested by using a set of pre computed test pattern. Small numbers of test patterns would be required to test the simple circuits. Many large circuits require large numbers of test vectors to attain high test coverage of these circuits. An efficient test pattern generator (TPG) is needed to generate the test patterns for these circuits. The test pattern generated by the test pattern generator (TPG) should have minimum number of faulty test pattern and it would be satisfy the requirement of the circuit. The reduction in test-data volume not only reduce the memory requirements, but also reduce the testing time. The test pattern generator generates the pseudo random test patterns. It is constructed by using Linear Feedback Shift Registers (LFSR). The test pattern generator (TPG) is constructed by using flip flops and mod-2-adder. By using m number of flip flops, a test vector consisting of 2m-1 number of bits van be generated. The architecture of Test Pattern Generator (TPG) is shown in fig. 4.

had lost some information. In lossless compression the original data can be retrieved without any loss of information.

This paper proposes a binary matrix lossless compression scheme to compress the test patterns in the test cubes. The following steps are to be taken to compress the test patterns.

The test patterns generated by the TG are converted into its equivalent decimal values and are denoted as original matrix [OR]. The steps involved in compressing the test patterns are as follows. Read the original matrix. Construct the Binary matrix [BM] and Gray Scale Matrix [GSM]. The binary matrix can be calculated as follows. The initial value of the binary matrix [BM] had set as 1 by default. Then the first and second element of the [OR] is compared and the output value is 0 if both were equal otherwise the value is 1. Likewise all the values are calculated and finally the binary matrix[BM] can be obtained.

0 if [OR]i,j = [OR]i,j+1 [BM]i,j = 1 otherwise

The Gray Scale Matrix can be calculated as follows.

Null if [OR]i,j = [OR]i.j+1 [GSM]k = [OR]i,j otherwise

After compression the original data can be reconstructed as follows.

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BINARY MATRIX LOSSLESS COMPRESSION SCHEME

Test data compression is a test resource partitioning scheme whose main target is to reduce the volume of test data. The test pattern generated by the test pattern generator needs a large amount of memory space to store the test pattern. So a compression mechanism is required to compress the test patterns. The compression mechanism is generally classified

[GSM]k if [BM]i,j = 0 [RM]i,j = [GSM]k+1 if [BM]i,j = 1

4 BUILT IN SELF DIAGNOSE AND REPAIR SCHEME Built-in self test detects the presence of error. But, it did not diagnose or repair the error present in the test set. In this paper we propose the Novel Built-in Self Diagnose (BISD) and Built-in Self Repair (BISR) based on the fail pattern identification. The test pattern is decompressed and the syndrome pattern is calculated for each test pattern in the test set.

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 S. Grunagalakshmi is currently pursuing masters degree program in applied electronics in Anna University,India,. E-mail: guru.coolbreeze@gmail.com..  S. Ravanaraja pursued masters degree program in VlSI design in Kalasalingam University and currently working as Asst.prof in R.V. S College of Engineering & Technology, India,. E-mail: sravanaraja@gmail.com

as lossy compression and lossless compression. In lossy compression the original data retrieved after decompression

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Syndrome1=rx[2]^rx[3]^rx[4]^rx[7]; Syndrome2=rx[1]^rx[2]^rx[3]^rx[6]; Syndrome3=rx[3]^rx[4]^rx[1]^rx[5];

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 4 ISSUE 1 â&#x20AC;&#x201C; APRIL 2015 - ISSN: 2349 - 9303 Depending on the value obtained after the syndrome calculation the error bit is located and then the repairing of test vector is done. The error bit is calculated as follows. rx=rx[1]^rx[2]â&#x20AC;Ś.^rx[7].

The faulty test pattern can be corrected and the new test pattern can be calculated as follows. New pattern = old pattern + rx

5 EXPERIMENTAL RESULTS The novel based BISD and BISR schemes provides a very efficient and effective solution for the identification and correction of fail pattern in the BIST circuit. The performance of this methodology is often evaluated by using the parameters such as latency and power of the circuit. The experimental results shows the power and latency report.

6 CONCLUSION

The power of the proposed method is 81mW. About 50.9% of power ate often reduced. It can be obtained by using the equation Power reduction = (p2 pwr/p1 pwr)* 100

BIST schemes constitute an attractive solution to the problem of testing VLSI devices. Input vector monitoring concurrent BIST schemes perform testing during the circuit normal operation without imposing a need to set the circuit offline to perform the test, therefore they can circumvent problems appearing in offline BIST techniques. The analysis criteria for this category of schemes are the hardware overhead and the CTL, i.e., the time required for the test to complete, while the circuit operates normally. In this brief, a novel input vector monitoring concurrent BIST architecture has been presented, based on the use of a SRAM-cell like structure for storing the information of whether an input vector has appeared or not during normal operation. The proposed scheme is shown to be more efficient than previously proposed input vector monitoring concurrent BIST techniques in terms of hardware overhead and CTL. The BISD and BISR scheme perform the fail pattern identification and repairing of the fail pattern in the test cubes. Thus this method is shown to be more efficient than the previously proposed method because it not only detect the error in the circuit, however additionally repair and correct the error in the test pattern. The binary matrix lose less compression scheme provides an effective compression methodology to compress the test patterns in the test cube.

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