Design And Analysis Of Low Power High Performance Single Bit Full Adder

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INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303

Design And Analysis Of Low Power High Performance Single Bit Full Adder JAYACHITHRA P1

SARAVANA KUMAR P2

1

2

PG Scholar of ECE department Kalasalingam Institute of Technology shyachithra@gmail.com

Asst. professor of ECE Department Kalasalingam Institute of Technology kumar271985@gmail.com

Abstract: Adder is the significant circuit in arithmetic operations. Adder cells are designed for power and delay reduction. Now ground bounce noise is also necessary for good performance. In this paper the full adder is designed using only 8 Transistors using Pass Transistor Logic (PTL). The power gating technique is one such a best technique which reduces leakage power through the ground. This technique is implemented using sleep transistor added between ground rail and actual ground. Here a single bit 8 Transistor full adder is proposed. We will perform analysis and simulation of various parameters like power, delay and ground bounce noise using tanner EDA tool 180nm CMOS Technology. Index terms- Full adder, Ground bounce noise, PTL, Sleep transistor

mode. In our paper 8 transistor full adder is designed with power gating technique to reduce noise, delay and area.

1. INTRODUCTION With the extensive development of electronic devices, the low power VLSI system is most important. The single bit full adder is used in various arithmetic operations, digital signal processing and micro controller. The area of full adder is the major concern for area reduction. The current 50-60 % affects the performance of system [1-2]. The full adder is designed with increased transistor count which is used in multiplexer, compressor and parity checker [3-5]. The ground bounce noise disturb the performance of device. The scope of paper is to implement full adder to reduce the power and delay [6-7]. To achieve reduced the ground bounce noise, forward body bias with multiple thresholds is introduced to add additional wait mode which separate the sleep and active mode [8]. The ground bounce noise and leakage current during mode transistor cause performance reduction. To overcome this stacking power gating technique is introduced [9]. The Nano CMOS technology is implemented for full adder but the area requirement is high compared to our paper [10]. The degenerate pass transistor logic is developed for low power requirement of full adder. But the threshold voltage loss problem occurred [11]. One of the most important techniques is MTCMOS also known as power gating technique which is used

2. 8T FULL ADDER DESIGN The full adder has been designed using various logic styles to reduce the area and power dissipation. PM1

PM2

B NM1

A

Sum

NM2

C

NM3 NM4

C

PM3

Carry

A NM5

Figure 1: 8T full adder

for reduce the leakage power and leakage current in an idle mode and to improve the performance of device in active mode [12-13]. The main idea behind this technique is to turn off the device in sleep

To analyses the various parameters of adders we use the pass transistor 8T full adder as our base structure as shown in the figure 1 which have 2 xnor

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Design And Analysis Of Low Power High Performance Single Bit Full Adder by International Journal for Trends in Engineering and Technology - Issuu