Implementation of Stopwatch using QCA based Carry Select Adder

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303

Implementation of Stopwatch using QCA based Carry Select Adder M.Priyanga1 1

2

Kalasalingam Institute of Technology, M.E(VLSI Design), priyangamanoharan057@gmail.com

R.Subhashini2 Kalasalingam Institute of Technology, AP/ECE Subhashini.rj@gmail.com

Abstract— As transistor size reduces and more of them can be accommodated in a single die, thus rising chip computational capabilities. However, transistors cannot get smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit. The design of adders on quantum-dot cellular automata has been of recent interest. This paper presents an efficient QCA design for the Carry Select Adder (CSA). The QCA based CSA has better performance in terms of area and delay than the existing RCA. The application of this QCA based Carry Select Adder in stopwatch also designed.

Index Terms— Transistor size, Quantum-dot Cellular Automata ,Carry Select Adder, Stopwatch, Ripple Carry Adder, ——————————  ——————————

1 INTRODUCTION CMOS Technology is approaching its scaling limit very fast. In practical point of view CMOS technology in nano-scales are facing many troubles. So in order to enhance the performance of a system new nanotechnology approach should be taken into account. Quantum Cellular Automata is one of the promising and emerging technologies which providing a solution at nanoscale and CMOS technology.Quantum-dot cellular automata (QCA) is an advanced technique in VLSI technology. It is suitable for the development of ultra-dense , low-power , high-performance digital circuits. For this reason the design of efficient logic circuits in QCA has received a great deal of scrutiny. Special efforts are directed to arithmetic circuits, with the main interest on the binary addition that is the basic operation of any digital system.

QCA is based on the interaction of bi-stable QCA cells constructed from four quantum-dots. A high-level diagram of two polarized QCA cells is shown in Fig. 1. Each cell is constructed from four quantum dots arranged in a square pattern. These electrons occupy antipodal sites as a result of their mutual electrostatic revulsion. Thus, there exist two equivalent energetically minimal arrangements of the two electrons in the QCA cell as shown in Fig. The schematic representation of the basic cell of an electrostatic-based QCA is illustrated in Fig. 1 that also shows the two possible states of electrons in quantum dots through which the binary information is encoded. Adjacent cells interact with each other through electrostatic forces and a zone clocking scheme is usually exploited to provide controllable data directions.

Fig.1. QCA cells.

Four clock signals, each phase shifted by 90’, are used to

scan the switch, hold, release, and relax phases. Clock signals are generated by means of clocking wires that run under the surface containing the QCA cells and modulate their energy barriers. All the cells above the same clock wire belong to the same clock zone.

Arrays of QCA cells can be arranged to perform all logic functions. This is due to the Coulombic interactions, which influences the polarization of neighboring cells. QCA architectures have been proposed with potential barriers between the dots that can be controlled and used to clock QCA circuits.

2

CARRY SELECT ADDER IN QCA

A QCA is a nanostructure having as its basic cell a square four quantum dots structure charged with two free electrons able to tunnel. through the dots within the cell. Because of Coulombic revulsion, the two electrons will always reside in facing corners. The locations of the electrons in the cell determine two possible stable states that can be associated to the binary states 1 and 0.

A quantum dot cellular automata is an advanced model of quantum computation. This is the mechanism in analog to digital standard model of cellular automata established by von Neumann. A cellular automaton is a finite state machine. It is consisting of an uniform grid of cells. Each cell can be in only one finite number of states at the discrete time. Quantum dot is a nanocrystal made of semiconductor material. Electronic characteristics of a quantum dots are closely related to its size and shape.

The QCA paradigm is based on a cell with four quantum dots. Each QCA cell is employed by two electrons. Fundamental QCA logic devices are the three-input majority gate and inverter. A clocking mechanism is used to cause electrons to tunnel through to the appropriate locations. A four-phase clocking scheme is commonly used.

Cellular automata are commonly implemented as software program only. but now a day cellular automata is implemented as the physical implementation using quantum cells is called Quantum dot cellular automata. QCA used 4 dots arranged in square pattern. The advantages of Quantum dot cellular automata is easier logic mapping, minimal routing requirements, power consumption is significantly low compare to CMOS and interconnects designed with

104

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303

QCA would be faster and would work almost up to the speed of the processing device which would be drastically enhanced the system performance.

Fig. 3. Novel n-bit adder (a) carry chain and (b) sum block.

Fig.2. Novel 2-bit basic module.

QCA cells are used for both logic structures and interconnections that can exploit either the coplanar cross or the connection procedure. The fundamental logic gates inherently available within the QCA technology are the inverter and the MG. Given three inputs a, b, and c, the MG acts the logic function described in providing that all input cells are associated with the same clock signal , whereas the remaining cells of the MG are associated with the clock signal clkx +1.

M(abc)=a.b+a.c+b.c

(1)

Equation (1) describes the carry block. Many styles of adders in QCA exist in literature. The RCA and also the CFA method n-bit operands by cascading n full-adders (FAs) Even supposing these addition circuits use totally different topologies of the generic full adder, they need a carry-in to carry-out path consisting of one MG, and a carry-in to sum bit path containing two MGs plus one inverter.

M(abc) =a|b|c

(2)

The main mercantilism of trading off area and delay, the hybrid adder (HYBA) delineate in combining a parallel prefix adder with the RCA. Within the presence of n-bit operands, the design incorporate a worst computational path consisting of 2 × log2n + 2 cascaded MGs and one inverter. Once the methodology recently projected in was exploited ,the worst case path of the CLA is reduced to 4 × log4 n + 2 ×log4 n − 1 MGs and one inverter. The preceding approach will be applied to conjointly design the BKA. During this case the overall area is reduced with relation to, however , maintaining the same computational path.

The carry select adder consists of RCA and MUX. It computes (n+1) bit sum of 2-bit numbers. The basic building block is two 4-bit RCA and MUX. Twice two ripple carry adders are used , one time assume zero, other assume one. The resulting carry and sum bits are selected by the Cin. Two results are calculated, the correct sum as well as the correct carry is then selected to mux once correct carry is known. Carry will be considered. Cout of each section determines the Cin of the next section. The very first section has a carry in of zero. Particular way to implement an adder which is a logic element that computes the (n+1)bit sum of two n-bit numbers.

The advantages of carry select adder is simple, very fast, being able to calculate all input bits nearly simultaneously. In digital adders, the speed of the addition is limited by the time required to propagate a carry through the adder. The design of the novel 2-bit module shown that also shows the computation of the carry ci+1 = M( pi gi ci ).

The sum bits are finally computed as shown. It must be noted that the time critical addition is performed when a carry is generated at the least significant bit position (i.e., g0 = 1) and then it is propagated through the subsequent bit positions to the most significant one. The subsequent 2-bit modules contribute with only one MG each, thus proposing a total number of cascaded MGs equal to (n − 2)/2.considering that further two MGs and one inverter are required to compute the sum bits, the worst case path of the novel adder consists of (n/2) +3 MGs and one inverter.

3

STOPWATCH

The Stopwatch is timepiece equipment which is designed to measure the amount of time elapsed from a particular time when activated to when it is deactivated.

Stopwatch has the most commonly used functionalities  Start  Pause  Reset

105

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303

Start is used to trigger the counting on the stop-watch.

When this input is activated from an initial state, the watch increases every second counting from 0 to 59 and then looping back to 0. The counting process continued until and unless any other input (stop or reset) is activated.

Pause is used to stop the stopwatch counting. When the stop button is pressed the stopwatch stops counting and displays the time (in seconds) continuously, until any other input (resume/reset) is pressed.

Reset is used to reset the stopwatch display to 0. When the reset button is pressed, stop watch is reset to zero (the display should read 0) and should hold this value zero until the start/resume button is activated.

The block diagram consists of buffer, comparator, multiplexer and CSA .it has three stages (second, minutes, hour).buffer is used to store the data. The comparator is a devise for comparing measurable value with a reference value. The comparator is used to compare the input value, when the second is increased by 59 then minutes is increased by one. When the minute is increased by 59 then hour is increased by one. The multiplexer is an electronic device that selects one of the selected input and forward the selected input into the buffer. The comparator output is given to the Cin of the next stage. The output is getting from CSA.

Fig.5. Result of SUM Chain.

Fig.6. Result of CARRY Chain.

Fig.4.Block diagram of stopwatch

4

SIMULATION RESULTS.

The carry select adder using QCA technique is simulated in Xilinx 13.2 and modelsim and the various results are shown below.

Fig.7. Result of INITIAL CARRY Chain.

106

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 [4]

[5]

[6]

[7]

[8]

[9]

Fig.8. Result of 64-bit adder.

[10]

[11]

[12]

[13]

[14]

[15]

W. Liu, L. Lu, M. O’Neill, and E.E. Swartzlander, Jr., “Design rules for quantum-Dot cellar automata,” in Proc. IEEE Int. Symp.

Circuits Syst., May 2011, pp. 2361-2364 K. Kim, K. Wu, and R. karri, “ Toward designing robust QCA architectures in the presence of sneak noise paths,” in Proc. IEEE Design, Autom. Test Eur. Conf. Exhibit., Mar. 2005, pp. 12141219.

K. Kong, Y. Shang, and R. Lu, “An optimized majority logic synthesis methodology for quantum-dot cellular automata,” IEEE Trans. Nanotechnol.,vol.9, no.2, pp. 170-183, Mar.2010.

K. Walus, G. A. Jullien, and V. S. Dimitrov. “Computer arithmetic structures for quantum cellular automata,” in Proc. Asilomar Conf. signals, syst. Comput., Nov. 2003, pp. 1435-1439.

J. D. Wood and D. Tougaw, “Matrix multiplication using quantumdot cellular automata to implement conventional microelectronics,” IEEE Trans. Nanotechnol., vol. 10, no. 5, pp. 1036-1042, Sep. 2011.

K. Navi, M. H .Moaiyeri, R .F. Mirzaee, O.Hashemipour, and B. M. Nezhad, “Two new low-power full adders based on majority-not gates,” Microelectron. J., vol. 40, pp. 126-130, Jan. 2009.

L. Lu, W. Liu, M. O’Neill, and E.E. Swartzlander, Jr., “ QCA systolic array design,” IEEE Trans. Comput., vol. 62, no. 3, pp.

548-560, Mar. 2013.

H. Cho and E. E. Swa1rtzlander, “Adder design and analyses for quantum-dot cellular automata,” IEEE Trans. Nanotechnol., vol 6 no.3,pp.374-383, May 2007.

H. Cho and E. E. Swartzlander, “Adder and multiplier design in quantum-dot cellular automata,” IEEE Trans. Comput., vol. 58, no.

6, pp. 721-727, Jun. 2009.

V. Pudi and K. Sridharan, “Low complexity design of ripple carry and Brent-Kung adders in QCA,” IEEE Trans. Nanotechnol., vol.

11, no.1, pp. 105-119, Jan. 2012.

V. Pudi and K. Sridharan, “Efficient design of a hybrid adder in quantum-dot cellular automata,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 9, pp. 1535-1548, Sep. 2011.

S. Perri and P. Corsonello, “ New methodology for the design of efficient binary addition in QCA,” IEEE Trans. Nanotechnol., vol.

11, no. 6, pp. 1192-1200, Nov.2012.

Fig.9. Result of stopwatch.

5 CONCLUTION

Author Profile:

A new adder designed in QCA was presented. The Area and Delay performance is greater than all the existing QCA adders. An area requirement for the CSA is cheap compared with the RCA and CFA. The novel adder operated in the RCA manner, but it could propagate a carry signal through a number of cascaded MGs significantly lower than conventional RCA adders. Hence the proposed CSA implemented using QCA technique is an efficient one.

A stopwatch is a handheld timer. Stopwatch is implemented by using QCA based Carry select Adder.

REFERENCES C. S Lent, P. D. Tougaw, W. Porod, and G. H. Bernestein, “Quantum cellular automata,” Nanotechnology, vol. 4, no. 1,pp. 4957, 1993.

[2] M. T. Niemer and P. M. Kogge, “ Problems in designing with QCAs: Layout = Timing .” Int. J. Circuit Theory Appl., vol. 29, no.

1, pp. 49-62, 2001.

[3] J. Huang and F. Lombardi, and Test of Digital Circuits by Quantum-Dot Cellular Automata. Norwood, MA, USA: Artech House, 2007.

[1]

107

 M. Priyanga is currently pursuing masters degree program in VLSI Design in Kalasalingam Institute of Technology, India.

E-mail: priyangamanoharan057@gmail.com  R. Subhashini is currently pursuing Assistant Professor in ECE dept., in Kalasalingam Institute of Technology, India.

E-mail: subhashini.rj@gmail.com