108 An Efficient Execution of Clock Gating Technique for Logic Circuits

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303

An Efficient Execution of Clock Gating Technique for Logic Circuits S.Sri Kanchana Devi1

R.Rajalakshmi M.Tech2

1

2

PG Scholar, Kalasalingam Institute Of Technology(Affi), Anna University,Srivilliputur. sakthisri28@gmail.com

Asst.Prof of ECE, Kalasalingam Institute Of Technology(Affi), Anna University,Srivilliputur. rajeemtech@gmail.com

Abstract — Clock gating has been heavily used in reducing the power consumption of the clock network by limiting its activity factor. Fundamentally, clock gating reduces the dynamic power dissipation by disconnecting the clock from an unused circuit block. This result in three major components of power consumption: power consumed by combinational logic whose values are changing on each clock edge; power consumed by flip-flops; power consumed by the clock tree in the design. Here clock gating approach is done for various logic circuits in response to examine its application.

Index terms— Clock gating; activity factor .

asking for and discharging of the rarely used routine. The average power dissipated in an electronic routine is given as.

1. INTRODUCTION Decreasing energy intake in very extensive incorporated circuit (VLSI) style has become an interesting analysis place.

Most of the convenient gadgets available in the market are battery power motivated. These gadgets encourage a limited restriction on the energy dissipation. Decreasing energy intake in such gadgets enhances battery power significantly. Due to smaller progression in battery power technology, low energy style has become a more challenging analysis place.

Paverage = Pdynamic + Pshort-circuit + Pleak +Pstatic

(1)

Paverage is the common power dissipation, Pdynamic is the dynamic power dissipation due to changing of transistors, Pshortcircuit is the short-circuit present power dissipation when there is a dc direction from power source down to the floor, Pleak is the ability dissipation due to leak voltages, P static and is the static power dissipation

Power has become a primary consideration during component style. Dynamic energy can play a role up to 50% of the total energy dissipation. Clock-gating is the most common RTL marketing for reducing dynamic energy. Effective clockgating execution requires competent application and extensive confirmation.

1) Static Power Static power is the ability dissipated by a gate when it is non-active or non-productive.

Preferably, CMOS (Complementary Metal Oxide Semiconductor) circuit goes away no static (DC) power since in the stable condition; there is no immediate direction from Vdd to the floor.

There is a range of clock-gating techniques available to designers. Clearly not all of these are equivalent when it comes to reducing changing activity. Many changes are simple, while others are highly protected, trademarked methods. Most clockgating is done at the Register Transfer Level (RTL). RTL clock-gating methods can be arranged into three categories: system-level, sequential and combinational. System-level clock-gating blocks clock for an entire prevent, effectively limiting all performance. On the opposite, combinational and sequential clock-gating precisely hold clocking while the block is constantly on the produce outcome.

2) Dynamic power Dynamic power is the ability dissipated during effective condition due to changing activity of feedback indication. Since a feedback can modify without actually leading to reasoning conversion in the outcome, dynamic power can be dissipated even when an outcome doesn’t modify its reasoning condition.

This part of dynamic power dissipation is caused by asking for and discharging parasitic capacitances in the routine. Dynamic power dissipation in a routine is given as:

Energy absorbed in a electronic routine is of two kinds. (1) Static power and (2) Dynamic power. Static power includes power dissipated due to leak voltages whereas dynamic power includes capacitive changing power and brief routine power. In VLSI routine time indication is used for the synchronization of effective elements. Clock power is a significant part of power mainly because time is fed to most of the routine blocks, and time changes every pattern. Thus the complete time power is a significant part of complete power dissipation in an electronic routine. Clock-gating is a well-known strategy to decrease time power. In a sequential circuit individual block utilization relies on the program, not all the blocks are used at the same time, providing an increase to dynamic power decrease chance. By clock gating strategy, time to a nonproductive section is impaired, thus preventing the power dissipation due to needless

pd=αCL fV 2dd

(2)

Where α is the charging activity , f is the function regularity, CL is the fill capacitance, Vdd is the given volts.

3) Short-Circuit Power The short-circuit power intake, P short-circuit, is due to the present circulation through the immediate direction current between the ability source and the floor during the conversion stage.

4) Leakage Power

108

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 The PMOS and NMOS transistors used in a CMOS reasoning routine generally have non-zero opposite leak and sub-threshold voltages. These voltages can promote the complete power dissipation even when the transistors are executing any charging activity. The leak power dissipation, P leak is due to two kinds of leak voltages. a)Reverse-bias diode leak present. b)Sub threshold current through a turned-off transistor circuit.

methods is clock gating, whereby the clock indication is precisely obstructed for signs up in the style that are non-active or do not otherwise need to be modified, thus reducing the common capacitance that must be turned per pattern [8]. The most common approach is to personally recognize structural elements that can be deactivated, but in this work, we focus on automated methods that can be used to net list-level circuit. The condition under which is a register’s clock can be cased may be based on its current and next state features, and past methods have considered such direct calculations and features.

2. RELATED WORK The clock distribution system and registers regularly apply 40% of the power attracted by a processor [5]. The techniques suggested for reducing clock power integrate preventing needless moment of signs up by clock gating, using double edge-activated flip-flops to split the clock repeat [6], and providing clock inverters by working together a few flip-flops into a multibit flip-flop. In the research of low power and low volts VLSI tour, the use and execution of double edge triggered flip-flop (DETFF) has obtained more attention at the gate stage style. The benefit of using DETFF is that it allows one to maintain a continuous throughput while working at only 50 percent the clock regularity. This dissertation analyzes four previously released to fix double edge triggered flip-flops (DETFFs) together with the style for their performances, power dissipation, and low volts, low power programs. For each DETFF, the maximum wait, power intake, and power are identified as the primary source of benefit.

A clock buffer was built to decrease the energy intake, particular segments of time shrub which is a nonproductive was kept in off state by gating time alerts [9]. Approximation criteria and actual criteria were used to fix gate placement problem. The idea NP-representative (NPR) which is exclusive for any NP-equivalence sessions, and provided a desk look-up centered breadth-first search criteria to quickly estimate it; we used NPRs to effectively check the running equivalence of a given routine against a huge collection under permutation and complementation of outcome. The method is more than two purchases of scale quicker than Hinsberger-Kolla’s criteria. The strategy is easy for features with up to seven variables; this number is completely huge to work with many mobile collections such as lib2, which includes ranges up to six information and is substantially used by the research team.

A bottom-up strategy [10] for the automated removal and features of powerful energy control circuits beginning from architectural logic-level requirements. Our methods make use of the lightweight BDD-based reflection of Boolean and pseudo-Boolean features to identify nonproductive circumstances where time can be ceased without allow precise probabilistic computations; in particular, they allow the use of non-equiprobable main feedback withdrawals, a key step in the development of designs that coordinate the actions of real component gadgets with a high level of constancy. The results are motivating, since energy benefits of up to 34% have been acquired on conventional standard routine Dynamic energy control is probably the single most effective strategy for energy minimization ion in digital techniques.

The suggested style shows the least power at low currents.

In order to show the advantages in using DEFTTs over traditional single-edge triggered flip-flops (SETFFs), a digital half-band FIR filter is designed, used and used as a standard routine for further research. The execution of the FIR filter with DETFFs displays power preserving of 38% over the execution with SETFFs. Today’s technological innovation makes possible highly effective computers with multi-media abilities.

Customer’s behavior is geared towards better availability and flexibility.

Gate level net list is given to draw out the gating operate of each attach [7]. To decrease the amount of additional reasoning this gating operates is combined. Heuristic criteria considering three gating features are evaluated in terms of power preserving and area using 45nm technology. Also attach is motivated by brief clock beats. The primary goals are reducing the number of impulses and reduce additional reasoning to apply. For each gi possibility should be find by Picard peano version finally large p (gi) is chosen so that clock is private often. Time gating is the placement of combinational reasoning along the clock path to prevent the needles changing of signs up and decrease highly effective power intake. The circumstances under which the conversion of a sign-up may be securely obstructed can either be clearly specified by the designer or recognized instantly. We present a new means for instantly synthesizing these circumstances in a way that decreases net record perturbation and is both timing and physical-aware. Our automated technique is also scalable, using simulator and satisfiability assessments and requiring no representational reflection. On a set of standards, our technique efficient decrease the highly effective clock power by 14.5% on regular. Furthermore, we illustrate how to apply causing don’t likes you and decrease the reasoning by 7.0% on regular.

The Boolean actions reflection in Reduced Order Binary Decision Plan (ROBDP) [11].Flip-Flops which are not to be clocked was examined by these equations. Number of FlipFlops so known as keep websites, then clocked by gating indication. Hold and Non-hold expression are present in routine modification. Power intake is reduced to about 29%.

3. CLOCK GATING TECHNIQUE Today’s consumer needs more performances, power efficient program and enhanced power devices as time goes, so to be able to improve power of a program the easiest management strategy is to close off length of the successive block of the product when there is no function required from that area for some length. Clock gating is a strategy that can be used to manage power dissipated by the clock net is responsible for a significant part of power dissipation (up to 40%). Clock gating decreases the unwanted modification on the parts of the clock net by limiting time.

RTL clock gating is the most common strategy used for optimization and enhancing performances but still it results in one question that how efficiently style is clock private. Gated Clock is easily approved strategy to be able to improve power and can be applied at program stage, gate stage and RTL. Clock Gating can save more power by not clocking the sign-up if there is no change in its condition. Clock consistently takes in

The highly effective changing of the clock network typically records for 30-40% of the total power intake of a modern style, and with the growth of low-power requirements and hear restrictions, reducing this part of the power intake is crucial. One of the most effective and widely implemented

109

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 power because it toggles the signs up and their associated reasoning. So, to decrease power consumption clock gating turns off time while program maintaining its current condition.

the energy absorbed by flip-flops and the energy absorbed by clock submission network.

RTL clock gating has two critical limits: 1) the founder needs to give a gating potential and 2) signs up whose gating capabilities are not described are left ungated. One approach to purpose these issues is to take each one ungated sign-up, join it’s include and generate to a limited NOR gate, and utilize the generate of that front entrance as a gating potential of signup.Fig.1. Shows the clock gating in Load enable registers [1].

Fig.2. Example for implementing clock gating

Clock power is a main issue with power mainly because clock is fed to most of the routine blocks, and clock changes every pattern. Thus the complete clock power is a significant part of complete power dissipation in a electronic routine.

Clock-gating is a well-known strategy to decrease clock power.

By clock gating strategy, clock to a non-productive area is impaired, thus preventing power dissipation due to needless asking for and discharging of the rarely used routine. In clock gating clock is precisely ceased for a part of routine which is not performing any active calculations.

There are several considerations in implementing clock gating. The allow indication should stay constant when clock is high and can only switch when clock is in low phase. In order to guarantee after the gated-clock, it should be turned on in efforts and glitches on the private clock should be avoided.

3.2 Clock Gating Efficiency RTL is the best factor in the design process to improve energy. At this factor in the design flow, there is flexibility in the performance to make important improvements in energyefficiency. There is accurate information is available from features to reflect the total impact on energy, moment and area, as well. What’s needed is a good RTL measurement to evaluate how well a design is clock private and to help identify candidate clock-gating optimizations within the design.

A typical measurement used to measure the effectiveness of clock gating is the amount of signs up in the design that are clock private. While this gives designers an indication of the number of clock-gated signs up in the design, it has poor connection to real energy savings. That’s because powerful energy intake relies on the toggle amount. Clock-gating performance, on the other hand, views the toggle amount, making it a more telling signal of real powerful energy intake.

Fig.1. Load Enable Registers

Clock-gating performance is defined as the amount of the energy and effort a sign-up is private for a given stimulus or changing action. The typical clock-gating performance can be calculated as the regular of all clock-gating performance relies on representative changing action.

Combinational clock-gating is a straightforward replacement to the RTL rule. It decreases power by limiting clock on signs up when the outcome is not modified. In typical designs, combinational clock-gating can decrease powerful power by about 5-10%.

3.3 Execution Of Clock Gating

Sequential clock-gating changes the RTL microarchitecture without impacting style functionally. Power is enhanced by determining rarely used calculations, information reliant functions and don’t-care periods in the unique rule.

Sequential clock gating has a greater impact on energyefficiency then combinational clock gating because it turns off signs up for many years periods. In fact, successive clock gating has been shown to decrease power by up to 60% on style blocks. Sequential clock gating requires successive research based on action over several clock periods to decide which signs up can be private and under what enable conditions.

i)

Simple sequential circuits There are two types of clock gating styles available. They

are: a) b)

Latch free design Latch based design

a) Latch free design The latch-free clock gating uses an effective AND / OR gate (depending on the advantage on which flip-flops are triggered). Here [4] if allow indication goes non-active in between clock beats or if it many clocks then private clock outcome either can cancel ahead of clock or produce several clock impulses. This limitation makes the latch-free clock gating design unsuitable for our single-clock flip-flop centered design.

3.1 Clock Gating Implementation Clock gating works by determining groups of flip-flops discussing a typical allow indication. This allows indication is ANDed with a chance to produce the private clock, which is fed to clock ports of all of the flip-flops that had the typical allow indication. In the fig.2.E.g [2] the sel indication encodes whether they attach. This sel indication is ANDed with the clk indication to produce the private clock for the attach. This modification maintains the functional correctness of the routine, and therefore does not increase the pressure of verification. Clock gating has the potential of decreasing both

110

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303

Fig.3.Latch free design b) Latch based design The latch-based clock gating design [4] adds a levelsensitive attach to the design to hold the allow indication from the effective advantage of your energy and effort until the nonactive advantage of your energy and effort. Since the attach catches the state of the allow indication and holds it until the complete clock beats has been generated, the allow indication need only be constant around the rising advantage of the energy and effort just like as the traditional ungated design a sign-up produces the allow indication to ensure that the indication is totally without any glitches and spikes. The sign-up that produces the allow indication is activated on the non-active advantage of your energy and effort to be private. Using this technique, only one input of the gate that turns clock on and off changes at some factor. This stops any glitches or spikes on the outcome. Use an AND gate to gate clock that is effective on the rising edge. For time that is effective on the falling edge, use an OR gate to gate efforts and sign-up the allow command with a positive edge- triggered sign-up.

Fig.5.Application of clock gating in pipelined circuit 4

SIMULATION RESULTS

The execution of clock gating technique in simple circuits and pipelined design is performed to show its effectiveness.Fig.6&7. Shows the result of Latch free and Latch based design. Fig.8.Shows the result of pipelined design.

Summary result of power is established in Table.1

Fig.6 Simulation result of Latch free design

Fig.4. Latch based design ii) Pipelined circuit In a pipelined design, [2] the effect of clock gating can be increased. If the information to one direction stage stays the same, then all the later direction levels can also be frozen. The same clock gating reasoning being used for gating multiple directions levels. This is a multi-cycle optimization with several performance tradeoffs, and can save important energy, typically decreasing changing action by 15-25%.

Here Combinational logic is replaced by c17 testing circuit which is the circuit referred in [3]. C17 has two outputs in which one output is given as d flip-flop input another as next stage d flip-flop input ,whereas last d flip-flop alternate output is used as sel input to next stage this process repeats. By the way, as the rule clock given to all stage is same, this is AND to the sel input.

Fig.7 Simulation result of Latch based design

111

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 Table.1.Power Summary Circuit

Power (mW)

Latch based

86

Latch free

86

Pipeline design

95

Fig.8. Simulation result of pipelined design.

As latch is used as a bit storage element power variation is not much more.Fig.9, 10 &11 shows the power summary of simple and pipelined circuit.

Fig.11. Power summary of pipelined circuit.

5 CONCLUSION The application of clock gating technique in logic circuits such as simple and pipelined sequential circuit’s in order to, identify the effectiveness of clock gating technique. Also the prior need of this technique is to reduce power and hence power summary is evaluated with less time. As this technique reduces power by turn-off the inactive stage and hence every designers prefer clock gating technique to reduce overall dynamic power.

Fig.9. Power summary of Latch free circuit

REFERENCES [1] Inhak Han and Youngsoo Shin, ― Simplifying Clock Gating Logic by Matching Factored Forms,‖ IEEE transactions on very large scale integration (vlsi) systems, vol. 22, no. 6, June 2014.

[2] ―Basic Low Power Digital Design’’ user guide, Jan 2014.

[3] ―Fault Modeling and Simulation Tools for iDDT Testing‖, university of North Carolina, 2004.

[4] Priya singh and Ravi Goel,―Clock Gating: A Comprehensive Power Optimization Technique for Sequential Circuits‖International Journal Vol. 2, Issue 2, Ver. 2 (April June 2014) [5] Chinnery and K. Keutzer, ―Closing the Power Gap between ASIC & Custom‖, Norwell, MA, USA: Kluwer, 2007.

[6] S. Unger, ―Double-edge-triggered flip-flops,‖ IEEE Trans.

Comput., vol. 30, no. 6, pp. 447–451, Jun. 1981.

Fig.10. Power summary of Latch based circuit

112

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 [7] S. Kim, I. Han, S. Paik, and Y. Shin, ―Pulser gating: A clock gating of pulsed-latch circuits,‖ in Proc. Asia South Pacific Design Autom. Conf., Jan. 2011, pp. 190–195.

[8] Hurst, ―Automatic synthesis of clock gating logic with controlled netlist perturbation,‖ in Proc. Design Autom. Conf., Jun. 2008, pp. 654–657.

[9] Farrahi, C. Chen, A. Srivastava, G. Téllez, and M. Sarrafzadeh, ―Activity-driven clock design,‖ IEEE Trans.

Comput. Aided Design Integr. Circuits Syst., vol. 20, no. 6, pp. 705–714, Jun. 2001.

[10] L. Benini, G. De Micheli, E. Macii, M. Poncino, and R. Scarsi, ―Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers,‖ ACM Trans. Design Autom. Electron. Syst., vol. 4, no. 4, pp. 351–375, Oct. 1999.

[11] E.Theeuwen and E. Seelen, ―Power reduction through clock gating by symbolic manipulation,‖ in Proc. Symp. Logic Archit. Design, Dec. 1996, pp. 184–191.

113