Fixed-Outline 3-D IC Floor planning with TSV Co-Placement

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Fixed-Outline 3-D IC Floor Planning With TSV Co-Placement R. Priyadarsini1, C.H Kavya2 1,2Academic

consultant , Department of ECE,SPMVV, Tirupati, Andhrapradesh ---------------------------------------------------------------------***---------------------------------------------------------------------

Abstract - We describe, in this paper, a new digital input

output power configurable PAD for a wafer-scale-based rapid prototyping platform for electronic systems. This wafer scale platform includes a reconfigurable wafer-scale circuit that can interconnect any digital components manually deposited units active alignment-insensitive surface. The whole platform is powered using a massive grid of embedded voltage regulators.

Power is fed from the bottom side of the wafer using through silicon. The CPAD can be configured to provide CMOS standard voltages of 1.0, 1.5, 1.8, 2.0, 2.5, and 3.3 V using a single3.3 V power supply. The digital I/O includes transistors sharing and is embedded within the regulation circuit by combining it with a turbo mode that insures high-speed operation. Fast load regulation is achieved with a 5.5-ns response time to a current step load for a maximum current of 110 mA per CPAD. The proposed circuit architecture benefits from a hierarchical arborescence topology where one master stage drives 16 CPADs with a very small quiescent current of 366 nA. The CPAD circuit and the master stage occupy a small area of 0.00847 and0.00726 mm2, respectively, in CMOS 0.18-μm technology.

Key Words: CMOS technology, configurable voltage

reference, low-drop out regulator, prototyping platform, wafer-scale system, wafer IC

1. INTRODUCTION Today electronic systems integrate increasingly complex components with demanding constraints on size, power efficiency, and time-to-market. There have been previous efforts to overcome the design, prototyping, and debugging costs of high-end electronic systems, but none has succeeded in all the areas needed to revolutionize system design, prototyping, and debugging. Components, such as field

programmable interconnect chips (FPICs), are known to be capable of reconfiguring the interconnections of an electronic system [1].Nevertheless, a printed circuit board (PCB) must be fabricated to match the layout pattern of the © 2017, IRJET

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required components for each system. Furthermore, in the case of high-end electronic systems that require high-density routing, several FPICs must be used due to their limited capabilities [1].A novel platform made up of an active reconfigurable wafer-scale circuit, Wafer Board, has recently been introduced for rapid prototyping of electronic systems [2]. This platform interconnects any user integrated circuit manually deposited on its active alignment-insensitive surface, Wafer IC, by the system designer. This active area is densely populated with over a million small conducting pads, called nano pads, and covered with an anisotropic conductive film (z-axis film), formed with high density micro-metallic fibers, in order to insure a good electrical contact and to protect the Wafer IC surface. A square array of 32×32 Unit-Cells, each with a group of4×4 nano pads forms article image (Fig. 1). The article image is photo-repeated to create the wafer-scale circuit and with inter-reticle stitching for connections between reticle images.

Each nano pad can be in contact with any type of user integrated circuit ball and must, therefore, be configured as floating, a digital input/output (I/O), a power supply, or a ground. The configurable PAD (CPAD) is internal circuit block that, when configured as a power supply or I/O, provides a rang stable and regulated VDD to its connected load. To support a large of digital user integrated circuit , the CPAD can be configured to one of the nominal VDD standard levels: 1.0, 1.5, 1.8, 2.0, 2.5, or 3.3 V, with the reference voltage internally generated rather than externally generated as in a FPGA [3]. The CPAD also includes a contact detection mechanism based on a user integrated circuit ball covering more than one nano pad. The top side of the Wafer IC must be free of any other mechanical or electrical structures to ensure good electrical contact between user integrated circuit balls and the z-axis film wires. All external connections, such as power supplies and I/O signals are carried out by through silicon vias (TSV) to free the top side of the Wafer IC of any components or mechanical connectors. The connection between the desired pins of two or more user integrated circuit is accomplished via a fault-tolerant reconfigurable interconnection network, called Wafer Net. This multidimensional mesh structure links a number of CPADs together in each physical direction(N-S-E-W) at near intra-chip-density [1].The Wafer IC is a photo-repeated assembly of more than 1.2 million CPADs. Each CPAD has to integrate all possible configurations, meaning that an embedded regulator has to be placed in all of them, as well as all other functionalities.

The available space for one CPAD is approximately 0.009 mm2,which makes the silicon area the most important constraint for any integrated solution. To provide stable and

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configurable VDD to each user integrated circuit ball, voltage regulators are distributed over the entire Wafer IC, one per nano pad. It is known that dc-dc converters and switching regulators can provide high power efficiency of ∼95% [4]. Nonetheless, leakage current due to constant switching reduces the possibility of wafer-scale integration.

Moreover, such regulators often require off-chip capacitors and inductors, which are not possible because the Wafer IC top surface is reserved for user integrated circuit . Linear regulators are more appealing and easier to integrate onchip within a small area despite their lower theoretical maximum power efficiency, e.g., 75.8% for a 3.3 V–2.5 V dcdc conversion. A typical topology for a CMOS linear voltage regulator uses a common-source output stage. Low-dropout voltage can be achieved with this design without the need for gate-overdrive[4]. The PMOS transistor, acting as the pass device, allows it to be turned on with very large VGS and reduces the required silicon area for a maximum desired output current compared to an NMOS pass device. On the downside, this topology offers poor noise rejection and its bandwidth is limited by the low frequency amplifier feedback [4].A solution to improve the transient response of the linear regulator is to include a differentiator in the feedback .Although good results and performances can be obtained, large integrated capacitance of 2.5 pF and resistances are needed[5]. This results in a total silicon area of 0.29 mm2 for a similar CMOS technology, according to the authors in [5], which does not meet the area requirement.

Another approach to improve the bandwidth uses an impedance-attenuator buffer that presents good performances with a maximum delivered current of 200 mA, a quiescent current of 20 μA, and a transient response of approximately 100 ns [6]. However, the use of integrated capacitors and resistors requires ten times the available area, even when technology scaling is applied on the published results of [6].Another technique uses multiple small gain stages to enhance the transient response of the low drop out (LDO)without introducing low frequency poles [7]. However, this solution would require more than the available silicon area for a single CPAD while providing only 50 mA. Nested Miller compensation can also be used for frequency compensation by using current buffer stages [8].

In counterpart, this architecture requires several integrated passive components, such as capacitors and resistors. Other approaches were proposed in[9] and [10] with solution 10 times the available silicon area for the CPAD. Hazucha et al.

[4] introduced a master-slave topology to minimize the silicon area with fast load regulation

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using current buffer stages [8]. In counterpart, this architecture requires several integrated passive components, such as capacitors and resistors. Other approaches were proposed in[9] and [10] with solution 10 times the available silicon area for the CPAD. Hazucha et al.

[4] introduced a master-slave topology to minimize the silicon area with fast load regulation. Exploiting this approach within the Wafer IC would result in a ten-fold reduction of the silicon area and power consumption requirements, for a specific circuit, when referring to a Unit-Cell with 16 CPADs. Fig. 1 shows a hierarchical architecture where the master stage, one per Unit-Cell, shares control signals with a 4 × 4 nano pad array.

The architecture reported in [4] separates the regulation into a master-slave topology dissociating the slow variations from the fast ones (Fig. 2).A primary low bandwidth control loop tracks a reference voltage along an Op Amp to counteract any slow variation in the desired output. The second loop, with a much higher bandwidth, is accomplished by a current feedback within the fast load regulation (FLR) block. Despite very good performances ,the silicon area of this design reported in [4] is an issue,0.008 mm2 for a 90-nm CMOS technology (same available area for a CPAD in a 180nm technology), and moreover, the area of the integrated capacitor is more than ten times higher than the LDO one. To our knowledge, no circuit structure exits in the literature that meets our silicon area requirements. Regulators use a voltage reference that must be internally generated to establish the predefined output according to the nano pad load requirements. External generation of voltage reference, such as used for FPGA I/O banks, would not be a suitable solution because of the numerous different voltages required (1.0, 1.2, 1.5, 1.8, 2.0, 2.5, and 3.3 V). Moreover, external generation of needed power supplies would require more silicon area than available and extra routing from a TSV to every nearby nano pad as well as mechanically weakening the wafer itself. The configurability of the internal voltage reference could be achieved using a digital-to-analog converter paired with a band gap reference voltage (BGR) using a vertical PNP parasitic transistor [11], [12]. However, these circuits focus on ultralow temperature deviations of the voltage reference, and the nano pad only supplies power to digital user integrated circuit and can, therefore, tolerate an overall ∼10% voltage ISO 9001:2008 Certified Journal

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Variation at their power supply pin [4]. This large variation allows us to focus on more important issues with regards to wafer-scale integration, such as configurability, fast transient response quiescent current, and silicon area A distributed linear regulator can regulate a load by tracking a reference voltage. This reference must be as independent as possible of any variation related to the power supply, temperature, and fabrication process. Typical BGR uses an operational amplifier (Op Amp) that ensures equality of both differential inputs [13]. Another typical BGR uses a cascade current mirror with PNP transistors to produce a proportional to absolute temperature (PTAT) current.

Temperature independence is achieved by combining this PTAT current with a complementary to absolute temperature (CTAT) structure using a third transistor.

Others use self-bias symmetrically matched current mirror instead of an Op Amp to reduce the circuit needed silicon area [14].Despite the fact that these approaches are simple and very efficient with regards to performance, they use large resistances and parasitic diodes, making them irrelevant for wafer-scale integration. For instance, in [13], 1.2-μm CMOS technology was used to implement the design.

The required silicon area was 1 mm2, which, with the scaledown factor of (1.2μm/0.18 μm)2, is equivalent to 0.0225 mm2 or almost3 times bigger than the available silicon area for an entire CPAD (0.00847 mm2). Layout optimization would allow silicon to use efficiency but would still leave no free space for all other required circuits. Many aspects need to be considered when building an I/O, such as process, voltage, and temperature variations. These variations directly affect the driver output impedance and degrade I/O performance [15]. The I/O can be either controlled by a current that is more sensitive to noise or by a voltage that offers good noise immunity. A first topology is a simple programmable I/O driver that has the ability to calibrate the pull-up and pull-down current drives with a combination of PFET and NFET that can be programmed in the right proportion .A second more complete topology uses additional pull up and pull-down transistors and poly resistances that flatten output impedance response [15].

However, such topology does not meet the design requirements with regard to available silicon area, due to the complexity and number of integrated resistances and transistors. To attain configurability, a similar approach to that available in some FPGA where an I/O voltage banks strategy is used with their external power supplies and voltage references would not be suitable for the Wafer IC. Several topologies exist to generate a voltage reference, voltage regulator, and I/O pads, but they are not amenable for the Wafer due to their large silicon area and quiescent current requirements. Given that the objective is to integrate one embedded CPAD per nano pad, and that a Wafer IC includes1 245 184 nano pads, sharing maximum circuits within a Unit-Cell would considerably help to improve those concerns. We propose, in this paper, a configurable PAD suitable for wafer scale integration, which integrates a fast load regulator that is merged with a high speed digital I/O by © 2017, IRJET

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using transistors sharing and a turbo mode. Moreover, the CPAD achieved the best figure-of-merit for voltage regulation while offering a wide range of operation and has turn-off capabilities for low power consumption. The remainder of this paper includes, in Section II, an introduction of the Wafer IC structure, which determines the architecture for the distributed linear regulators, voltage reference ,I/O, contact detection, and the strategy to improve overall quiescent current. The proposed circuits and their characteristics are also depicted in Section II. A layered structure that can feed current from a small PCB (mmscale)to the active silicon areas (μm-scale) from the bottom of the wafer is also reported in this section. In Section III, a test chip fabricated in a 0.18-μm CMOS technology is presented, and demonstrates the benefits of the proposed CPAD topology.

Experimental results show that the proposed solutions for the CPAD are reliable, efficient, and fit Wafer IC requirements. These results are detailed and discussed, and performances of the proposed circuits are compared with other published works.

2. OVERVIEW OF THE WAFERIC AND DESCRIPTION OF THE PROPOSED POWER DISTRIBUTION SYSTEM The Wafer IC benefits of the wafer-scale circuit programmable capabilities to interconnect user integrated circuit randomly deposited on its surface, but that creates several design challenges to power these multiple user integrated circuit . This section briefly describes the Wafer IC structure and its related power and physical requirement as well as describing solution for power distribution and regulation specific to the prototyping platform.It shows an adequate solution that suits wafer-scale integration.

2.1 Proposed Wafer IC Topology and Design Requirements Fig. 1 shows a hierarchical view of the Wafer IC, which has been implemented in a mature and low-cost seven metal layer CMOS 0.18-μm technology. Its active circuit is composed of76 photo-repeated reticle image tiles within a 200-mm wafer (Fig. 1). Each reticle image includes a 32×32 array of 560×560 μm2 Unit-Cells. Each Unit-Cell can support two 250-μm diameter user integrated circuit balls with an 800-μm pitch. It is also important to have 4 × 4 nano pads per cell to ensure good electrical and mechanical contact with the user integrated circuit balls, deposited on the z-axis anisotropic conductive film and conductive nano pad [16].

The Unit-Cell circuitries include 4 × 4 CPAD, the control logic, the Wafer Net, and the analog circuits [1]. The CPAD is the largest element at 77 μm × 110 μm, consuming in aggregated almost half silicon area. Each CPAD can provide 110 mA to a user integrated circuit ball load. The specified sizes have ISO 9001:2008 Certified Journal

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been done accordingly to fit the requirements of the 4 Ă— 4 array of nano pads explained earlier, and it is also a tradeoff of silicon area with the other necessary digital circuitries essential to a Unit-Cell. A contact detection mechanism is also implemented to locate physical connections to a user integrated circuit pin by detecting shorts created between two or more adjacent nano pads by a user integrated circuit ball (Fig. 1). This is done by addressing pairs of neighboring CPADs with appropriate pull-up and pull-down signals and activating the proper detection circuits. The power supply arborescence structure combined with the size of the power rails makes all power supplies uneven across the wafer, due to parasitic resistances, process variations, the large number of supplied user integrated circuit , and the random placement of these user integrated circuit over the surface.

These physical and structural constraints make the ground and power grids very noisy. The external voltage regulators feeding voltage through several TSV could suffer severe voltage drops and noise at the user integrated circuit ball due to parasitic resistances of the TSV and the on -silicon power and ground grids. A linear voltage regulator closer to the load, within each nano pad with virtually no distance to the regulated load, is more amenable. Embedded distributed voltage regulators are proposed to alleviate against dc variations and all frequency noise within the power grids and substrate.

Blocks with a ground and a 12 V supply. Each Power Block performs a dc-dc conversion down to 1.8 and 3.3 V and provides powers to the Wafer IC through its bottom surface to keep its active surface exempt of any components. Each Power Block powers up to four reticule images throughout a massive grid of TSVs. An on-silicon metal grid distributes the necessary voltages through all Unit-Cells and nano pads.

Decoupling capacitors cannot be placed on the topside of The Wafer IC because the link between user integrated circuit balls is digital. More over, placing a decoupling capacitor on the same nano pads the user integrated circuit ball would not be possible. Integration of sufficient capacitance is also impossible due to silicon area constraints imposed by the Wafer IC. Consequently, the chosen architecture needs to deliver a regulated voltage without the benefit of adding capacitors. Moreover, it is necessary to distribute a stable voltage level to the powered CMOS user integrated circuit deposited on the prototyping platform, in relation to VDD fluctuations, process, and temperature variations. Typical linear regulators use an Op Amp to ensure that VOUT tracks V ref across all these variations.

However, process, temperature, and VDD variations are slow (<kHz) while load current spiking is very fast (MHz), Several linear regulator topologies exist and offer a wide range of dc load regulations, output impedances, quiescent currents, silicon areas, decoupling capacitances, and transient responses. The requirements listed in Table I are the fore most objectives regarding required output range, maximum current, and silicon area. We adapted the which makes this approach unappealing.

2.2. Power-Supply Arborescence Topology A ground and two other power supply rails, 1.8 and 3.3 V (typical power supply voltages for a 0.18-Îźm CMOS technology),are distributed uniformly over the 200-mm wafer. The Wafer Net logic core is supplied with 1.8 V, with a maximum current of 5 A split among a maximum of four reticule images. The CPAD and all other analog circuits are supplied with the3.3 V rail for the same number of reticle images but with5 times the power of the 1.8 V rail.

The Wafer IC power-supply circuit has an arborescence structure alongside a single power source as the root, and the embedded regulators in each CPAD as the leaves (Fig. 3).Powering up the complete wafer is accomplished by an ac/dc converter fed by a PCB that interconnects 21 Power Š 2017, IRJET

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The master-slave approach proposed in [4] in order to minimize silicon area by sharing and combining a maximum of circuits. In Fig. 2, the master stage (Unit-Cell) encompasses the low bandwidth loop and there is one FLR block per nano pad for the higher bandwidth loop.

The silicon area has been reduced by a factor of four, and a novel digital configurable output is integrated to the ISO 9001:2008 Certified Journal

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architecture proposed in [4] by reusing the pass-transistor and the fast-loop feedback.

This section estimates

2.3 Through-Silicon Via Density and dc IR Drop Analysis The dc performances of the proposed power supply arborescence and determines if it could supply sufficient power to a user integrated circuit . Every stage introduces a dc voltage drop that can be modeled by discrete serial resistances. An overall dc drop of 150 mV from the root to the CPAD power supply is acceptable, leaving enough headroom for all circuits to work properly. The main backside PCB is considered as perfect power and ground plane due to the thickness of the metal lines. The TSV resistance was measured in [16]; with a value of ∼11 m_ per TSV. To determine the adequate TSV density and the equivalent resistance of the on-silicon Metal grid, modeling and simulation were performed using COMSOL Multi physics [17]. For the purpose of these Simulations , four power pins were each in contact with four nano pads. Each pin reduces the maximum available current, by a total of 400 mA per pin, which represents a powerful microprocessor activity. The results are summarized in Table II. The thickness of the CMOS technology metal layer is less than 1 μm, therefore it cannot carry a lot of current. To enhance the capabilities of the power grids, the density of TSVs/mm2 must be increased, but the TSV density is limited by the mechanical strength of a 200-mm wafer, the more holes it contains, the more fragile it is. The metal density is defined as the ratio of metal width to metal pitch. Fig. 4 is a representation of our model. This metal density has an upper bound because the routability of the Wafer IC logic must be maintained using six metal layers [1]. A TSV density of0.25 mm2 with a metal wire density of 6/30 (width/pitch) was selected for the actual implementation. The maximum dc overall voltage drop calculated with this setup, using COMSOL Metaphysics, is 90 mV, which is close to half the maximum acceptable dc voltage drop described earlier in this section.

2.4. Master Stage Topology Fig. 5 depicts the transistor level view of the proposed Master stage topology. All transistors are high voltage devices, except transistor M50, which is a native (low threshold)component to help improving the output range. It consists of a configurable voltage reference array (CVRA) that feed san Op Amp with a command (VREF) implemented in order to have a good power-supply rejection ratio in addition to good temperature independence. The OpAmp tracks VREF to ensurestability of VOUT0. The desired output voltage is obtained by supplying the FLR with the voltage VSET generated by an N Stage Buffer. The objective of this buffer is to isolate the operational trans conductance amplifier (OTA) from any noise induced by the load of the connected slave stages. Considering that the prototyping platform needs to powers IC with standard voltage level, as well as being compatible with the same digital levels, there is no need for a configurable voltage reference with intermediate levels. Voltages below the targeted standard CMOS are not desired as an increase of temperature will slightly increase the regulated voltage, helping to compensate for the dc IR drops of the power-supply chain.

The proposed architecture uses a beta multiplier architecture to provide a current, IREF, that ideally only depends on transistor parameters. This current is then duplicated into a transistor-based array of voltage divider sto provide the required reference standard voltages of 1.0,1.5, 1.8, 2.0, and 2.5 V [18], [19]. Given that the master stage will be instantiated 77 824 times, the very low quiescent current and the small silicon area of 0.0014 mm2 in a CMOS0.18-μm technology, offer an attractive solution to achieve configurability since no vertical PNP parasitic transistors or other large biasing current is needed.

This approach uses two different voltage dividers in order to achieve the targeted references. The first one can be expressed by (1) assuming M14 is saturated, M15 is in triode region, and their drain currents are equal to IREF generated

by M13

The second voltage divider technique cascades two saturated transistors. Assuming drain current ID16 equals ID17, the reference voltage can be expressed as follows:

where IREF is given by (3) and KPn is the trans conductance parameter and M the transistor size ratio of M11 and M10.Equation (4) shows the temperature dependence (dT) of IREF. As temperature increases the mobility decreases leading to a reduction of the trans conductance parameter butan increase of R1. Those two effects tend to cancel each © 2017, IRJET

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other improving the temperature independency but still slightly CTAT according to post-layout simulations [19]

Table -1: Sample Table

The small signal analysis of the current mirror in the first stage of the proposed master stage architecture (Fig. 5) leads to the expression of the output impedance seen looking into the drain of M6, which is mirrored in M13 as

Equation (7) gives the trans conductance gm10 from the basic of a beta-multiplier where Vgs10 = Vgs11+ ID11R1, given by (6), and shows the temperature dependence of the output current from the mirror current stage. From Fig. 5

Replacing gm10 by its expression in (5), the output impedance becomes

The output impedance ROUT of the current mirror depends on the value of the resistance R1.An Op Amp structure was selected with power consumption and silicon area requirements in mind. The open loop gain and bandwidth are not critical since temperature and process variations are slow, a gain around 40 dB is sufficient [4].

The output, VAMP, is connected to NB and generates an Output command, VSET that swings from 0.5 to 2.5 V. VSET is connected to each FLR slave stage in each nano pad and Duplicated FLR is integrated into the master stage.

Considering that all FLR stages are identical, the output voltage at the nano pad is equal to VOUT0.

To ensure low-power consumption of all master stages Implemented on the wafer, kill switches were added to all Described modules, controlled by an ON_MASTER signal.

The CVRA is put offline by shorting all gates of PMOS Transistors connected to power-supply, to 3.3 V. The same Approach is used on NB and FLR modules by disconnecting Appropriate transistors. The disconnection of the Op Amp is done by disrupting the biasing current of the differential pair with M12, the gates of M4, M5, and M13 are then shorted to3.3 V ensuring the complete halt of the Op Amp. Failure to do this would result in the summation of 77 824 times a biasing current of several hundred microamperes. E. Slave Stage â&#x20AC;&#x201D; the CPAD The proposed slave stage is shown in Fig. Š 2017, IRJET

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6. It combine s several distinctive circuits to fulfill the required features in the CPAD, all driving a single nano pad opening when acting as an output: configurable regulator, configurable digital output, variable digital input, contact detection, and ground. All transistors are high voltage devices, only M55 is a native device to help improving the output range.

The configurable FLR is brought from transistors M51 to M55, where the current is pushed by M53. M52 and M53 act as a super source follower while M54 as a common gate amplifier. The command VSET defines the desired non inverting output voltage with an additional threshold. When the nano pad load sinks no current, M53 barely turns on to accommodate the biasing current provided by M55. As the current demand increases, VOUT drops and M54 starts to turn off redirecting the fixed biasing current through M52, which pulls down the gate of M53 to readjust the current demand. When not in operation, the entire regulation can be turned off, reducing the quiescent current to virtually nothing. This is accomplished through the signal OE that shorts the gates of M51 and M54 to the appropriate voltage, placing the output in high impedance and interrupting all other current flows. The standard CMOS voltage level requirements for regulation and digital output are the same, linking both functions.

Moreover, the restricted silicon area suggests the possibility of transistor sharing. Using the configurable voltage regulator to define the input or output voltage levels when configured as a digital I/O would result in a significant surface gain. However, the limited capabilities of the regulator, with regard to rising and falling times, are limited due to the size of transistorM53. The suggested architecture to accelerate transition time is shown in Fig. 6, where the digital I/O is embedded into the regulator. A differential pair is added to boost the response time of the power transistor gate. Transistor M68 was designed to pull down VTURBO to the ground, opening M53 to the fullest to rapidly boost the output. Once VOUT reaches VSET, which is always smaller by a threshold voltage VTH, the differential pair ceases to operate and regulation takes over for the last few milli volts.

A custom NAND gate, made with transistorsM61–M66, ensures that this circuit operates with appropriate timing and is disconnected with the ON_IO signal when the I/O function is not needed. Digital input is performed by a single level shifter(M74–M80) that takes any voltages from 1.0 to 3.3 V, converts it to a clean 1.8 V and propagates it into the Wafer IC digital interconnection network. Due to lack of silicon area, the digital input was calibrated to offer a symmetric duty-cycle at 1.8 V.A more complex solution larger silicon area consumption to ensure symmetrical signal at any voltage would not be suited for the Wafer IC requirements.

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2.5. Layout of the Proposed Test chip The fabrication of a complete 200-mm Wafer is costly, not only in money but also in development time. Basic principles and feasibility of the Wafer Net, configurability via a JTA Glink, and all CPAD associated features were tested with a low -cost and quick turnaround solution. A shuttle run with a test chip several times smaller than the actual full-scale prototyping platform was realized. Fig. 7 is a micro photograph of the proposed layout of the test chip consisting of1024 nano pads and 64 master stages in an 8×8 square Unit-Cell matrix.

3. MEASUREMENT RESULTS 3.1. Embedded Regulators dc Characteristics The FLR was designed to achieve a maximum current of over 110 mA per CPAD, validated with destructive measurements .Fig. 8 shows the V/I curve over different dc loads. The layout of the test chip limits the dc characterization to a maximum current of ∼20 mA, because it could not benefit from the power supplied by TSVs as available in a real Wafer IC. As a result, the last metallization layer is

shared with the nano pads, the output pads, and the power grids of the chip itself. It is important to note that the produced voltages, under a no-load condition, always seem to be tens of millivolts higher than the expected value. The fact that the nominal voltage was chosen to be at a50-mA current load, half of the maximum current load of the CPAD, explains this deviation. The OE signal stops any current source when activated, leaving a very low quiescent current of5.85 μA for an entire Unit-Cell or the equivalent of 366 nA per CPAD. 3.2. Embedded Regulator Transient Response to a

Load Step The accurate validation of the regulator requires a transient load with a rising edge of few nanoseconds, which was determined through calibration measurements. Fig. 9 shows the transient response using an external 1-MHz load clock with a 50% duty cycle. Rising and falling times were <8 ns ISO 9001:2008 Certified Journal

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with20-mA amplitude due to the test chip limitations.

According to Fig. 9, the dynamic output impedance is close to 1 _, with drops of 1% of the configured voltage. Notice that a user integrated circuit ball should be in contact with several nano pads concurrently,ideally four or more reducing the output impedanceaccordingly.

3.3. Power-Supply Rejection

(M81–M84) alongside a custom XOR gate (M85–M92) that would generate an appropriate signal when the inputs of this gate are VOUT and the control signal NA_WT_TPT_0.

If two nano pads are shorted by a user integrated circuit ball, applying the pull up to the first and the pull-down to the second would resulting an overall ground, which is not the expected value for the first nano pad. The detection of this contact would result in a digital “0” signaling a short.

3.5 Performance Comparisons

The fabricated test chip was tested with a 400-mVpp sinusoidal power supply added to a dc offset of 3.3 V at 1 MHz and1 kHz, without any decoupling capacitance at VDD. Figs. 10 and 11 show that, even under stressful conditions, the output voltages remain stable with about 20 dB of power-supply rejection for those two frequencies.

3.4 Embedded Digital I/O Characteristics Fig. 12 shows VOUT when configured as a digital output.

These results were obtained by cascading two CPADs, one Configured as an input and the second one as an output.

The proposed configurable CPAD was implemented in a 180-nm CMOS technology. For a simulated ∼110-mA post layout maximum current rating, the total area for one CPAD is 0.00847 mm2, where half the area is occupied by the output stages. When scaling previous works done in [4] to a180-nm technology, the used silicon area becomes 0.036 mm2.Our circuit represents an overall improvement of the silicon area by a factor of more than four times when compared to this original version. Moreover, the proposed CPAD integrates more functionality, such as the configurable digital I/O. The master stage requires almost the same area, 0.00726 mm2. This design does not require any on-chip capacitance; it is meant to Work only with parasitic capacitance conveyed by a user integrated circuit ball And its power grid (∼1 nH, 5 nF). The response time, TR, is Calculated from the required capacitance CLOAD for a specific

For the purpose of comparison with other regulators designed with specific application or design goals, such as Quiescent current IQ, decoupling, and maximum rating, IMAX, we used a figure-of-merit (FOM) detailed in (10). The smaller

The results presented were probed in a test bench with a high parasitic capacitance (∼nano Farads), which resulted in the impossibility to gather high-speed results such as those suggested in post-layout simulation (∼300 MHz). Despite the high-speed incapability of the test configuration, we were able to demonstrate the configurability of the digital interface. The remaining function of the CPAD, such as the ground, is Carried out by a large NMOS transistor (M56). This transistor is turned on by controlling circuitry of M57–M60, when all other major functions associated with power transistorM53are not in operation. The CPAD also includes contact detection mechanism that allows the user interface software, configuring the Wafer IC, to pinpoint all nano pads connected together when a user integrated circuit ball shorts a certain number of nano pads. This is achieved with a system of weak pull-up and stronger pull down © 2017, IRJET

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Impact Factor value: 5.181

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is the FOM, the better is the regulator. According to Table III, this paper achieves smaller FOM than all others designs

4. CONCLUSION A promising platform to rapidly prototype electronic systems was developed in our lab. A smart configurable wafer scale active circuit allows system designers to manually deposit integrated circuits on its surface and to power and interconnect them all together. We focused, in this paper, on the power-supply voltage distribution of this structure, which is fed through a dense grid of through silicon combined with an arborescence power-supply topology allowing minimal dc voltage drops and the embedded digital output that shares the LDO transistors. We demonstrated a CPAD in 180-nmCMOS technology with configurable standard voltage for voltage regulation, as well ISO 9001:2008 Certified Journal

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as for digital input and output. We achieved a fast response time of 5.5 ns and the best figure of-merit, which takes into account decoupling capacitance, maximum current, quiescent current, response time, and output deviation. The proposed pads fulfill other applications, such as ground and contact detection between similar pads. The silicon area of the whole CPAD and the master stage with no integrated capacitor are 0.00847 and 0.00726 mm2, respectively.

The 366-nA quiescent current makes this CPAD suitable for the Wafer IC.

REFERENCES [1] E. Lepers, O. Valorge, Y. Basile -Bellavance, N. LaflammeMayer,Y. Blaquière, and Y. Savaria, “An interconnection network for a novelreconfigurable circuit board,” in Proc.

2nd Microsyst. Nano Res. Conf., Oct. 2009, pp. 53–56.

[2] R. Norman, O. Valorge, Y. Blaquière, E. Lepercq, Y. BasileBellavance,Y. El-Alaoui, R. Prytula, and Y. Savaria, “An active reconfigurablewafer-scale circuit board,” in Proc. Joint IEEE NEWCAS TAISA Conf.,Jun. 2008, pp. 351–354.

[3] Virtex-6 FPGA Data Sheet: DC and Switching Characteristics, XilinxCorporation, San Jose, CA, Sep. 2010.

[4] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S. Borkar, “Area-efficient linear regulator with ultrafast load regulation,”IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933– 940, Apr. 2005.

[5] R. J. Milliken, J. Silvia-Marinez, and E. Sanchez-Sinencion, “Full onchipCMOS low-dropout voltage regulator,” IEEE Trans. Circuits Syst.I, Reg. Papers, vol. 54, no. 9, pp. 1879– 1890, Sep. 2007.

[6] M. Al-Shyoukh, H. Lee, and R. Perez, “A transientenhanced lowquiescentcurrent low-dropout regulator with buffer impedance attenuation,” [7] M. Ho, K. N. Leung, and K.-L. Mak, “A low-power fasttransient 90-nmlow-dropout regulator with multiple smallgain stages,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp.

2466–2475, Nov. 2010.

[8] A. Gari mella, M. W. Rashid, and P. M. Furth, “Reverse nested miller compensation using current buffers in a threestage LDO,” IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 75, no.

4, pp. 250–254, Apr. 2010.

[9] K. N. Leung and Y. S. Ng, “A CMOS low-dropoutregulator with amomentarily current-boosting voltage buffer,” IEEE Trans. Circuits Syst.I, Reg. Papers, vol. 57, no. 9, pp. 2312– 2319, Sep. 2010.

[10] O. Trescases, A. Prodié, and W. T. Ng, “Digitally controlled currentmode DC–DC converter IC,” IEEE Trans.

Circuits Syst. I, Reg. Papers,vol. 58, no. 1, pp. 219–231, Jan. 2011.

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