76361e by KLA Corporation

The analysis of EUV mask defects using a wafer defect inspection system Kyoung-Yong Cho, Joo-On Park, Changmin Park, Young-Mi Lee, In-Yong Kang, Jeong-Ho Yeo, Seong-Woon Choi, Chan-Hoon Park, Samsung Electronics Co., Ltd. (Korea, Republic of); Steven R. Lange, SungChan Cho, Robert M. Danen, Gregory L. Kirk, Yeon-Ho Pae, KLA-Tencor Corp., 1 Technology Dr. Milpitas, CA, USA 95035 ABSTRACT EUVL is the strongest candidate for a sub-20nm lithography solution after immersion double-patterning. There are still critical challenges for EUVL to address to become a mature technology like today’s litho workhorse, ArF immersion. Source power and stability, resist resolution and LWR (Line Width Roughness), mask defect control and infrastructure are listed as top issues. Source power has shown reasonably good progress during the last two years. Resist resolution was proven to resolve 32nm HP (Half Pitch) lines and spaces with good process windows even though there are still concerns with LWR. However, the defectivity level of blank masks is still three orders of magnitude higher than the requirement as of today. In this paper, mask defect control using wafer inspection is studied as an alternative solution to mask inspection for detection of phase defects on the mask. A previous study suggested that EUVL requires better defect inspection sensitivity than optical lithography because EUVL will print smaller defects. Improving the defect detection capability involves not only inspection system but also wafer preparation. A few parameters on the wafer, including LWR and wafer stack material and thickness are investigated, with a goal of enhancing the defect capture rate for after development inspection (ADI) and after cleaning inspection (ACI). In addition to defect sensitivity an overall defect control methodology will be suggested, involving mask, mask inspection, wafer print and wafer inspection. Keywords: Extreme ultraviolet lithography, mask defect printability, absorber defect, ADT (alpha-demo-tool)

1. INTRODUCTION In order to make EUV lithography successful in the industry, the detection and control of mask defects are one of the issues which need to be solved. As devices scale down, critical defect sizes that can affect the printed pattern become smaller and the defect size that an inspection tool can detect needs to gets smaller too. Mask phase and pattern defects that can create a 10% CD change to the printed pattern are considered necessary to detect. We investigate two issues: The printability of mask defect shapes and sizes transferred to a wafer and the inspection sensitivity of mask and wafer inspection tools. To this end, we made masks with programmed defects and used either the EUV ADT (Alpha Demo Tool) scanner at IMEC or at Sematech facilities to expose them. We further studied wafer stack changes to maximize defect sensitivity of wafer inspection tools on pattern transfer wafers and tested photoresist LWR. KLA-Tencor has demonstrated detection of phase defects on mask blanks1. To complement this work, we did experiments to detect phase defects utilizing wafer inspection of ADI and ACI wafers. The remainder of this paper is organized as follows. Section 2 describes the programmed-defect masks and structure of print check wafers investigated here. Section 3 reports wafer inspection measurements of print check wafers, mask defect printability analysis and a method to find mask phase defects using wafer inspection. Section 4 summarizes results and presents conclusions.

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2. EXPERIMENTS Mask We fabricated two different PDM (Programmed Defect Masks) to check defect printability, detectability of absorber defects and to analyze the number of phase defects. PDM 1 and 2 were full-field size and analyzed by the methods mentioned earlier. The layouts of PDM 1 and 2 are shown in Fig. 1. The field size of the two masks was 25.5mm*23mm at the wafer level and each mask had 6 sub-blocks each being 8mm by 10mm in size. We printed a 50 nm HP (Half Pitch) line-and-space pattern and inserted programmed defects at the specific sites indicated. Programmed defects were of four types: extrusion, intrusion, pin hole and pin dot. Each type was printed in an array of rows and columns with defect size decreasing down the column and the same defect across the row. We added a â&#x20AC;&#x153;markerâ&#x20AC;? to each side of the row to facilitate finding the defects easily. The differences between PDM 1 and 2 were the sampling of defect sizes and the number of defects between the markers. PDM 2 contained five defects between markers with sizes decreasing by 10nm down a column. PDM1 contained three defects between markers with sizes decreasing by 20nm down a column.

(a)

(b)

Figure 1 (a) PDM 1 & 2 layout

(b) Defect matrix, PDM1 (upper ), PDM2 (lower)

We used the KLA 5xx series as the mask inspection tool. Note that the 5xx is not the current-generation, 193nm reticle inspection system; it uses 257nm illumination and is specified for 45nm node and beyond. We used a Leica LWM9000 9380 for defect review. Print Check Wafers Traditional print check wafers have used a simple stack of photoresist over the bare silicon substrate. Photoresist is a dielectric with a relatively low index of refraction that scatters little light, causing the wafer inspection to be difficult due to too little signal as the defect sizes have gotten smaller over time. Recognizing that we desire to dramatically increase the inspection sensitivity for future EUV design rules, we elected to investigate transferring the pattern into an optimized wafer stack that would produce more signal. A SiN stack was an easy choice as it has a relatively high index of

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refraction (produces higher scattered light signals) and its thickness could be optimized to produce the best inspection signal. In our investigation, we produced two types of film stacks: oxide and silicon nitride (SiN). We tested two different silicon nitride thicknesses for defect sensitivity. Oxide 2000A Pattern UL Amorphous carbon

ADI

SiN 850A

SiN 1700A

Pattern UL

Pattern

Amorphous carbon

SiO2

SiN

SiN Si

ACI

SiO2 Si

SiN

Si Si

Table 1. Wafer stack data for ACI and ADI samples Defect simulations were conducted by KLA-Tencor using a RCWA solver for Maxwell’s equations and predicted that the nominal 850Å SiN thickness should be increased to 1800Å to achieve the best signal for this material and the inspection tool parameters. We chose a 1700Å thick layer as the process was already available. We used an established under-layer structure with amorphous carbon optimized for etch process and pattern integrity. It was difficult to optimize the etch process with such a limited number of wafers, so there were cases where only the ADI data were available (no ACI data). See Table 1. for stack data on the wafers we fabricated. We made best efforts to minimize the skew of ACI CD to ADI CD to maintain similar defect sizes at ACI step compared with the original ADI. Additionally, two types of photoresist were tested to see their effects on the wafer noise. One case had a high LER (Line Edge Roughness) of 7 nm at ADI with a 120nm thick photoresist. The other case had a low LER: 4.5nm at ADI with an 80nm thick photoresist. The wafer inspection tool utilized was the KLA-Tencor 2830 and SEM review was done with the Hitachi CD SEM 9380.

3. RESULTS & DISCUSSION PDM1 - Wafer Stack Optimization To determine how much, if any, the print-check wafer stacks improved defect sensitivity over the standard short-loop wafer ADI, one can examine the problem in several manners. First, one could compare the inspection tool’s signal and signal-to-noise ratio on reticle defects that were known to print, according to SEM review, as a function of the wafer stacks. Another method is to determine the smallest wafer defect that can be detected with each stack and then relate that back to reticle defects which could create that size wafer defect. We completed both of these methods using a KLATencor 2830 wafer defect inspection system on a set of 8 wafers with 4 ADI and 4 ACI wafers each printed with the same PDM1 reticle. We compared mask inspection and ADI/ACI results with two variables, two SiN thicknesses and an Oxide film stack and low and high LWR photoresist. From this matrix of wafers, we could investigate the effect of the wafer stack on signal and SNR, and the effect of low and high LWR on signal and SNR. Finally, we could investigate how defect size changed as the pattern was transferred from the ADI to the various ACI wafers and from that data

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determine the ultimate sensitivity of the wafer inspection tool, i.e., the minimum size wafer defect that could be detected as a function of the wafer LWR noise. The goal would be to see how far the inspection sensitivity could be extended when future EUV processes drive LWR noise lower and whether this would meet EUV inspection requirements. ACI SiN 1700 1800 Low-LWR

Mask

ACI SiN850 Low-LWR

ACI SiN850 High-LWR

ACI Oxide H-LWR

-103 48.9 -103.5

-104

49.1

49.2

49.3

49.4

49.5

49.6

49.7

Defect size decrease

-104.5

-105

Pin hole

Intrusion

Pin hole

Pin dot

Extrusion

Pin dot

-105.5

-106

-106.5

-107

ADI SiN 1700 1800 Low-LWR

ADI SiN850 Low-LWR

ADI SiN850 High-LWR

ADI Oxide H-LWR

Figure 2. Mask (KLA-Tencor 5XX) and wafer (KLA-Tencor 2830) inspection results, for stack type, thickness, and photoresist LWR.

Wafer and mask inspection results were first compared using defects captured during wafer inspection scans as shown in Figure 2. As illustrated above in Figure 1(b), programmed defect size decreases down each column. Thus, more defects captured in each column indicate smaller defects are captured. In summary, mask inspection was the best for absorber defect detection. ACI was better than ADI for wafer inspection and SiN1700 > SiN 850 > oxide in capture rate. Low LWR was better for defection inspection than high LWR. In order to extrapolate to smaller design rules, we examined the signals and SNR for the various print check ADI and ACI wafers to examine how the experimental variables affected the results. We first compared simulated signals with measured signals to see if they correlated, as shown in Figure 3. Both show a considerable increase in signal from the ADI stack to the SiN ACI stack. Signal & SNR ratios to baseline ADI

Average Simulated & Measured Signal Normalized to PR 65nm

40 35

Simluated Signals

Measured Signals

40 35 30

A SiN 1700nm

0 ADI PR 650A 65nm

ACI SiN 850A 850nm

Figure 3. Comparison of simulated signals to measured signals.

A SiN 850nm SNR

ACI SiN 1700A 1700nm

Signal

Figure 4. Comparison of optimized SiN stacks, signal and SNR, expressed as a ratio to the ADI baseline (PR/2000A Oxide)

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But, of more interest is whether SNR increases as the wafer stack conditions change, that is, if noise goes up as fast as signal, then no benefit would be realized from changing the stack conditions. To examine this, we measured the ratios of signals and SNRs of the central three columns of defects in each type and compared the SNR with various wafers across nine of the many possible wafer inspection tool recipes. Inspection tools can be optimized to focus on a single defect type or minimize a type of noise, which is an unrealistic situation in a fab, so here we averaged the results of each inspection recipe across the set of defect types without regard to which recipe might be optimized for the type of defect. In comparing the LWR for the ACI wafers, we found that the SNR was 1.78 times higher for the low LWR wafer indicating that low LWR does help the inspection sensitivity. For the ADI wafers, the LWR had little effect on the SNR. Comparing the signals and SNR for the two SiN stacks against the baseline ADI we see considerable improvement in the both the median signal and the SNR, as shown in Figure 4. This indicates that both signal and SNR are improved with the ACI stacks compared with the ADI wafer. This implies that the pattern transfer technique can be used to improve wafer inspection sensitivity to printed reticle defects. One can now ask how small of a defect can be captured on the print check wafers with the optimized ACI stack? We examined this by looking at the measured signal compared with the defect size and then extrapolating the size down to the tool noise. We characterized defect size by its area as measured with a high resolution SEM. Since the line-space ratio changes depending upon the process for each wafer, this makes the most sense, and the area can be used to extrapolate to other design rules. Figure 5 shows a plot of the signals vs. size for the 1700Å SiN ACI wafer for the different defect types. The bridge and open type defects printed only at large sizes and have signals that are well above the wafer and tool noise, so the extrapolation to find the minimum size detectable has significant uncertainty. The wafer inspection tool noise is much less than the current wafer noise from the LWR, but as the EUV litho process improves, we expect the LWR noise to improve. The results show that the signal vs. size is not well controlled and shows considerable variability. Some of this can be attributed to the inspector’s sampling of the defect. If a sampling pixel lands on the exact top of the defect, the signal will be high, but if the corner of the pixel lands on the top of the defect the signal will be split among four pixels and will be lower; thus the measured signal tends to underestimate the best signal if a smaller pixel is used. Another cause of the variation is errors associated with measuring the defect size from the SEM image, which is mostly a visual exercise. 2 The fit curves seem to converge at a defect area of 350nm with a signal of 2 which should have 100% capture rate if wafer noise were not an issue. This implies that the inspector should be able to detect a 6-8nm wide bridge or open and an 11nm protrusion or intrusion. We plan to validate these predictions on smaller design rule examples in the future and extrapolate the sensitivity to the 22 and 16nm nodes with our models for our future inspection tools.

Signal Vs. Size –- 1700nm SiN Etched ACI Wafer vs. Size 170nm SiN wafer

1000

Signal

100

Low LWR Wafer Noise 1 0

1000

2000

3000

Open Intrusion Protrusion Brige Bridge Type Fit Open Type Fit 4000

5000

Size (nm2)

Figure 5. Signal vs. size for the 170nm SiN ACI wafer showing defect types. We compared the mask defect size and type to the size and shape of defects printed on the print-check wafers with some interesting results. The wafer inspection system showed similar detection sensitivity for the both pin dot and the pin hole, but only the first three sizes were detected on the wafer. SEM analysis of the print-check wafers revealed that the

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smaller pin dot and pin hole defects were not printed on the wafers. However, the wafer inspections detected smaller intrusions and extrusion type defects; SEM review confirmed that these defect types transferred from the mask to the wafer. To understand this effect, we conducted a simulation of the EUV mask-to-wafer print, comparing the pattern size of an extrusion defect and a pin dot defect for the 50nm HP vertical line and space pattern. As we can see in Fig. 6, the printed pattern size for the pin dots is the same for the larger mask sizes and then drops dramatically with smaller mask defect sizes. The print size for the extrusion defect type shows a monotonic decrease in print size with the mask size. This simulation confirmed the wafer inspection and SEM review results for the print-check wafers.

110

Ext r usi on Pi ndot

Def ect si ze vs pat t er n si ze

Pat t er n si ze( nm)

100 90 80 70 60 50 40

160

140

120

100 80 Def ect si ze( nm)

Figure 6. Simulation of EUV mask to wafer print. X-axis denotes size of defect on mask; y-axis shows simulated defect size expected to print on wafer. ΔCD/CDref @ ADI

100%

>50%

<50%

ΔCD/CDref @ ACI

140

120

100

140

120

100

Oxide+H LWR

0.48

0.28

0.16

0.13

0.14

Oxide+H LWR

0.27

0.19

0.11

0.2

0.08

SiN850+H LWR

0.44

0.35

0.18

0.11

0.04

0.08

SiN850+H LWR

0.20

0.08

0.07

0.02

SiN850+L LWR

0.37

0.31

0.16

0.12

0.11

0.05

SiN850+L LWR

0.37

0.14

0.09

0.13

0.03

SiN1700+L LWR

0.58

0.28

0.17

0.11

0.10

0.09

SiN1700+L LWR

0.33

0.14

0.09

0.12

0.04

140

120

100

140

120

100

Oxide+H LWR

0.52

0.21

0.20

0.08

Oxide+H LWR

0.35

0.16

0.08

0.05

SiN850+H LWR

0.30

0.16

0.07

SiN850+H LWR

0.26

0.21

0.07

0.01

0.03

SiN850+L LWR

0.36

0.18

0.12

0.05

SiN850+L LWR

0.45

0.33

0.21

0.09

0.04

SiN1700+L LWR

0.33

0.17

0.14

0.04

SiN1700+L LWR

0.44

0.27

0.08

0.06

0.03

Hole

140

120

100

Hole

140

120

100

Oxide+H LWR

0.18

0.06

0.10

0.11

Oxide+H LWR

0.12

0.09

0.05

0.04

SiN850+H LWR

0.16

0.02

0.03

SiN850+H LWR

0.12

0.02

0.04

SiN850+L LWR

0.13

0.04

0.03

SiN850+L LWR

0.15

0.05

0.03

SiN1700+L LWR

0.13

0.03

0.04

SiN1700+L LWR

0.21

0.03

0.04

0.07

Dot(S)

140

120

100

Dot(S)

140

120

100

Oxide+H LWR

0.07

0.05

Oxide+H LWR

0.13

0.01

0.03

SiN850+H LWR

0.10

0.05

0.06

0.03

SiN850+H LWR

0.27

0.05

0.03

0.05

0.03

SiN850+L LWR

0.13

0.05

0.03

0.04

SiN850+L LWR

0.12

0.04

0.01

SiN1700+L LWR

0.09

0.03

0.05

SiN1700+L LWR

0.45

0.05

0.06

0.03

Table 2. Printed defect size ∆CD/CD and 2830 detection rate. Empty entries (-) correspond to fully bridged or cut lines. Color coding gives 2830 detection capture rate: white indicates 100% capture rate, bright gray >50%, dark grey < 50%, black 0%. Additionally, subtle differences in wafer exposure and wafer processing conditions can make differences in line pattern and defect size. Because we developed a new process using only a small number of wafers, a perfect etch condition will

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not result. Substrate type and thickness can make a skew, which can change the line-to-space ratio. To better qualify inspection results and understand the transfer of mask defects to print-check wafers, we SEM reviewed all programmed defect locations for all print-check wafers. Table 2 reports the SEM measurements at each programmed defect site as ∆CD/CD, where ∆CD is the change in width of the printed line at the defect site and CD is the line width. As noted above, Line Edge Roughness (LER) varied between 4.5 and 7 nm depending on resist thickness. This indicates that for CD= 50 nm, only defects with ∆CD/CD > 0.1 would be distinguishable from LER. For example, for the pin dot defects simulated above that do not print well (mask size of 100nm and below), ∆CD/CD values are near 0.1 or below. Table 2 additionally shows wafer inspection capture rate as a color code (white corresponds to 100% detection of programmed defect and black corresponds to 0% detection). In general the entries with 0% capture rate correspond to printed defects with sizes similar in magnitude to LER. Table 2 confirms no difference in defect sensitivity for the pin dot and pin hole defect types due to their printing characteristics described above. The best inspection result for intrusion and extrusion types was with the low LWR ACI wafer with 1700Å SiN. Detectability and printability of PDM defect are compared in Table 3, where SEM images of the mask and printed wafers show how well the patterns transferred. Table 3 shows SEM images for the 2000A oxide print-check wafers (both ADI and ACI) with high LER and SEM images for the 1700A SiN print-check wafers with low LER. The columns titled ADI KLA and ACI KLA are the mean defect sizes detected from the wafer inspections. The minimum defect sizes printed were decided by visually reviewing SEM images, and are in the columns labeled Print ADI and Print ACI. These SEM images clearly illustrate the aforementioned process development issues with noticeable LER and differences in the line width on some of the printed wafers. Even with the process variation, wafer inspection detected programmed defects on the SiN ACI wafer with sizes almost as small as the smallest printed defect. Analysis of image noise indicates that LER probably limits inspections. Thus 2830 inspections might detect even the smallest printed defects when LER improves. Non-programmed Defects The PDM1 mask had natural defects that wafer inspection found but mask SEM review was not able to see after the mask was cleaned. To determine whether these were true phase defects, we cleaned the mask and re-exposed a print check wafer and inspected it with a SEM. The potential phase defects were not found at the same coordinates on reexposed wafer. In other words, the potential defects are not phase defects but likely particles that were removed in the cleaning process. Figure 7. PDM2 We analyzed printability of absorber PD and printability of natural phase defects using the PDM2 mask and considered the stepper exposure effect on printability of mask defects using print-check wafers. The PDM2 has the same layout as PDM1 except: the spacing between the programmed defects changed from 20nm to 10nm (4X) and we increased of the number of defect columns from three to five. Programmed defect inspection results show good detectability for pin dot or extrusion which results in a bridge with under-exposure, and the same for pin hole or intrusion types which result in a notching-type defect with over-exposure. As shown in Fig. 8, exposure has an effect on defect printability. We can easily think that detectability gets better for smaller pin dot or extrusion types with under-exposure and worse with over exposure. Over- and under-exposure can make ± 10% CD variation in the printed line width.

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Mask

ADI KLA

ACI KLA

Print.(ADI)

Print.(ACI)

80nm

140nm

120nm

80nm

140nm

120nm

100nm

120nm

100nm

120nm

100nm

Intrusion

Extrusion

Pin hole

Pin dot

ADI KLA

ACI KLA

Print.(ADI)

Print.(ACI)

120nm

80nm

70nm

120nm

100nm

80nm

120nm

100nm

120nm

100nm

Intrusion

Extrusion

Pin hole

Pin dot

Table 3. SEM images of mask and printed defects for both oxide print-check (upper four rows) and 1700Ă&#x2026; SiN printcheck wafers (lower four rows). Note the oxide wafer has high LER and the SiN wafer has lower LER.

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Type I

Defect review at mask site

Type II

Mask

Mask Non visible

Wafer

Non visible

Wafer

Phase Defect?? Mask Cleaning

• Are Type I defects, phase defects? • Type I defects were not found at the same position after:

2nd Exposure

Mask cleaning Æ Expose Æ review. • Therefore, the source of type I defects seems to be from

Non visible

mask handling (moving particles?).

Figure 7. Phase defect verification method and results 10% Underdose

Optimum Dose

Pin dot

Pin hole

10% Overdose

Figure 8. a) Programmed defects captured vs. exposure 10% Under

Optimum

10% Over

Figure 8. b) Defect SEM images, upper pin dot, lower pin hole

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Best focus â&#x20AC;&#x201C; 0.05um

Best focus

Pin dot

Pin hole

Best focus + 0.05um

Figure 9. a) Programmed defects captured vs. focus offset Minus

Best

Plus

Minus

Pin dot (2, 5)

Intrusion (3, 5)

Pin dot (3,3)

Intrusion (4,5)

Best

Plus

Figure 9. b) Printability vs. focus offset. This defect has sensitivity to focus. With focus change, we compared the defects that we reviewed above and found that positive focus made better printability for some of the defects. However, for most of the defects, dose made the bigger change. We varied the focus by Âą50nm from best focus. As the focus moves from negative to positive, only the pin dot capture gets slightly worse, but the other defect types become slightly better. For more analysis, an in-line SEM was used to measure defect size and profile. Statistical analysis with an ANOVA test confirmed that there is no significant difference in defect size with focus offset. Profiles look similar as shown in Fig. 9 b). Therefore, we think that the small capture deference comes from other variables such as the combination of local variations of the wafer, thickness of resist pattern and other factors. For the evaluation of absorber defects, it is more effective to use exposure variations rather than focus variations. Using mask, ADI andACI inspection results for PDM2, we compared printability and detectability of natural defects and then classified potential phase defects with the results shown in Figure 10. As shown in Figure 10, the mask inspection found 154 defects. The ADI wafer inspection had 331 in total, but removing the programmed defects left 111 defects. The ACI wafer inspection had 447 defects in total, but removing the programmed defects left 210 defects. As indicated in figure 10, we divide inspection results for the non-programmed defects into categories (a)-(g). Categories (a)-(d) correspond to defects detected on the mask: (a) defects that were on the mask, but were not printed on the wafer, (b) defects that mask inspection detected but wafer inspection missed, (c) defects that mask and ACI detected, but ADI missed and (d) and defects that mask, ADI and ACI detected. Figure 11 shows SEM images from both mask and printcheck wafer for categories (a), (b) and (c).

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Mask 36a :

not printed on wafer

64b : printed on wafer but not detected 0 ADI

51d

52f

104g

Except PD

ACI

Except PD

Mask : 154ea

ACI : 447ea

ADI : 331ea

Mask 검사 결과

ADI def ect

ACI def ect

20000

15000

10000

5000

0 0

5000

10000

15000

20000

0 0

25000

5000

10000

15000

20000

25000

5000

10000

15000

20000

25000

Programmed defect area

Figure 10. PDM2 mask, ADI, and ACI inspection results.

Mask

ADI

Mask

(a) Detected by mask inspection tool, not printed on wafer

Mask

ADI

(b) Detected by mask inspection tool, not detected by wafer inspection tool, but printed ACI

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. H is t o g ra m o f Ty p e _ a , Ty p e _ b , Ty p e _ c , Ty p e _ d 9

Va ria b le Typ e _a Typ e _c Typ e _b Typ e _d

8 7 Fr e q u e n c y

6 5 4 3 2 1 0

100 120 D asize ta nm(X4) Defect

140

160

180

200

Figure 12. Size histogram of defects Type (a)~(d) less than 200nm(4X) To analyze printability of mask defects vs. size, and defect capture of the wafer inspection tool, we measured the mask defect size with a SEM and made a histogram of the result as shown in Fig. 12. Fig. 12 shows a histogram for defects smaller than 200nm. Larger defects are not included since we can print and detect all the defects larger than 200nm. Type (a) defects are mask defects which are not printed on the wafer and are the smallest. Type (b) defects are those that are too small for wafer inspection to detect. Type (d) defects are bigger than type (a) and (b) and have a uniform distribution with sizes larger than 110nm on the mask. This result generally matches the expectation that the bigger the mask defects are, the better they print and wafer inspection is more likely to capture them. However, there is no clear boundary between each type and overlaps of the regions exist. This is due to the different printability of defects that are generated naturally. Natural defects can have many different shapes (instead of a fixed programmed shape) and are located different distances from main pattern. Fig. 13 shows the simulation results for pin dot and extrusion defects, which have a vertical profile varying from 90 degrees to a sloped profile. As the absorber height is reduced and becomes smoother, defect CD decreases. In addition to CD and the defectâ&#x20AC;&#x2122;s relative location from main pattern, vertical profile is one of the factors that affect defect printability3. Therefore, we think that there exist overlapped regions rather than clear boundaries for the defect that are printed or not printed on the wafer. So, the printability of defects is not a straightforward exercise.

54.2nm

52.0nm

51.2nm

50.5nm

55.9nm

54.0nm

(a) Pin dot

61.8nm

59.5nm

(b) Extrusion Figure 13. Defect printability vs. defect profile

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The next step is to analyze defects detected by wafer inspection but not by mask inspection with the possibility that these are phase defects. Fig. 14 (a) shows two of the Type (e) defects (see figure 10 for type definitions) detected by wafer inspection at the ADI step: four of them are small defects and the others are non visual. SEM review of the ACI wafer at the same wafer coordinates reveals four defects as well: These defects are considered to be mask defects because they occur on both wafers at the same location. SEM review indicates that all 52 Type (f) defects (detected by wafer inspection at ACI and ADI) are real and occur on both wafers at the same location. Out of the total 104 type (g) defects detected on only the ACI wafer, 28 defects occurred on both ADI and ACI wafers at the same location; figure 15(b) shows two line bridges from this category. These defects were not detected by inspections of the ADI wafer. We considered all 84 defects that reside on both ACI and ADI wafers but were not detected by mask inspection as potential phase defects.

Small 4ea

False 4ea

a) Type (e) , ADI defects,

(b) Type (f)

4 of them existed on ACI wafer as well

28 ACI defects that also found at ADI

Figure 14. ILS image vs. defect type. Next we cleaned the mask and exposed another wafer to determine if the 84 wafer defects resulted from contamination of the mask after mask inspection. We then SEM reviewed the second-exposure wafer at the 84 positions determined from inspections of the first round of wafers. All 84 positions on the second-exposure wafer contained defects; thus particles introduced on the mask are an unlikely source of these 84 defects. We converted the wafer coordinates of the defects found before and after cleaning to mask coordinates and reviewed them on the mask. However, no defects on the mask were found, as shown in Fig. 16. Therefore, we believe that these 84 defects were all phase defects.

Figure 15. Defects found from wafer inspection after 1st and 2nd exposure and mask review results

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Next Steps We have two plans going forward. First, we plan to use the phase defect detection methodology that we developed and monitor the existence of phase defects on the full field masks that we plan to fabricate. Currently, we taped out a full field mask for a DRAM array of small contacts and will investigate the number of phase defects on this mask while device integration is ongoing. Second, we have also prepared another mask with 50/40/35/30nm HP to evaluate defect printability and detectability with different types of patterns and design rules. This evaluation is ongoing and we will see whether mask inspection detection capability is dependent on design rule.

4. CONCLUSION The ACI stack optimization worked out well with both signal and SNR increasing considerably with the thicker SiN film and pattern transfer. This allows for much smaller defects to be captured with the ACI print-check wafers compared with the standard PR short-loop wafers. We expect that the minimum sized defects are CD variations on the order of 11nm and ~6-8nm line short/open type defects. Going forward, we plan to compare these results on smaller DR print check patterns and validate the predictions with smaller defects than were available in this study. We fabricated and tested reticle masks with programmed defects. Using the PDM1 mask, we compared different wafer stacks and photoresists having varying LWR, and measured wafer defect detectability for this inspection step. As the defect signal simulation predicted, we observed the following capture rate and SNR results. z

ACI >> ADI

SiN 1700Å > SiN 1000 Å > Oxide 1000 Å

Low LWR > High LWR

LWR on the print-check wafers limited our sensitivity. Also, mask defects are not printed in any easy to understand way and the understanding of what prints required simulations of the mask-to-wafer transfer. We found that it was difficult to do defect studies for the pin dot and the pin hole types due to their defect printability fidelity. We tested defect printability and detectability for the PDM1 mask by varying the stepper exposure time and focus. We SEM reviewed wafers with varying EUV exposure conditions and investigated printability for exposure as well as focus. Over/under exposure condition enhanced defect printability and made inspection more sensitive for the absorber defect types, but focus variations made almost no difference in the printability. An optimized inspection recipe can detect natural mask defects larger than 40nm and programmed defects larger than 60 nm, at which size they just start to transfer onto the wafer. Phase defects were not found in the first mask, but potential phase defects on the second mask were found, as indicated by the lack of re-detection during wafer SEM review of 84 of these printed defects. We have plans to suggest new controls and improvements by monitoring defects, including phase defects, over a full-field mask. We will use a different PDM and check for defect printability, defect detectability, and for inspection tool performance to get ready for EUV litho mass production.

5. ACKNOWLEDGMENTS We would like to thank Jinhong Park, Sean Huh, Chawon Koh for help with exposing wafer and samsung mask shop EUV team for their making programmed defect mask.

6. REFERENCES [1] Stokowski, S. and Wack, D, “Using a 193-nm inspection tool for multi-layer mask blank inspection,” 2009 International EUVL Symposium, Prague, Czech Republic, 18-21 Oct 2009. [2] Christian Holfeld, Karsten Bubke, Falk Lehmann, Bruno La Fontaine, Adam R. Pawloski, Siegfried Schwarzl, Frank-Michael Kamm, Thomas Graf, Andreas Erdmann , " Defect Printability Study using EUV Lithography," Proc. SPIE 6151, 61510U (2006). [3] Rik Jonckheere, Fumio Iwamoto, G.F. Lorusso, A. M. Goethals, K. Ronse,H. Koop, T. Schmoeller, , " Investigation of mask defectivity in full field EUV", Proc. SPIE 6730, 673012 (2007).

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[4] Jinhong Park, Seong-Sue Kim, SukJoo Lee, Sang-Gyun Woo, Han-Ku Cho and Joo-Tae Moon, " Simulation and experiments for inspection properties of EUV mask defect", Proc. SPIE 6283, 62833E (2006). [5] Hakseung Han, Kenneth A. Goldberg, Anton Barty, Eric M. Gullikson, Yoshiaki Ikuta, Toshiyuki Uno, Obert R. Wood II and Stefan Wurm, " EUV MET printing and actinic imaging analysis on the effects of phase defects on wafer CDs", Proc. SPIE 6517, 65170B (2007). [6] Yoshihiro Tezuka, Jerry Cullins, Yuusuke Tanaka, Takeo Hashimoto, Iwao Nishiyama, Tsutomu Shoki, " EUV exposure experiment using programmed multilayer defects for refining printability", Proc. SPIE 6517, 65172M (2007). [7] Wonil Cho, Hak-Seung Han, Kenneth A. Goldberg, Patrick A. Kearney, Chan-Uk Jeon, " Detectability and printability of EUVL mask blank defects for the 32 nm HP node", Proc. SPIE 6730, 673013 (2007).

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