Automated optimized overlay sampling for high-order processing in double patterning lithography Chiew-seng Koaya, Matthew E. Colburna, Pavel Izikson , John C. Robinson*c, Cindy Katod, Hiroyuki Kuritad, Venkat Nagaswamic a IBM Corp., 257 Fuller Road, Albany NY 12303 USA; b KLA-Tencor Israel, 1 Halavian Street, Migdal Ha'Emak 23100, Israel; c KLA-Tencor Corp., One Technology Drive, Milpitas, CA 95035 USA; d KLA-Tencor Japan Ltd., 134 Godo-Cho, Hodogaya-Ku, Yokohama, 240-0005 Japan b
ABSTRACT A primary concern when selecting an overlay sampling plan is the balance between accuracy and throughput. Two significant inflections in the semiconductor industry require even more careful sampling consideration: the transition from linear to high order overlay control, and the transition to dual patterning lithography (DPL) processes. To address the sampling challenges, an analysis tool in KT-Analyzer has been developed to enable quantitative evaluation of sampling schemes for both stage-grid and within-field analysis. Our previous studies indicated (1) the need for fully automated solutions that takes individual interpretation from the optimization process, and (2) the need for improved algorithms for this automation; both of which are described here. Keywords: overlay, metrology, sampling, double patterning
1. INTRODUCTION Sampling has always been a key topic for metrology with the primary focus being the balance between data accuracy and cycle time1,2. In high-end semiconductor manufacturing, as design rules shrink, the accuracy requirements become ever more stringent. Sampling garners considerable attention during major industry inflection points. In the past these inflection points have included the transition from aligners to steppers, from steppers to scanners, and during wafer diameter transitions. Currently the industry is undergoing a lithographic inflection from linear control to high-order (HO) control including both inter-field and intra-field3. This work addressed overlay metrology and the transition to high-order control. Historically, sampling analysis has been a manual and difficult process and often times involves engineering judgment by individuals. This work involves the evaluation of a fully automated software tool in KLA-Tencor Corp.’s KT Analyzer to address sampling requirements. As was reported previously, a key requirement is for an automated tool that reduces or eliminates the need for individual judgment calls.2,4. 1.1 Design of Experiment To perform the sampling analysis, a super-set of data was required that contained a high number of overlay data-points corresponding to intra-field and inter-field targets. For this, a DPL mask-set was generated which contained test patterns, various inter-field and intra-field alignment and registration marks. The zero layer mask was generated using a Pattern Generator and L1 and L2 were generated using an e-beam system at a third party mask-shop. The mask-set consisted of a Zero Layer (L0), and a test pattern split in to 2 separate masks (L1 and L2). L1 contained one portion of the alignment mark and L2 contained the remaining portion, as color coded in green and red respectively in Fig. 1. The Test Pattern on the mask contained cells of 11x 14 rows and columns and each cell contained various Overlay Registration targets over a field size of approximately 24x30 mm. In each field, 49 locations were available for measurement. All possible exposure fields (71) were measured resulting in approximately 3500 data points (intra-field and inter-field) per wafer. Five wafers were used in this experiment (referred as W21 to W25 later in the paper) to account for wafer to wafer variability. The wafers were exposed using a DPL Litho-Freeze-Litho process by IBM at Albany5,6. From this super-set of data (henceforth referred to as ‘omniscient’), it was possible to select desired number of data-points in a step-wise fashion (e.g. 6, 12, 20, 27, 35 etc.) and test the model accuracy compared to the maximum available data. *John.Robinson@KLA-Tencor.com; phone 1 512-231-4221 Metrology, Inspection, and Process Control for Microlithography XXIV, edited by Christopher J. Raymond, Proc. of SPIE Vol. 7638, 76381R · © 2010 SPIE · CCC code: 0277-786X/10/$18 · doi: 10.1117/12.846371
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