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Methods for Benchmarking Photolithography Simulators: Part V Trey Graves, Mark D. Smith, and Sanjay Kapasi KLA-Tencor Corp., ABSTRACT As the semiconductor industry moves to double patterning solutions for smaller feature sizes, photolithography simulators will be required to model the effects of non-planar film stacks in the lithography process. This presents new computational challenges for modeling the exposure, post-exposure bake (PEB), and development steps. The algorithms are more complex, sometimes requiring very different formulations than in the all-planar film stack case. It is important that the level of accuracy of the models be assessed. For these reasons, we have extended our previous papers in which we proposed standard benchmark problems for computations such as rigorous EMF mask diffraction, optical imaging, PEB, and development [1-4]. In this paper, we evaluate the accuracy of the new PROLITH wafer topography models. The benchmarks presented here pertain to the models (and their associated outputs) most affected by the switch to non-planar film stacks: imaging at the wafer (image intensity in-media) and PEB (blocked polymer concentration). Closed-form solutions are formulated with the same assumptions used in the model implementation. These solutions can be used as an absolute standard and compared against a simulator. The benchmark can then be used to judge the simulator, in particular as it applies to speed vs. accuracy tradeoffs. Keywords: Lithography simulation, numerical accuracy, image intensity, post-exposure bake, PROLITH

1. INTRODUCTION Single patterning lithography has pushed k1 values near the theoretical limit (0.25). Double patterning will be the method used to print features at the 32nm and 22nm nodes and possibly beyond. Double patterning presents some new challenges for lithography simulation. In the past, it was a good assumption that the wafer stack was made of planar homogeneous films. The first patterning step in a double patterning process is modeled well under this assumption. However, in the second step this is no longer the case. Imaging, PEB, and develop computations must handle the non-planar topography introduced by processes such as etch, spin coating, deposition, etc. The algorithms that do these computations are more complex, sometimes requiring very different formulations than in the all-planar film stack case The accuracy of simulators is important, especially if lithographers are to use these simulators to make quantitative assessments that lead to critical decision making. It is also important to realize that there are many ways to model various steps in the photolithographic process. FDTD, RCWA, and FEM are just a few of the methods that can be used to determine the image-in-media in a non-planar film stack. Regardless of the implementation of the model, the algorithm should have good characteristics in terms of accuracy and convergence. It is also necessary that any numerical implementation of a model in a simulator be reasonably fast, as well as free of bugs or algorithm problems. For these reasons, we have extended our previous papers [1,2,3,4] where we proposed standard benchmark problems for aerial image calculations, image in resist calculations, EMF mask topography effects, PEB, and development. The benchmarks presented here are for image-in-media and post-exposure bake (PEB) under wafer topography conditions. We will use closed-form solutions as an absolute standard to judge the accuracy of a simulator. The benchmark can then be used to judge the simulator as it applies to speed vs. accuracy tradeoffs.

Optical Microlithography XXIII, edited by Mircea V. Dusa, Will Conley, Proc. of SPIE Vol. 7640, 764033 路 漏 2010 SPIE 路 CCC code: 0277-786X/10/$18 路 doi: 10.1117/12.846376

Proc. of SPIE Vol. 7640 764033-1 Downloaded from SPIE Digital Library on 12 Mar 2010 to 192.146.1.254. Terms of Use: http://spiedl.org/terms


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