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Recess gate process control by using 3D SCD in 3xm vertical DRAM Ming-Feng Kuo*a, Sheng-Hung Wua , Tien-Hung Lana ,Shuang-Hsun Changa a Rexchip Electronics Corp. NO. 429-1 Sanfong Rd, Houli Township, Taichung City, Central Taiwan Science Park. Taiwan, R.O.C Elvis Wangb, Houssam Chouaibb, Harvey Chengb, Qiang Zhaob b KLA-Tencor Corporation, One Technology Drive, Milpitas, CA, USA 95035 ABSTRACT As DRAM design advances from planar to vertical integration, process control of the recessed gate, generated by etching after patterning in vertical DRAM, is very critical because of the impact on device electrical characteristics and subsequent effect on yield. 3D Scatterometry Critical Dimension (3D SCD) technology is a widely-used metrology approach for process control for leading edge CMOS and DRAM IC manufacturing.

In this paper, the latest KLA-Tencor AcuShapeTM modeling software with 3D SCD capability is used in the modeling and solution development, and the SpectraShapeTM 8660 is used for data collection and CD measurement.

Recess gate measurements were taken in the active cell area having a non-orthogonal structure. The SCD measurement results were successfully confirmed to correlate well with cross-section Scanning Electron Microscope (X-SEM) and electrical performance data.

Keywords: Scatterometry, Optical metrology, Recess Gate, Vertical DRAM, Memory cell, Process control, 3D applications, Fin height

1. INTRODUCTION Buried word line/bit line with vertical transistor now main stream in DRAM manufacturing. 6F2 buried word line is now in mass production at 4Xnm and 3Xnm design rules and 4F2 vertical DRAM will be in mass production in the near future [1]. The advantages of buried word line technology from a device performance perspective are as follows: (1) A low resistive interconnect and metal gate of the array transistors; (2) High array device on-current; (3) Small parameter variability (4) High reliability; (5) Small parasitic capacitances; (6) Excellent array performance; (7) The array device can be scaled down to 30nm without compromising performance. From an economic point of view: (1) Higher yield for a less complex process; (2) More revenue at a faster cycle time; (3) Better time to yield; (4) Smaller Die size [2~3].

SCD has three main advantages for mass production process control: (1) It provides a fast time to result compared to XSEM, Transmission Electron Microscope (TEM) or AFM measurement; (2) It is nondestructive; (3) It is precise and has a small total measurement uncertainty (TMU) [4-6]. In this study, recess gate process control for the etching process after patterning is very critical because it will have direct impact on device electrical characteristics (Rs, Idsat, threshold voltage, etc…) and furthermore affects yield. 3D Scatterometry Critical Dimension (3D SCD) technology is now a widely-used metrology approach for process control for leading edge CMOS and DRAM IC manufacturing [7~9]. 3D in cell structures are used in this study and not 2D test structures because of micro-loading effects, which play a majority role impacting profile and CD differently on 2D testing structures and 3D cell structures in the etching process. This phenomenon is especially severe for design rule shrinks to 3xnm and beyond.

Figure 1 shows a simplified process flow to form a recess gate utilizing AcuShapeTM modeling software. A traditional STI (shallow trench isolation) is formed in the first step, followed by an oxide liner deposition. An isolation nitride is filled to separate the active area. Next, an oxide hard mask is formed. Finally, a recess gate structure is generated in the

Metrology, Inspection, and Process Control for Microlithography XXVI, edited by Alexander Starikov, Proc. of SPIE Vol. 8324, 83241Z · © 2012 SPIE · CCC code: 0277-786X/12/$18 · doi: 10.1117/12.916143

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etching and cleaning step after photo patterning. The fin gate height and silicon etching depth are very critical for DRAM final performance, requiring close monitoring in the DRAM production process.

Figure 1: A simplified process flow to form a recess gate.

2. DESCRIPTION OF METROLOGIES 2.1 Scatterometry Scatterometry is a valuable metrology measurement technique because of its high throughput, low relative cost, and small TMU. Scatterometry is an optical method in which polarized light from a regular array is collected and analyzed.

The KLA-Tencor SpectraShape™ 8660 metrology system with the latest SCD modeling software, AcuShape™, was used in this experiment. Figure 2 shows an overview of the scatterometry measurement process. A grating is illuminated with broad-spectrum polarized light and ellipsometric values α and β are extracted as a function of wavelength. These are called the measured spectra, which are then compared to an existing group of theoretical spectra (referred to as the library). The theoretical spectra are typically generated prior to measurement using known information about the sample. Such information includes: film optical constants, the period of the features and the profile characteristics.

Parameters describing the sample are varied, and a theoretical spectrum is generated for each set of parameter values.

The measured spectrum is then compared to the set of theoretical spectra to determine best-fit parameter values.

Figure 2: Overview of the scatterometry measurement process. KLA-Tencor’s SpectraShapeTM 8660 is the scatterometer used in this experiment.

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2.2 Electrical characteristics test Agilent (JP30H30445) tool is used for testing Vt for wafer acceptance test.

2.3 X-SEM Hitachi (S5500) is used for cross section check. A scanning electron microscope (SEM) is a type of electron microscope that images a sample by scanning it with a high-energy beam of electrons in a raster scan pattern.

3. MEASUREMENT MODEL A schematic presentation of top, isometric, and side views of the model used for the recess gate process step is shown in Figure 3. There are nine degrees of freedom (DOFs) in this model: SiN_HT, STI_Depth, Oxide_HT ,Si_Depth, OX_TCD, ISSG, STI_TCDmin, STI_BCDmin, Si Fin_HT. For SCD 3D applications, it is very important to build the model as close as possible to real cell structure.

Figure 3: Top view (top), isometric (left) and side view (right) of the simplified model used for the recess gate etch ACI process step.

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4. Design of experiment Table 1: DOE split table for Si Fin Ht and Si Depth of recess gate.

A design of experiment (DoE) is used to verify if SCD can detect the Si Depth and Si Fin Height changes in the recess gate etch process.

Table 1 shows the DOE split table for Si Fin Ht and Si Depth. The experiments are designed to detect Si Depth and Si Fin Height changes as a function of the etch time. The first split is primarily designed to detect the Si Depth change and the second split is primarily designed to detect the Si Fin Height change.

For the Si Depth split experiment, Si Fin Height has a 3nm range with an etch rate of 0.3nm/second. The Si Depth has 18nm range and an etch rate of 1.8nm/second.

For the Si Fin Height split experiment, the Si Fin Height has a 7.8nm range with an etch rate of 1.3nm/second. The Si Depth has a 7.8nm range and an etch rate of 1.3nm/second.

DoE table of Si Depth and Si Fin Height Wafer Si Depth Split(Sec.) Si Fin Height Split (Sec.) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Ref.+1 Ref.+2 Ref.+3 Ref.+4 Ref.+5 Ref.+5 Ref. Ref.-2 Ref.-3 Ref.-4 Ref.-5 Ref. Ref. Ref. Ref. Ref. Ref. Ref.

Ref. Ref. Ref. Ref. Ref. Ref. Ref. Ref. Ref. Ref. Ref. Ref.-1 Ref.-2 Ref.-3 Ref. Ref.+1 Ref.+2 Ref.+3

5. RESULTS AND DISCUSSION 5.1 Si Depth and Si Fin Height vs. Etch time

R² = 0.919

Si Fin Height_SCD (nm)

Si Depth_ SCD (nm)

Figures 4a and 4b show the Si Depth and Si Fin Height vs. etch time, respectively. SCD has good correlation with etch time for both Si Fin Height and Si Depth, with a correlation index, R2, greater than 0.9. The Si Depth measured by SCD has positive correlation vs. etch time and the Si Fin Height has negative correlation with etch time.

R² = 0.977

Etch Time (Sec)

Etch Time (Sec)

Figure 4a: Si Depth measured by SCD vs. etch time.

Figure 4b: Si Fin Height measured by SCD vs. etch time.

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5.2 Si Depth and Si Fin Height vs. Vt. (Threshold voltage) Figures 5a and 5b show the Si Depth and Si Fin Height vs. threshold voltage, respectively. Both the Si Depth and Si Fin Height measured by SCD show good correlation with Vt, with a correlation index, R2, of approximately 0.9. The Si Depth has positive correlation vs. etch time and the Si Fin Height has negative correlation with etch time.

Si Depth vs. Vt

Si Fin Height vs. Vt

R² = 0.945

Vt(Avg.)

Vt (Avg.)

R² = 0.893

Si Depth (nm)

Figure 5a: Si Depth vs. Vt.

Si Fin Height

Figure: 5b. Si Fin Height vs. Vt.

5.3 Agreement Between X-SEM and SCD An X-SEM is used to cross check the Si Depth and Si Fin Height. The disadvantage of an X-SEM are as follows: (1) It provides a slow time to result, usually taking one day to complete a measurement; (2) It is destructive; (3) It is less precise and has a large TMU that make it undesirable for production applications. Figure 6 shows the agreement between X-SEM and SCD results. SCD measured results are more consistent for wafer to wafer trends compared to XSEM on Si Depth and Si Fin Height measurements.

Figure 6: Agreement between X-SEM and SCD results for Si Fin Height and Si Depth measurements.

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5.4 Precision Testing on SCD A static precision test consists of repeated measurements of the same structure without changing the relative positions of the wafer and optical beam. For this study, data from ten repeats of SCD measurements were collected. The results are displayed in figure 7. The standard deviation of the mean value of the Si Fin Height is 0.01 nm and Si Depth is 0.03nm.

This result shows 3D SCD is suitable for production monitoring of these two critical parameters of recess gate process.

Si Fin Height

1

2

3

4

5

6

Si Depth

7

8

9

10

1

2

3

4

5

6

7

8

9

10

Figure 7: Within-wafer precision measurement results using SCD for Si Fin Height and Si Depth measurements.

5.5 Daily Trend Chart in Production A daily monitor trend chart of Si Fin Height and Si Depth were collected, as shown in figure 8. Data was collected on 183 production wafers with all of the data falling within the upper\lower limit of specification. The result shows SCD 3D library has very good and consistent performance in measuring recess gate critical parameters.

Figure 8: Results of daily trend chart of Si Fin Height and Si Depth measurements.

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6. CONCLUSIONS As vertical DRAM design rule scaling continues below 3Xnm, process control of the Si fin height and Si depth of the recess gate has become more critical. Improper Si fin height and Si depth control of the recess gate process will affect device electrical characteristics, especially in threshold voltage and subsequent device yield. An SCD 3D application showed good correlation to threshold voltage, the reference measurement system, and thus can be used to monitor Si fin height and Si depth difference in production. SCD also has the advantage over other available metrology technologies of being a non-destructive method and provides more repeatable measurements.

As structure complexity increases, metrology to characterize and control such structures becomes more challenging.

In this study, the latest SpectraShapeTM 8660 with AcuShapeTM 3D SCD was used in the 3D model and calculation.

Recess Gate measurement in the cell area with non-orthogonal structure can be measured and confirmed with X-SEM measurement and electrical data successfully.

ACKNOWLEDGEMENTS The authors would like to thank Ching-I Chen who contributed to this project and performed all of the X-SEM measurement used in this project.

REFERENCES [1] International Technology Roadmap for Semiconductors (ITRS), http://member.itrs.net./ [2] G. Dan Hutcheson ”Qimonda and the strategic advantage of buried Word Line” VLSI research Inc. May, 2008 [3] Schloesser et al., "A 6F2 Buried Wordline DRAM Cell for 40nm and Beyond", IEEE, Qimonda Dresden GmbH & Co., pp. 809-812 (2008).

[4] R. Liou et al, “Feasibility of measuring Four Profile Parameters for Metal-0 Trench of DRAM by Spectroscopic Ellipsometry Based Profile Technology”, Semiconductor Manufacturing Technology Workshop Proceedings, p.156~159, 2004 [5] M.K. Lee et al, “Applications of AFM in semiconductor R&D and manufacturing at 45nm technology node and beyond”, Proc. of SPIE Vol. 7272, 2009 [6] M. Sendelbach et al, “Comparison of scatterometry, atomic force microscope, dual beam system, and XSEM to measure etched via depths”, Proc. of SPIE Vol. 5752, p.272-287, 2005 [7] M. Yeh et al., “Capability of spectroscopic ellipsometry-based profile metrology for detecting the profile excursion of poly silicon”, Proc. of SPIE Vol. 5375, p.1135-1143, 2004 [8] T.G Dziura et al., “Measurement of high-k and metal film thickness on FinFET sidewalls using scatterometry”Proc. of SPIE, Vol.6922, 2008 [9] M. Duan et al, “Metrology of micro-step height structures using 3D scatterometry in 4x-nm advance DRAM” Proc. of SPIE, Vol.7971, 2011

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