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Multi-Level Overlay Techniques for Improving DPL Overlay Control Charlie Chen1, Y C Pai, Dennis Yu1, Peter Pang1, Chun Chi Yu1 , Robert (Hsing-Chien) Wu 2, Eros (Chien Jen) Huang2, Marson (Chiun-Chieh) Chen2 , David Tien3 , Dongsub Choi4 1

United Microelectronics Corporation / Nanke 2nd Rd., Tainan Science Park, Shnshih Township, Tainan County 741, Taiwan 300, R. O. C. 2 KLA-Tencor Corporation / OMD, HSINCH-23337/Shan-Hua, Tainan, Taiwan 3 KLA-Tencor Corporation, One Technology Drive, Milpitas, CA 95035, USA 4 KLA-Tencor Corporation / OMD, Hwasung-city, Gyeonggi-do, 445-160, Korea ABSTRACT

Overlay continues to be one of the key challenges for lithography in semiconductor manufacturing, especially in light of the accelerated pace of device node shrinks. This reality will be especially evident at 20nm node where DPL and multi-layer overlay will require 4nm or less in overlay control across many critical layers in order to meet device yield entitlements. The motivation for this paper is based on improving DPL overlay control in face of the high complexity involved with multi-layer overlay requirements. For example, the DPL-2nd-litho layer will need to achieve tight registration with the DPL-1st-litho layer, and at the same time, it will need to achieve tight overlay to the reference-litho layer, which in some cases can also be a DPL layer. Of course, multi-level overlay measurements are not new, but the combination of increased complexity of multi-DPL layers and extremely challenging overlay specifications for 20nm node together will necessitate a better understanding of multi-level overlay control, specifically in terms of root cause analysis of multi-layer related overlay errors and appropriate techniques for improvement In this paper, we start with the identification of specific overlay errors caused by multi-layer DPL processing on full film stack product wafers. After validation of these findings with inter-lot and intra-lot controlled experiments, we investigate different advanced control techniques to determine how to optimize overlay control and minimize both intra-lot and inter-lot sources of error. A new approach to overlay data analysis will also be introduced that combines empirical data with target image quality data to more accurately determine and better explain the root cause error mechanism as well as provide effective strategies for improved overlay control.

Keywords: Overlay, DPL, Multi-level

1. INTRODUCTION The shrinking of the semiconductor device involves not just device scaling but also device structure complexity to embody the device a in smaller area on wafer. As a consequence, the relationship among layers or litho steps becomes more complicated. This fact heightens the multi-layer overlay measurement complexity by involving more than two levels of overlay measurements for the same layer.

In case of single-level measurement, the control can simply rely on one single layer measurement. However, multi-level overlay have more than 2 measurement sets. Therefore, multi-level overlay control can have several different control schemes; one-level is for the control and the other-level is for monitoring only, both-levels are for the control with weighting, or one-level is for x-direction control and the other-level is for y-direction Metrology, Inspection, and Process Control for Microlithography XXVI, edited by Alexander Starikov, Proc. of SPIE Vol. 8324, 83242A 路 漏 2012 SPIE 路 CCC code: 0277-786X/12/$18 路 doi: 10.1117/12.915711

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control. The decision depends on the design of the device structure. In this paper, we mainly investigate the case that one level is for the control and the other is for monitoring. Figure1 is one of the typical multi-level overlay measurements, and Figure2 is another case. Our investigation focused on the DPL layer because DPL is expected to be the most popular multi-level use-case until EUV lithography becomes a viable solution. In the case of DPL there are 2 measurements; one is Litho-2(2nd) to Litho-2(1st) and the other is Litho-2(2nd) to Litho1(1st).

Figure 1: Multi-level measurement for the single layer case (left) Figure 2: Multi-level measurement for DE/DPL layer case (right)

When overlay control performance is being discussed, the residual of the control model is often used to indicate the maximum achievable performance. As an example for the maximum achievable, you can get overlay results very close to your residuals when you expose the wafer after rework because you already know the suitable parameters of the correction. This is one of the reasons that residual suggests the maximum achievable overlay performance. Of course, residuals can be also used for many other purposes like comparing different control models to see which one is superior for the control. However, in the case of multi-level overlay, the residuals have to be considered in the context of the multi-level control scheme being used. Conventional residuals are the leftover after removing the model parameters from the raw data. However, in the case of multi-level measurement, there are multi-sets of measurements, and the scanner cannot correct 2 different set of corrections for one exposure step. Therefore, conventional residuals cannot be achieved in the same way for some overlay layer schemes of measurement. In this case, the actual achievable performance has to be considered differently.

From here, we will call the actual achievable performance as relative residuals, and relative residuals will depend on the control scheme.

Our investigation is based on the control scheme that measurement of Litho-2(2nd) to Litho-1 is the measurement for overlay correction parameter calculation, and the measurement of Litho-2(2nd) to Litho-2(1st) is only being used for monitoring. Based on the investigated control scheme, conventional residuals and relative residuals were calculated in Figure 3. We noticed that the practical achievable overlay performance of Litho2(2nd) to Litho-2(1st) is significantly inferior to the typical residual of control based on a traditional binary layer combination. The reason for the gap is that the relative residuals of Litho-2(2nd) to Litho-2(1st) still contains unmodeled parameters, while traditional binary layer schemes generally remove all the modeled parameters completely from the raw data. This indicates that minimizing for the modeled parameter difference between 2 measurements is one of the keys for maximum performance in overlay control. Once you minimize the modeled parameter difference between measurements, you can make your practical maximum achievable as close as possible to the residuals for each individual measurement.

As the overlay margin becomes more and more tight, especially for DPL, each level of measurement will also require tighter overlay specification. Therefore, the gap between residuals and relative residuals has to

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be minimized to achieve maximum performance. We found that the wafer scale term followed by the translational term were the main terms identified in the leftover model parameters for the experimental layer.

Figure 3: Overlay Map of Field Average; upper-left is raw data of ‘aa’, upper-middle is residual of ‘aa’, bottomleft is raw data of ‘bb’, bottom-middle is residual of ‘bb’ and bottom-right is the relative residual of ‘bb’ High order correction is one of the methods to improve overlay and reduce the residuals since it provides higher degrees of freedom to model the data than linear corrections. We checked the potential improvement of several high order correction methods in Figure 4. Equation (1) is a model of high order grid for HOPC, and Equation (2) is a model of high order field for iHOPC. We also checked another multi-level control layer, similar to Figure 1. Wafer scaling was also found to be the main difference between different levels of measurement in as shown in Figure 5.

dx = k1 + k 3 * X + k 5 * Y + k 7 * X 2 + k 9 * XY + k11* Y 2 + k13 * X 3 + k15 * X 2Y + k17 * XY 2 + k19 * Y 3 dy = k 2 + k 4 * X + k 6 * X + k 8 * X 2 + k10 * XY + k12 * Y 2 + k14 * X 3 + k16 * X 2Y + k18 * XY 2 + k 20 * Y 3

dx = k1 + k 3 * X + k 5 * Y + k 7 * X 2 + k11 * Y 2 + k13 * X 3 + k19 * Y 3 dy = k 2 + k 4 * X + k 6 * X + k 8 * X 2 + k10 * XY + k12 * Y 2 + k14 * X 3 + k16 * X 2Y + k 20 * Y 3

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Eq.(1)

Eq.(2)

Figure 4 Residuals of several high order correction methods ( DPL layer )

Figure 5: Residuals of several high order correction methods (Non-DPL layer) In the next step, we investigated whether this phenomenon is stable. We measured 3 lots to check inter-lot and intra-lot stability by checking the wafer scaling difference. The following are the wafer sampling for the measurements. The results show that the phenomenon is repeatable among inter-lot and intra-lot for the 3 lots investigated (Figure 6): Lot-A : Slot # 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 Lot-B : Slot # 1, 2 Lot-C : slot # 1, 2, 13, 14, 24, 25

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Figure 6: Wafer Scaling difference between ‘aa’ and ‘bb’

2. Experiment and analysis In the previous section, we identified the issues involved with multi-level control, which proved to be common to DPL schemes as well. Potential root-causes were identified to explain this effect and each root-cause was investigated accordingly: (1) Remaining model parameters at relevant reference layer (2) Process induced measurement (3) Process induced overlay (1) Remaining model parameters at relevant layer In Figure 7, when ‘overlay of Litho-2(1st ) to Litho-1’ is zero, there should be no overlay difference between ‘overlay of Litho-2(2nd) to Litho-1’ and ‘overlay of Litho-2(2nd) to litho-2(1st), because ‘cc overlay’ should be the same as ‘aa overlay minus bb overlay’. Figure 8 shows simplified drawings for multi-level overlay cases of Figure 7. When overlay of cc is zero, there are 2 cases; one is both aa and bb are zero, and the other is neither aa nor bb are not zero; but still aa overlay and bb overlay are the same. When overlay of cc is not zero, overlay of aa and bb become different. Therefore, we checked if the overlay difference between ‘aa’ and ‘bb’ is coming from the overlay of ‘cc’. If the scaling difference of ‘aa’ and ‘bb’ is coming from ‘cc’, we should have seen the scaling parameters of ‘(aa-bb) – cc’ as close to zero. Instead, the calculated results showed that the calculated scaling of ‘(aa-bb) – cc’ is nothing close to zero as shown in Figure 9. Considering that the calculated scaling is on the order of several nanometers at the wafer edge (Figure 9), it is hard to consider this as simple noise which might come from multiple different target measurements or multiple different locations. We also checked that the overlay raw data correlation between ‘calculated overlay (aa-bb)’ and measured overlay ‘cc’ as shown in Figure 10. Based on both results, we assume that there is an unknown overlay influence causing the scaling difference between ‘aa’ and ‘bb’ measurements on top of the remaining overlay error from the cc measurement.

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Figure 7: Multi-level measurement scheme

Figure 9: Calculated wafer scale of ‘(aa-bb)-cc’

Figure 8: Overlay error examples: Overlay of ‘cc’ is zero (left and middle) and overlay of ‘cc’ is non-zero (right)

Figure 10: Raw data correlation between (aa-bb) vs cc

(2) Process induced measurement One potential inconsistency of calculated cc-overlay (aa-bb) and measured cc-overlay is the influence process effect to the measurement. Non-litho-processes like etch, CMP (Chemical Mechanical Polish), or deposition can influence the profile of the measurement target. In turn, this profile influence can influence the overlay measurement. As one of the studies (Investigation on Accuracy of Process Overlay Measurement[1] ) previously reported, different wavelength of measurement can report different overlay, especially when the overlay target has process influence to target profile. This influence can eventually influence the measurement.

KLA-Tencor has introduced a new capability to determine the image quality of the measurement. This capability was used for the investigation of the process induced measurement quality. We exposed the wafer with DE (Double Exposure) and then measured the overlay and reworked the wafer. We measured the same overlay target again but with DPL processes (non-lithography processes between litho-2(1st) and litho-2(2nd)).

This means the reference target of the overlay mark has been processed by non-lithographic DPL processes. We compared the image quality merit for both measurements in Figure 11, and we could easily confirm that measurement quality was degraded. Also, we measured that the overlay of Litho-2(2nd) to Litho-1 with different color filters and found that wafer scaling range among colors was more than several nanometers as shown in Figure 12.

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Figure 11: Image quality merit of DE process (left) and Image quality merit of DPL process (right)

Figure12: wafer scaling with 5 different measurements We used the image quality merit to create the optimized measurement recipe. Figure 12 shows the overlay map and image quality merit map before and after recipe optimization. We optimized the ‘aa’, ‘bb’ and ‘ccc’ recipes based on image quality merit (The ‘cc’ recipe could not be optimized further since cc-overlay was measured at previous layer. Therefore, we used ‘ccc’ recipe which is the measurement at Litho-2(2nd) step for the target of ‘cc’ overlay). After we re-checked the correlation based on optimized measurements, we could observe improved correlation between calculated overlay from ‘aa-bb’ and measured overlay of ‘ccc’ and also wafer scaling terms became more similar in Figure14. Nevertheless, a significant degree of wafer scaling difference still remained. Although measurement optimization helped to explain some of the wafer scaling difference, there is still some additional wafer scaling influence beyond measurement influence by process.

(a)

(b)

(c)

(d)

Figure 13: Recipe optimization using image quality merit; overlay map before optimization (a), Image quality merit map before optimization (b), Overlay map after optimization (c), Image quality merit map after optimization (d)

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Figure14. correlation-x before recipe optimization (1), correlation-y before recipe optimization (2), correlation-x after recipe optimization (3), correlation-y after recipe optimization (4), wafer scaling terms comparison before recipe optimization (5), wafer scaling term comparison after recipe optimization (6) (3) Process induced overlay Another potential root-cause is that non-litho processes between Litho-2(1st) and Litho-2(2nd) actually induce wafer overlay. A possible explanation for this is that since cc-overlay is being measured before these processes, the induced overlay cannot be detected at cc-overlay measurement. To prove this theory, we measured the ccoverlay target before and after these processes. Figure 15 shows the overlay difference before and after these processes. There are several potential reasons for the process induced overlay, such as strain mismatch among films and substrate, different thermal expansions among films and substrate, or even non-perpendicular etching.

After adding the process induced wafer scaling into account, we could achieve better correlation as shown in Figure 16. This process induced overlay can be overcome by applying intentional overlay error at reference layers as seen in Figure 17.

(a)

(b)

(c)

Figure 15: Overlay influence by non-litho process; overlay before the processes (a), overlay after the processes (b), grid correctable of the delta (c)

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Figure 16: Scaling difference measured overlay and calculated overlay

Figure 17: Overlay measurement diagram (left), overlay control without intentional overlay error (middle), overlay control with intentional overlay error at relevant reference layer(right)

3. SUMMARY The key finding from this study revealed that minimizing the modeled parameter differences between measurements is critical to achieving maximum entitlement for multi-level overlay control. The challenge posed by multi-layer overlay control, especially as it relates to DPL, was investigated in depth. The multilayer overlay challenges posed by the DPL wafers investigated showed significant overlay error that seemingly was not correctable. However, after an exhaustive study and with significant data collected and analyzed, clear root-cause for this problem was determined and experimentally confirmed. Moreover, practical solutions were provided and validated in the fab. Through all of this work, an important new capability to measure the image quality merit was effectively validated and applied on the wafer measurements to help unravel both the measurement and process induced overlay effects on the metrology target in order to finally achieve entitlement overlay control and performance. In summary, using the tools and techniques discussed in this study enabled the removal of all the relevant remaining systematic modeled errors initially found on this DPL process layer and will make a significant advancement to the understanding and capability to control DPL overlay to meet the 20nm process node.

4. Reference

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[1] Chan Hwang, Jeongjin Lee, Seungyoon Lee, Jeongho Yeo, Yeonghee Kim Hongmeng Lim and Dongsub Choi, “Investigation on Accuracy of Process Overlay Measurement,” Proc. SPIE 7971, 7971-50 (2011)

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