Autumn99

VOLUME 2 ISSUE

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AUTUMN 1999

$5.00 US

Yield Management

S O L U T I O N S Yield Enhancement and Process Control Strategies for the Semiconductor Industry

SPECIAL: SPECIAL: A A F FOCUS OCUS O ON N C COPPER OPPER C-3 C-3 COVER COVER STORY STORY — — C COPPER OPPER IINTERCONNECT NTERCONNECT — — A AN N E ENABLING NABLING T TECHNOLOGY ECHNOLOGY FOR FOR F FUTURE UTURE S SCALING CALING C-8 C-8 IIMPROVING MPROVING COPPER COPPER P PROCESS ROCESS IINTEGRATION NTEGRATION U USING SING E-B E-BEAM EAM IINSPECTION NSPECTION

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The Role of E-Beam Inspection in a Production Environment E-Beam inspection addresses many of the challenges created by shrinking design rules, new materials and new processes.

10 Real-Time Classification Streamlines Yield Management Process Real-time defect classification removes nuisance defects, enabling a more intelligent sampling strategy for highresolution defect classification and time-to-results.

15 Wafer Inspection Technology Challenges for ULSI Manufacturing — Part II Manufacturers face an increasing challenge in maintaining the optimal mix of defect detection sensitivity, throughput and cost of ownership.

20 New CMP Challenges for Unpatterned Wafer Inspection at 130 nm Topography variations on unpatterned wafers necessitate a new inspection solution.

Metrology 22 Measuring Fab Overlay Programs Stepper overlay management effectiveness can be improved by expanding current measurements.

26 Diagnosing Processing Problems through Electrical Charge Characterization To optimize the front-end electrical test process, the right test parameters must be chosen and data analyzed quickly.

30 Profiling High Aspect Ratio Features for Post-Etch Metrology Reliable, non-destructive metrology methods are required to maintain control over the etch process.

Lithography 32 Perspective: What Shall We Work On Now? A broad array of technical challenges, accelerating roadmaps and competing technologies are creating issues for the mask industry.

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Interconnect image courtesy of UMC Group, © 1999 UMC Group. All Rights Reserved.

Cover

Cover image by Luie Lopez, Stephen Marley Productions

St or y

C-3 Copper Interconnect — An Enabling Technology for Future Scaling It is widely recognized that sub-0.25 µm device performance will be highly influenced by device interconnects. Optimal interconnect solutions must address the performance, density and reliability requirements of a particular product.

Analysis 34 Automatic Defect Sizing Gives Near-SEM Accuracy A new method for on-line sizing of defects improves yield prediction accuracy.

36 The Importance of Variable Wafer Tilt for Defect Classification Improvements in imaging and classification can be derived from a defect review tool allowing fully-variable tilting.

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Copper Interconnect — An Enabling Technology for Future Scaling Sub-0.25 µm device performance will be highly influenced by device interconnects. Optimal interconnect solutions must address performance, density and reliability requirements.

Improving Copper Process Integration Using E-Beam Inspection Automated e-beam inspection enables fabs to accurately capture new defects and increase yield learning in the transition to copper interconnects.

C-13 Preventing Cross-Contamination Caused by Copper Diffusion New techniques can help to prevent cross-contamination caused by copper diffusion.

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42 eS20 Automated E-Beam Inspection System HRP-240 ETCH Automated Surface Profilometer Amray 4300+ Defect Reduction Tool 8100XP-T E-Beam Metrology System 43 8100XP-ABS E-Beam Metrology System 365UV-HR High-NA UV Reticle Inspection System

C-20 Non-Contact Copper and Cobalt Detection for 0.18 µm Technology A series of experiments outlines the potential effects of trace contamination.

AITTFH In-line Patterned Wafer Inspection System for Thin Film Heads

C-26 CD SEM Measurement of Dual-Inlaid Copper Interconnect While copper deposition processes pose new challenges, they create an opportunity to collect previously unavailable information.

2139 In-line Patterned Wafer Inspection System

C-28 Increasing Learning Rate on Copper Processes Motorola has developed a novel statistical method to optimize inspection and sampling strategies.

Yield Management Solutions is published by KLA-Tencor Corporation. To receive Yield Management Solutions contact Corporate Communications at:

Sections

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Editorial: Collaboration: An Essential Technology

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Business News

KLA-Tencor Corporation 160 Rio Robles San Jose, CA 95134 Tel 408.875.4200 Fax 408.875.4144 www.kla-tencor.com

Leading KLA-Tencor into the 21st Centur y KLA-Tencor’s new management team is focused on building company success through understanding customer requirements and delivering yield management solutions.

For literature requests call: 800.450.5308

25 Q & A KLA-Tencor’s recently introduced process module control solution for copper interconnects.

33 KLA-Tencor Trade Show Calendar 40 Best of YMS

©1999 KLA-Tencor Corporation.

All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation.

Products in this document are identified by trademarks of their respective companies or organizations.

Defect Detection for the 21st Century.

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Editorial

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COLLABORATION:

An Essential Technology Negotiating the ever-changing terrain of the semiconductor industry, where lightningfast shifts in technology can eliminate the need for a process, material or method almost overnight, can seem more challenging than scaling the highest mountain peak. Even the most experienced climber would never challenge Mount Everest alone, without the right team and tools for support. So too, must semiconductor manufacturers and equipment makers put collaboration skills as well as leading edge technology in their tool boxes, working together to create and implement successful methods to scale the peaks of semiconductor technology cycles.

Throughout its history, the semiconductor equipment industry has existed in close lockstep with its customers. Indeed, the equipment industry found its genesis within the closely guarded R&D facilities of the semiconductor producers themselves. Despite the inevitable creation of an independent industry, equipment makers have always retained close ties to their roots. One might theorize that neither industry could have thrived without the stimulus, the challenge and the cooperation of the other. While at times this symbiotic relationship chafes us, we all clearly benefit from it.

Today more than ever, the need for close cooperation is evident. Rapid adoption of new methods and processes, such as copper interconnect, will require semiconductor and equipment companies to work together in assessing challenges and developing solutions.

Neither side has all the pieces to engineer a viable result. And the timeframe for reaching productivity has never been shorter.

Collaboration is not easy, but it remains an essential “technology” that the best companies have in their portfolio. Successful programs require that trust be earned and responsibility for results be assumed by both sides. The rewards can be tremendous. By sharing appropriate information and learning from each other, both sides of the semiconductor manufacturing and equipment equation can develop the expertise to scale this peak. And for now, that is our challenge . . . until the next peak rises in the distance.

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ED I T O R - I N- C H I E F Roberta Emerson M A N A G I N G ED I T O R Kevin Clover C O N T R I B U T I N G ED I T O R S Kern Beare Judy Dale Carol Johnson Kavitha Kannan Viet Pham E D I T O R I A L A S S I S TA N T Rolando Gonzalez A R T DI R E C T O R A N D P R O D U C T I O N MA N A G E R Shirley Short D E S I G N C O N S U LT A N T S Carlos Hueso Harry Wichmann C I R C U L AT I O N Cathy Correia

KLA-Tencor Worldwide C O R P O R AT E H E A D Q U A RT E R S

KLA-Tencor Corporation 160 Rio Robles San Jose, California 95134 408.875.4200 I N T E R N AT I O N A L O F F I C E S

KLA-Tencor France SARL Evry Cedex, France 011 33 16 936 6969 KLA-Tencor GmbH Munich, Germany 011 49 89 8902 170 KLA-Tencor (Israel) Corporation Migdal Ha’Emek, Israel 011 972 6 6449449 KLA-Tencor Japan Ltd. Yokohama, Japan 011 81 45 335 8200 KLA-Tencor Korea Inc. Seoul, Korea 011 822 41 50552 KLA-Tencor (Malaysia) Sdn. Bhd. Johor Bahru, Malaysia 011 607 557 1946 KLA-Tencor (Singapore) Pte. Ltd. Singapore 011 65 780 1088

Roberta Emerson Vice President, Corporate Communications

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KLA-Tencor Taiwan Branch Hsinchu, Taiwan 011 886 35 335163 KLA-Tencor Limited Wokingham, United Kingdom 011 44 118 936 5700

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Business News

Leading KLA-Tencor into the 21st Century This past July, KLA-Tencor announced key promotions within its executive management ranks: the appointment of Ken Schroeder to CEO and Gary Dickerson to COO. Ken Levy, formerly CEO has become the company’s chairman, replacing Jon Tompkins who has retired but will continue to serve on KLA-Tencor’s board. These transitions reflect a strategic succession plan developed to ensure optimal leadership for the company in the coming years. Levy noted, “As we continue to grow and expand in keeping with our customers’ changing needs, we are also working to evolve our organization and develop the leaders of the future.” By promoting Schroeder and Dickerson, two longtime company veterans, the company has begun a transition to the next generation of management that will ensure smooth execution of the company’s established strategic direction.

Delivering value Schroeder believes in taking a strong customer-value approach in developing and prioritizing corporate goals.

“It is our job to understand our customers’ challenges and to deliver the yield management and process control solutions they need to be successful,” he stated. “Our customers must implement accelerated technology roadmaps to remain competitive in today’s global market. In such a fastpaced environment, defect reduction and process control strategies become critical enablers. By facilitating the development and production ramp of new technologies, we can help speed time-to-market and increase fab profitability.”

moving the company towards its goals. Schroeder first joined KLA in 1979 as vice president of operations.

After leaving in 1987 to pursue other interests, he returned in 1991 as president and COO, and has played a vital role in the company’s growth from $150 million to more than $1 billion in revenues.

Ken Schroeder, CEO.

Over the past few years, Schroeder has led his team in putting in place engineering, marketing and customer support strategies to foster close customer relationships and enhance rapid technological development.

He has placed particular emphasis on cross-company synergies — pushing to combine the company’s hardware, software and expertise into process module control (PMC) solutions tailored to customers’ needs in critical areas such as copper interconnect. As CEO, Schroeder will continue working with KLA-Tencor teams to build on these strengths, as well as seeking new opportunities for growth.

Dickerson has served in a variety of management roles during his 13 years with the company. He ran KLA-Tencor’s single largest division — wafer inspection — and oversaw the formation of the yield management group which united sales, technical support and consulting services.

Together with their management team, many of whom are also long-standing employees, Schroeder and Dickerson bring to the company’s leadership a pow- Gary Dickerson, COO. erful combination of long-term perspective, dedication to the customer and vital new energy — all essential assets for KLA-Tencor in the 21st century.

Long-term perspective Both Schroeder and Dickerson have been instrumental in developing the company’s strengths and strategic direction. Their insights and perspectives, acquired over their long tenures at KLA-Tencor, will be invaluable in Autumn 1999

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The Role of E-Beam Inspection in a Production Environment

by Jeff Hamilton, Senior Product Marketing Manager

The process and yield challenges that face today’s device manufacturers are increasing dramatically. The combination of new materials such as copper, low-k and DUV resists, new processes such as dual damascene, and rapidly shrinking design rules necessitate solutions that detect and identify all defect mechanisms. With manufacturers moving from traditional alu minum processing to dual damascene, defect mechanisms will switch from surface-related defects to defects within metal fills and high aspect ratio structures. In addition, design rule shrinks below 0.18 µm will require the detection of defects down to below 50 percent of the minimum design rule. Further, the accelerated development cycles of today plus the requirements for high yields at process transfer and higher yield ramps significantly compound the challenge.

The nature of defects is changing as customers develop processes with design rules less than 0.18 µm. As a result, new materials and fabrication techniques are being introduced at an unprecedented rate. Defects associated with high aspect ratio lithography and etch, as well as high aspect ratio fills will predominate in these new processing schemes (such as copper dual damascene).

With each progression in device generation, the increased aspect ratios of damascene structures and the variety of new materials place a larger burden on etch and fill processes. Specific detection needs include:

conventional optical inspections. Defects such as voids within metals (copper, tungsten, aluminum), residues at the bottom of contact/via holes and poor silicide formation cause electrical signatures that can be easily detected with this method.

3. High depth of focus imaging: A high depth of focus is needed that allows for the detection of physical defects (residues, particles, etc) within vias and trenches that cause failures and/or reliability issues.

Electron-beam inspection effectively addresses these needs. In order to reliably detect all yield limiting defects, customers must now develop strategies that utilize both optical and e-beam inspection solutions.

1. High resolution imaging: Sensitivities below 100 nm are needed that can detect very small residues and stringers at the bottom of high aspect ratio structures (vias and trenches), as well as very small surface defects.

2. Voltage contrast imaging: Due to the nature of “hidden” defects, voltage contrast imaging offers a quick method to identify these defect types. The interaction between electrons and specific defect mechanisms enable this imaging capability to detect the “hidden” defects that cause electrical yield failures and/or reliability issues. Detection of these defects within the process is critical since these defects are undetectable through 6

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F i g u re 1. “Hig h a spect ratio” a nd “hig h resol ution, high depth of f ield ” via/trench i nspecti on technolo gy is re q u i r ed (i.e., e-beam) to iden tify defects in the ppb level in today ’s new fabr ication pro c e s s e s .

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bridging, stringers, particles, corrosion, extra/missing pattern

opens, shorts, voids, resistance issues, organic residues, extra/missing pattern

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polymer residues, CD variations, particles,

missing, under-etch, residues, resistance issues

Tungsten Plugs

coring, residual W, particles, CMP scores, filled scores, slurry

voids, stringers, coring missing plugs, stress breaks

Damascene Trench/Fill/CMP

bridging, stringers, particles, µscratches, CMP scores, slurry

missing, under-etch, residues, resistance issues, voids, stress breaks, liner voids

Polys

polymer residues, stringers, extra/missing pattern

opens/breaks, shorts, resistance issues, organic residues

Capacitors

polymer residues, bridging, stringers

capacitor shorts, cell contact opens

F i g u re 2. Yield issues detected using e-beam technol ogy.

Early adopters of e-beam inspection technology were motivated by the need to rapidly increase learning cycles in process development and get their product to market, so that they could obtain initial high margins and capture market share. As these processes were introduced into high volume production, the need to monitor certain critical layers became apparent.

Knowing that the narrow process windows were inherent in some of these process layers and that the conventional methods to identify these defects (electrical tests and end of line yield) created a large window of product at risk, these early adopters implemented a “line auditing” scheme — sampling a few wafers per day on key critical layers. Although not true line monitoring, the “auditing” scheme served to minimize risk of critical layer yield excursions on their most advanced processes.

F i g u r e 3. Impact of comb ined e-beam a nd optical line monit oring strategy on yi eld learn i n g .

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Examples

With new defect types and shrinking design rules, a line monitoring solution is needed for these critical layers in advanced production fabs. To meet these needs, KLA-Tencor has introduced an e-beam line monitoring solution, the eS20. With this technology, significant increases in inspection speed have been obtained, up to 75 times over current inspections on many critical layers. As a result, this new e-beam inspection capability provides the vital link that IC manufacturers need to develop comprehensive in-line monitoring strategies that leverage both e-beam and optical inspection technologies— enabling the detection of all critical defect types at all critical layers at the high speeds needed for true production monitoring. Optical systems alone are not enough, nor are e-beam systems alone. However, together they represent a powerful and unique combination for meeting the development and production challenges of today’s IC manufacturing. Through effective sample planning and judicious use of e-beam inspection with optical methods, risk due to yield excursions of these new process technologies can be minimized and an optimum use of inspection tools can be developed. A high return on investment can then be realized by minimizing the effects of yield excursions in these advanced high volume production fabs. ❈ circle RS#029

F i g u re 4. Optimized sa mpling stra teg ies provide high ROI.

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ONE LOOK

eS20 detection of copper void in dual damascene process.

ALREADY THERE.

Given today’s shrinking design rules and new copper technologies, optical inspection alone is no longer enough. Fortunately, our new eS20 fills the gap. Orders of magnitude faster than competitive systems, it’s the industry’s first e-beam inspection tool truly designed for in-line monitoring. And the first to be optimized for use in full-volume production. The eS20 captures today’s most difficult to detect defects. Including sub-design rule particle and patterning defects.

Defects in very high aspect ratio structures. And electrical defects, such as voids and shorts.

INTO OUR IN-LINE E-BEAM INSPECTION SYSTEM WILL REALLY OPEN YOUR EYES. To further enhance productivity, our proprietary Sample Planner™ software – one of our solutions engineering services – creates and optimizes a fab-wide inspection strategy to help you identify the ideal combination of e-beam and optical inspection.

Ensuring the detection of the full spectrum of yield killing defects at all critical layers at the high speeds needed for true production monitoring. All of which serves to increase yield, reduce time to market, and make our eS20 worthy of a good long look. Call us at 1-800-450-5308 or visit us at www.kla-tencor.com/eS20 for more information.

©1999 KLA-Tencor Corporation.

Sample Planner is a trademark of KLA-Tencor Corporation.

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Real-Time Classification Streamlines Yield Management Process

by Rebecca Howland Pinto, Ph.D., Director of Marketing, WIN Division

The introduction of automatic defect classification (ADC)1 may have been the most important advance in yield management in recent years. When ADC was first introduced on off-line review stations, customers indicated that ADC provided more reproducible results more quickly and less expensively than using technicians to classify defects. When ADC software and hardware were moved on to the inspection platform itself, utilizing the integrated optical review microscope, the time to classification was improved again — the cassette of wafers did not have to be transferred across the bay to a separate review microscope, where it might wait in the queue for an hour or more.

KLA-Tencor is now refining the concept of automatic defect classification even farther.

With the ongoing goal to reduce the time required to classify all defects on the wafer, KLA-Tencor has put in place the ability to make a first-pass classification as the wafer is being inspected. Those defects sorted into the nuisance class require no further investigation. They can be removed from the process control charts, cleaning up and purifying the signature of process excursions.

Defects in the killer classes may be passed on to the high-resolution ADC subsystem described above — if high-resolution classification is even necessary. During the highresolution ADC step, the sampling strategy can now be more intelligent: instead of choosing a manageable number of defects randomly from an unsorted defect set, the samples can be chosen from the defects of interest. Potentially all of the defects of interest can now be classified in a reasonable amount of time. Finally, a small number of defects may pass to SEM review after high resolution ADC. Only at this last step do the wafers leave the inspection platform.

The first step of the streamlined process is called real-time classification (RTC). Real-time classification utilizes data collected during the inspection by the inspector’s sensors and 10

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optics to extract descriptors used to separate the defects into coarse classes. Because the defects detected do not need to be re-detected and re-imaged, RTC maintains the throughput entitlement of the inspection system. In contrast, high resolution ADC (HRDC) utilizes data collected after inspection from the inspector’s built-in review microscope (or an off-line review station).

Characteristics from the high-resolution images used for HRDC are used to separate defects into more specific classes. Figure 1 shows the dramatic time savings accomplished by using this multi-step process.

F i g u re 1. Real-Time Cla ssifica tion is pa rt of the ADC pathway, re d u cin g the numb er of defects requir ing HRDC. The first f our actions take place wit h no discern ibl e effe ct o n t hro u g h p u t .

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provide accurate classification of most defects into preliminary classes that are acceptably pure. (See definitions of accuracy and purity in the sidebar.) In fact, an ideal RTC package would be as close as possible to HRDC in performance. Furthermore, this performance should be achieved without noticeable impact on the inspector throughput.

F i g u r e 2. RTC can enable sensitivity to be increased at the ins pector recipe level in some ca ses, because f als e/nuisance defects are kept un der contro l .

How RTC provides value

As described above, real-time classification enables a more intelligent sampling strategy for high-resolution defect classification. RTC also provides value by immediately removing nuisance defects — defects not of interest because they are believed to have no effect on yield.

Once RTC separates defects into preliminary classes, statistical process control (SPC) algorithms can be used to monitor defect excursions by type. Monitoring defect count for each important yield-limiting defect type has been shown to be much more effective than monitoring total defect count. 2 Excursions of a particular defect type can be lost completely when only total defect count is trended. Such trending can help detect “hidden excursions” and provide a basis for baseline reduction efforts.

Another way RTC provides value is by maintaining the sensitivity entitlement of the inspection system.

“Hotter” recipes are possible when nuisance events are eliminated during scan time. In the absence of RTC, a fab engineer often reduces the sensitivity of a recipe so that it captures most of the defects of interest while at the same time limiting capture of nuisance defects.

Because RTC can be very effective at screening out nuisance defects, RTC may allow the engineer to increase the sensitivity of a recipe to capture more defects of interest (figure 2).

Components of a good RTC package

Several capabilities are considered crucial in the design of a leading-edge real-time classification package. First, performance is paramount — an RTC package should

An ideal RTC package should be easy to set up and use.

The number of classes into which defects can be sorted should be flexible (while maintaining acceptable computation time) and should be customizable by recipe.

The ability to specify classes according to process layer is necessary to achieve high performance across different layers. For example, users can separate “color” as a nuisance defect on a CMP layer while independently separating “grain” as a nuisance defect on a metal layer.

Characterization studies have shown that classificaOutputs of RTC — tion based on pre-set Accuracy and Purity classes common for all As with HRDC, the success of layers does not provide the RTC on a given defect set is desired yield management measured by the accuracy and performance. With the purity of the results. The defi ongoing introduction of nitions used for RTC are new processes and materitaken from definitions intro als in IC manufacturing, duced by HRDC. For a given the ability to customize class: the classification system • Accuracy is the ratio of the for new defect types is number of defects classified critical.

The relationship of RTC to the rest of the ADC pathway should be well designed. In RTC, the defect signal during inspection is parameterized and used for sorting; this information is of further use if the defect is classified later by HRDC. For this reason, a “feed forward” information pathway is part of the design of an efficient RTC-HRDC process. By the same token, information provided by HRDC can be used during RTC setup. A “feed back” information pathway is also part of an effective ADC process.

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correctly by RTC (where cor rectly means in agreement with a human expert) to the number of defects put into the class by the human expert. In other words, accuracy mea sures agreement between the RTC system and a human expert.

• Purity is the ratio of the number of defects classified correctly by RTC (same numerator as accuracy) to the number of defects put into the class by the RTC system. In other words, purity indicates the number of correct calls made by RTC as a percent of defects sorted into a given class.

Figure 3 illustrates the con cepts of accuracy and purity for a simple case.

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Defect s classified as residues by RT C but found t o be scratches by huma n expert

Defects classifi ed as residues by human expert

Defects classified as residues by RTC and human expert

Defect s class ified as residues

by RTC

Accura cy = 70/100 = 70% Purity = 70/80 = 82.5%

F i g u re 3. Definitions of accuracy a nd purit y.

Finally, inspector sensitivity is of critical importance in any kind of defect classification. You cannot classify defects that are not detected. In essence, real-time classification is only as good as the quality of the information from the inspector. RTC cannot be used to compensate for a fundamental lack of sensitivity to defect types.

The issue of inspector sensitivity shows up in the signal-to-noise ratio of the defect. Defects too small or too low in contrast to be detected with strong signalto-noise by an optical inspection system will not be classified well using optical RTC or optical HRDC. These defects may be detected better with a SEMbased inspection system such as KLA-Tencor’s eS20, and would likewise be classified more accurately using SEM ADC, as found on KLA-Tencor’s 4300+.

In accordance with the strategy described above, KLA-Tencor has designed RTC packages for darkfield (AIT) and brightfield (2xxx) product lines. These products not only provide highest performance, but also minimize impact on inspection time, with straightforward user interfaces, configurable classes, automatic figure of merit generation, and the ability to exchange information with HRDC. Examples of results from these systems are described in the following section.

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RTC on brightfield and darkfield inspectors

Recall that the main difference between RTC and HRDC is that, while HRDC uses higher resolution information gained after the inspection from an automated, often integrated, review microscope, RTC Real-time equals utilizes only the informareal value tion collected during an inspection. Thus HRDC In today’s market products images would be similar that claim to do real-time on a brightfield inspector defect classification go by (like a 2xxx) and a darkmany names. In-line, onfield inspector (like an the-fly, run-time and noAIT), since both utilize overhead are phrases that brightfield optical review often comprise the first part microscopes. However, it of the term. The phrases are is important to note that meant to convey that the the defect signals captured classification process has lit on a brightfield inspectle or no impact on inspector tion system are qualitathroughput. There are two tively and quantitatively ways in which a real-time different from the signals classification process can add captured on a darkfield literally no time to the system. Therefore RTC inspection: employing a sepa on a brightfield system is rate, parallel microprocessor working with substanor utilizing idle time for the tially different informasingle microprocessor, perhaps tion from RTC on a darkwhen a mechanical motion is field system. taking place in the absence of The defect signals generated by a brightfield system are very similar to images captured by optical review microscopes — which are generally used in brightfield mode. The difference is mostly one of resolution.

KLA-Tencor’s darkfield inspection systems are designed for high throughput to meet the low cost of ownership requirements for process tool monitoring.

Parameterization of the defect signals from these tools is inherently less

data collection. Especially because inspector throughput has received so much atten tion in today’s equipment design, such idle time can be difficult to find. Efficient algorithms are essential to RTC. Utilizing fixed defect classes and descriptors would be an additional time saver, but its price is high. Defect classification would not be as accurate and pure on all layers; correlation to yield killers specific to a process layer would not be as high, and performance of the yield management system would suffer. KLA-Tencor elected to forego fixed classes in favor of higher performance with its RTC solution.

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S u rf a c e P a rt i c l e

Residual S l u rr y

P re v i o u s Layer µscratch

P revio us Layer µscratch ( A rr a y )

S u rf a c eP re v i o u s

P re v i o u s Layer Par t i c l e

TEOS W Poly Sio2

W Poly

P re v i o u s CM P Step

F i g u r e 4. Cur ren t layer and previous layer defect s on an oxid e CMP l a y e r, for a 0.25 µm design rule device.

complex. The defect attributes are used to group and separate nuisance defects from defects of interest while also allowing sorting into multiple, user-configurable classes.

Recent results using RTC

Case 1: Using RTC as an effective previous-layer defect filter on the AIT platform A simple but highly effective use of RTC came to light recently when a customer of KLA-Tencor wanted to separate current-layer defects from previous-layer defects on an oxide CMP layer, for a device having a 0.25 µm design rule. The customer was interested in only the current-layer defects, including microscratches, slurry and rip-out defects (figure 4). The difficulty was that the defects of interest were in the minority; the transparent TEOS film was allowing numerous previous layer defects to be detected. The AIT II’s optical design helped to minimize capture of previous layer defects: oblique incidence minimizes penetration of the beam below the surface (since reflectance increases at oblique angles), and oblique detection minimizes collection of the sub-surface defects that do manage to scatter significant light. Even so, a large number of previous-layer defects were showing up on the wafer map.

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and purity of the surface-layer class was 79 percent.

Most importantly, RTC enabled the AIT II to run a “hot” recipe to capture the small population of surface defects within the large population of previous-layer defects. Previous to RTC, less than 3 percent of the total defects on the wafer map were of interest; after RTC, 95 percent of the defects identified as surfacelayer were key to the subsequent investigation into the source of the defects.

Case 2: Using RTC to classify defects that touch metal lines on the AIT platform A less simplistic use of RTC on the AIT platform was shown when RTC was used to identify defects that touch metal lines on a Metal 6 post-etch inspection.

The AIT II detected 1722 defects. The object of the RTC exercise was twofold: first to remove nuisance defects arising from metal grain, and second to separate the defects touching metal lines from other non-nuisance defects. After the metal-grain nuisance defects were removed, the remaining defects that touched metal lines were discovered to group together on a two-dimensional feature plot (figure 6).

Defining the non-nuisance classes using this methodology resulted in very successful separation of the defects of interest. After 55 metal-grain nuisance defects were removed from consideration, RTC classified 51 of the remaining 1667 defects as touching metal lines. When these defects were reviewed, accuracy for this class was 78 percent and purity was 84 percent.

RTC was used simply to divide the defects into two classes using these attributes, as shown in figure 5.

This very fast and simple version of RTC was nonetheless extremely effective.

More than 3000 defects were captured on the wafer by the AIT II, with RTC identifying 69 as surface-layer.

Manual review by an expert identified 73 as surface layer and the rest as previous-layer. Thus, accuracy on identification of surface-layer defects was 95 percent,

F i g u re 5. RTC on the AIT platf orm successfully separa ted pr e v i o u s la yer (nuisance) from current-layer defects. Before RTC, less than 3 percen t of d efects were of interest (73 curr ent l ayer out of 3000 total). After RTC, 95 percent of defects are of interest — RT C class ifi ed 6 9 of 73 corre c t l y.

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F i g u re 6. Sep arat ing defects t hat touch metal lines on a M6 post-etch layer using RTC on the AIT platfo rm .

Case 3: Using RTC to find missing metal defects on the 2xxx platform RTC was the answer in another situation where the defects of interest were in the minority. A Metal 1 wafer inspected by the 2138 system was found to have 2671 defects — mostly nuisance defects arising from metal corrosion. In this case the fab was looking for “Missing Metal” defects, such as the one shown in figure 7.

Using 94 defects to train the RTC system, RTC employed 3 of a possible 36 descriptors to identify 972 defects as missing metal defects. When 771 of these defects were revisited for manual classification, it was found that RTC had correctly classified 763 of these defects, for an accuracy of over 98 percent.

F i g u re 7. Example of miss ing met al defect type wh ose population wa s over whelmed by n uisa nce, corrosion defect s. RTC on th e 2xxx p l a t f o rm found 9 72 of these d efects among over 2600 total defects.

What happens next?

The utility of RTC to extract defects of interest, permit more sensitive recipes on the inspection system, enable a more efficient sampling strategy for HRDC and reduce the number of defects that need manual classification is making RTC an object of much interest in leading-edge fabs. What’s next for RTC? The most likely extension is on the SEM inspection platform, as SEM inspection tools become more and more necessary for capturing small killer defects on devices with design rules of 0.15 µm or less. RTC capability is also predicted to expand as optical inspection systems continue to evolve — and as parallel processing becomes increasingly practical. ❈ circle RS#015

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1. For further reading on ADC: Breaux, L., Kolar, D., “Automatic Defect Classification for Effective Yield Management”, Solid State Technology, Vol. 39 No. 12, pp. 89-96 (1996).

2. See for example “Applications and Benefits of AIT/ADC Back-End-of-theLine Process Development and Tool Monitoring”, John Alvis, Andy Campbell, Sean Collins, Nancy Benavides, Michael Peterson (Motorola APRDL), David Price and Frank Fan (KLA-Tencor), Yield Management Seminar, SEMICON/ Southwest, October 1998. Another example is “Tracking the Performance of Photolithographic Processes with Excursion Monitoring,” Eric H. Bokelberg and Michael E. Pariseau (IBM Microelectronics), MICRO, Vol 16, No. 1, pp. 47-58 (1998).

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Wafer Inspection Technology Challenges for ULSI Manufacturing — Part II

by Stan Stokowski, Ph.D., Chief Scientist; Mehdi Vaez-Irvani, Ph.D., Principal Research Scientist

Continued pressure to increase the return-on investment for the semiconductor fabricator has made it critical for inspection systems to evolve from stand-alone “tools� that just find defects to being part of a more complete solution where detecting defects, classifying them, analyzing these results and recommending corrective actions are their functions. Part I of this article, published in the Spring issue of this magazine, discussed the challenges of detecting defects with differing scattering characteristics and the need for multiple technology wafer inspection solutions. Part II addresses system consid erations to meet the design shrink challenge and future needs and developments in wafer inspection technology.

System considerations

An inspection system obtains an image (electron or photon), then processes it to determine if a defect is present, classifies it according to some criteria, and finally passes the information on to a yield management system. Each of these steps may have certain limitations and we briefly describe some of the system considerations necessary to optimize the inspection strategy.

Ideally an inspection system should have high sensitivity, high throughput, and low cost of ownership (CoO). However, all these desired system characteristics are coupled and one must do trade-offs to achieve the optimum system.

The semiconductor industry is shrinking the area density of devices by 40 percent per year. The challenge for companies developing inspection systems is to maintain image acquisition time and CoO constant while moving to higher and higher image resolution. We consider how image acquisition, image processing, and defect classification might meet this challenge.

Obtaining the Image Image acquisition is the first step in the inspection process. It consists of illuminating the wafer with a source (lamp or laser), imaging or collecting the scattered light, and detecting this light with a photodetector (PMT, TDI, or CCD). The source has to be bright enough to provide sufficient photo-electrons from the detector to obtain a reasonable signal-to-noise Autumn 1999

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ratio (S/N). In the case of unpatterned wafers, S/N should be about 8 to 10 for 95 percent capture probability and one false count per 200 mm wafer.

While brightfield systems usually use a high-pressure mercury (mercury-argon) arc lamp, darkfield systems use lasers. The recent development of reliable solidstate, diode-pumped lasers with greater than 1-watt power has provided inspection systems with sufficient power for most inspection tasks.

Image acquisition by existing inspection systems fall into one of two main categories: imaging systems or scanner systems. In imaging systems the source optics illuminate the area to be inspected, which is then imaged by microscope optics on to a TDI or CCD camera. In a scanning system a focused laser beam “paints� the inspected area and a single element detector (usually a PMT) detects the collected scattered light.

These two types of systems have their own advantages.

An imager is basically a fast optical microscope; thus, the optical system design is straightforward. A TDI or CCD camera obtains the image elements in a parallel fashion.

A scanner-type system has no constraints on the angles over which one collects the scattered light because it is a non-imaging system. It obtains the image in a serial fashion. An imaging system is useable in a brightfield or single darkfield configuration, but not with double darkfield. A scanner can have all three configurations; however its disadvantage is the high speed required for the scanner, the detector and its electronics.

It may be relevant to describe the relationship between various terms commonly used in inspection systems, such as pixel size, spot size, and system spot size. In a camera-based system, pixel size, as referenced to the wafer surface, is the detector element size divided by the magnification of the collection optics from the wafer to the detector. Note that this definition has nothing to do with the resolution of the objective lens.

In a scanner system, the focused Gaussian spot size is the full width between the e-2 points. In this case, the resolution of the focusing optics determines the spot size. For these systems the pixel size is the spot size divided by the number of electronic samples per e-2 width.

The sensitivity of an inspection system is related to the system spot size, which includes the resolution (or modulation transfer function) of the optics, the detector element size, the front-end electronic bandwidth, and 16

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convolutions done after digitization. In addition, noise limits sensitivity; noise sources include photo-electron shot-noise, detector noise, electronic noise, noise from the analog-to-digital converter, aliasing noise, and spatial quantitization noise. These last two noise sources depend on the spatial sampling frequency relative to the system spot size. Generally one increases sensitivity by decreasing the system spot size.

Note that system spot size is a governing factor in sensitivity, not pixel size.Throughput of an inspection system, on the other hand, is inversely related to the square of the pixel size. Thus, the time for actually inspecting the wafer is determined by the pixel rate of an inspection system, given its pixel size. Additional factors affecting throughput are operations such as wafer loading and unloading, alignment and registration, and data processing.

Figure 1 shows the relationship between pixel size and inspection time for different pixel rates. Clearly, one tries to use as large a pixel as one can while achieving a given sensitivity. Here is where darkfield systems have a great advantage over brightfield systems; the ratio of system spot size to defect size is considerably greater than 1 in darkfield systems, whereas brightfield systems have a ratio closer to 1. For example, albeit, a particularly advantageous situation, a darkfield system exists that can detect small PSL spheres on bare silicon with a defect-to-spot area ratio of 3 x 105.

The detector or scanner is limited in speed. For imaging systems, the fastest ones employ TDI detectors with 400-600 Mpps. The fastest scanners use AOD technology, currently running at an equivalent pixel rate of about 50 Mpps. However, the slower pixel rate in a scanning system is more than compensated by the larger defect-to-pixel size ratio in a darkfield configuration.

Processing the Image After obtaining the image, the image processor has to determine the presence of a defect and accomplish this function at a rate almost as large as that for the frontend detection. In a simple unpatterned wafer inspection system a simple threshold scheme works well.

However, die-to-die and/or cell-to-cell comparisons are required for patterned wafers.

For DRAM chips with their highly periodic structures, some inspection systems use optical spatial filtering to eliminate the light scattered from the periodic structure before it reaches the detector. Thus, only light scattered by the non-periodic defects is detected. This technique

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M i n i mum scan time (minutes for 200 mm wafer) F i g u re 1. Actual inspection time ( no over head) fo r a 200 mm wafer as a function of pi xel size, wi th pixel r ate ( Mpps ) as a pa rameter.

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The speed and cost of the image processor for patterned wafer inspection is critical. Fortunately, inspection systems can leverage off the improvements in the microprocessor industry. In a sense, benefits can be derived from developments in the industry that is being supported. Computer speeds have improved by approximately 30 percent per year over the last three decades1 and the cost per MIP has fallen by approximately 65 percent per year. However, the semiconductor manufacturing industry is increasing the area density of IC devices by 40 percent per year. Thus, the time it takes for doing the image processing of a wafer should remain approximately constant, even as the required pixel rate needs to increase by 40 percent per year to maintain throughput. Processing cost should also fall, except for the fact that processing is becoming more complex (more MIPS!).

Points indica te ran ge of some exi sting systems.

Classifying Defects only works with coherent laser illumination. Optical filtering typically lowers the background scattering from the array by 100 times or greater.

In the early days of wafer inspection systems, classification consisted of simply classifying and reporting a defect size. High resolution, brightfield systems could

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resolve the defect and determine its area. Because darkfield systems detected defects much smaller than the system spot size, they measured only the scattering light signal in a single channel. Defect sizing came from comparing this signal against a calibration curve for PSL spheres on the substrate.

For extended defects, post-processing algorithms in current systems can classify clusters, scratches, and random defects. For defects smaller than the scanner spot size or the imager optical resolution, however, real time classification requires multiple views or channels. As described in Part I of this article, multiple angles of incidence or multiple collection channels can provide superior classification capability. However, all this comes at a price because each channel needs support, particularly in image processing.

Current gap in inspection

Inspecting contacts and vias or high aspect ratio structures represents a gap in the performance of current wafer inspection systems.

Inspecting contacts and vias: Both optical and SEM inspectors are effective in helping to develop and control IC manufacturing processes.

However, there is one major gap in the performance of current systems— the ability to see small defects or residue at the bottom of high aspect ratio structures.

Optically one can detect partially filled or missing contacts in highresolution systems. However, if a residue of 5 nm is at the bottom of a 250 nm diameter by 1000 nm deep via, we are requiring a capability that is difficult for optical systems (for example, ability to detect a volume difference equiva18

lent to a 75 nm diameter sphere at the bottom of the hole2). Thus, if contact/vias must be checked individually, we are not going to do it optically on real wafers. However, if all the contact/vias within a local area are incompletely etched, then optical means can detect it.

In a SEM system a voltage contrast mode can detect a residue at the bottom of a via or contact. However, SEM inspectors are not fast; thus, to inspect contacts/vias in a reasonable time, we must resort to sampling small areas. Therefore, as with optical techniques, here we can observe incomplete etching if this fraction is on the order of roughly 10-4, but finding 5 nm of residue in one contact/via out of 10 10 of them is beyond practical consideration.

Future needs and developments

Smaller critical dimensions, larger wafers and more integrated inspection systems are part of our future.

Inspection systems will follow the lead of lithography and migrate to ultraviolet wavelengths. We will also see an even closer coupling of inspection with process equipment, review stations, and yield management systems.

Using UV in inspection systems: For detecting smaller defects, brightfield systems need the higher resolution of shorter wavelengths.

However, in darkfield systems the system spot sizes currently employed are not limited by the visible wavelength. Thus, it is not imperative that these systems use UV immediately.

In darkfield systems, the shorter wavelength of a UV laser leads to a greater scattering cross-section from particles on bare silicon

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surfaces. That is clear from the Rayleigh “blue sky” factor of λ-4. Therefore, UV systems will be able to detect particles in the range of 20 nm diameter on smooth surfaces.

In terms of patterned wafers, however, using UV has the following issues. In darkfield scattering mode operations, one ultimately relies on the phase associated with the interaction of light with the structures. Patterned and unpatterned wafers with films on them will both see a more rapid thin-film effect fluctuation. Thus, process variations across the wafer will have a greater effect with UV illumination. It is therefore not obvious that one necessarily gains from detecting defects on dense structures where the amount of scattered power is not an issue. The shorter wavelength will result in the generation of more diffraction orders in the Fourier space to filter out. For larger cell sizes, this also means that the orders are closer together, causing difficulty in removing them. UV optics and lasers, of course, must be developed and available. For non-PMT detection, UV necessitates back-thinning of TDI/CCD detector arrays or coating them with a fluorescence. UV light also can cause photochemical deposition of air-borne contaminants on the optical surfaces, thus necessitating e.g. a constant nitrogen purge.

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Wafer inspection system performances have kept up with semiconductor manufacturing industry requirements. Both darkfield and brightfield systems continue to increase in sensitivity and throughput. To meet future needs these systems will go to higher resolution with faster image acquisition and processing. Real time classification will improve, with better coupling to review, data management, yield learning, and yield management. Ultraviolet wavelength systems will provide an additional increase in capability. ❈ For Part I of this article, visit our website at: www.kla-tencor.com/corpmag.

1. Brenner, A., Physics Today 49, 25 (1996).

2. Socha, Robert J., Neureuther, Andrew R., J. Vac. Sci Technol. B 15, 27182724 (1997)

This article is an adaptation of a paper presented at the 1998 International Conference on Characterization and Metrology for ULSI Technology, National Institute of Standards and Technology, Gaithersburg, MD. March 23-27, 1998.

These issues can be resolved, so UV systems will be available in the not too distant future.

Integrated inspection systems: Time-to-results is always an important driver in the industry. Thus, we will see more and more integration of inspection hardware units into an overall system that can find the defects, review them, and determine the source of the problem.

The industry has a great incentive to “shorten the loop”.

As a result there is considerable investigation into bringing metrology and inspection within the process chamber (“in-situ”) or into a port on the process equipment. However, both technical and economic barriers exist that make it difficult to accomplish this. High performance (sensitivity and throughput) inspection has engineering constraints that make compatibility with process equipment difficult. In addition, the cost of a metrology/inspection module has to be relatively low compared to present-day systems to make it cost-effective. On the other hand, we will see some development of integrated inspection units that are tuned to the specific defects generated by process tools and are sensitive to relatively large defects.

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New CMP Challenges for Unpatterned Wafer Inspection at 130 nm

by Hubert Altendorfer, Senior Product Marketing Manager; Lionel Kuhlmann, Senior Research Scientist; Henrik Nielsen, Senior Staff Electrical Engineer; and Mark Nokes, Principal System Design Engineer

Chemical Mechanical Polishing (CMP) has quickly become the standard planarization method in IC manufacturing.

However, for CMP to continue to mature and become a viable process for the 0.13 µm generation, it is important to look at some factors that may affect the CMP process such as variations in wafer surface topography. Currently, traditional wafer flatness criteria are used to manage the depth of focus budget in the lithography process. Additional flatness requirements are emerging, demanded by the use of CMP in the early stages of device manufacturing. Topography variations on unpatterned wafers in the nanometer range have shown to adversely affect post CMP uniformity of dielectrics. An automated, high-speed inspection solution is needed to control the wafer quality used for these devices. This paper will discuss how surface topology could affect IC devices and introduce a solution for such a future inspection step.

CMP and surface topography

Depositing a thin dielectric layer onto a wafer that exhibits surface topology variations results in a non-uniform film thickness after the CMP processing (figure 1). This non-uniformity leads to resistivity variations resulting in lower performance devices and eventually to a complete device failure.

Therefore, stringent control of starting material for these small topology variations has to be established. Traditional flatness tools neither have the spatial resolution or the vertical sensitivity to measure these features. A fairly sensitive piece of equipment that has been used thus far is known as the “Magic Mirror” revealing very small slope variations on the surface. While the Magic Mirror instantaneously produces an image of the full surface of the wafer, the results are seldom quantitative for magnitude and extent of a feature, which are critical parameters to assure that the wafers are within the specification limits.

The surface topology contains all the information of the deviations of a real surface from an ideal reference. The spatial frequency 20

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range detected by scattered light depends on the optical configuration and usually collects the signal of surface features with very high spatial frequency. Darkfield optics can collect high spatial frequencies but are insufficient for features that exhibit lower spatial frequency.

On the other hand, brightfield optics can detect the lower spatial frequencies required to characterize surface topology.

PreCMP

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F i g u re 1. Dielec tric film thick ness variation s a fter CMP due to sur f a c e t o p o l o g y.

A viable solution

The KLA-Tencor Surfscan SP1 platform, with its second-generation brightfield capability (SNT™ – Surface NanoTopography), can provide quantified results

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F i g u re 2. Sur fscan SP1 SN T h eight ma p.

F i g u r e 3. HRP-200 pro f i l e r.

of the wafer surface topography with nanometer height resolution at exceptionally high throughput. A critical item for success is to provide distortion free wafer handling during the measurement. Small forces at any part of the wafer will introduce artifacts to the measurement.

The SP1 incorporates a proprietary edge handling design that enables distortion-free wafer handling at all times.

The SP1 Surface NanoTopography design allows orientation-independent capture of large features. These features can be up to several millimeters with only a few nanometer height. Figures 2, 3 and 4 compare surface topography maps produced by the Surfscan SP1’s SNT feature to those from the HRP-200 profiler and a Magic Mirror, respectively. The results clearly show very good correlation with equivalent sensitivity for these long spatial wavelength defects on the Surfscan SP1.

Compared to the Magic Mirror, the Surfscan SP1 with SNT has the added benefit of quantifying the surface topology.

The quantifiable result from the Surfscan SP1 allows grading of the wafers based on user definable criteria.

The final result presents the number of defects above a specified height and total surface area covered by these defects.

Conclusion

It is essential that variations in wafer surface topology be detected as design rules move towards 130 nm.

This will require a broad range of spatial wavelengths extending from particles to surface site flatness. As mentioned earlier, detecting the different defect types requires the use of several methodologies. These have been combined in a single instrument, the Surfscan SP1.

The SP1 can rapidly and non-destructively inspect wafers up to 300 mm. It meets the challenge of reliably

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F i g u re 4. Magic Mirror im age.

detecting particles in the 60 nm range, can separate crystal originated pits (COPs) from particles and measure surface topology in the nanometer height range.

The Surfscan SP1 offers a comprehensive inspection strategy for CMP challenges at 130 nm design rules. ❈ circle RS#013

P a n e l

D i s c u s s i o n

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Panelists representing lithography, capital equipment sector, technology integration, CMP and process consumable segments of the industry will be present to lead the discussion. Companies represented include KLA-Tencor, Intel, Motorola, and other leading semiconductor manufacturers.

196th Meeting of The Electrochemical Society, Inc. Honolulu, Hawaii October 17-22, 1999 Hilton Hawaiian Village

For more details, visit www.electrochem.org/meetings.html

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Measuring Fab Overlay Programs

by Xuemei Chen, Senior Software Design Engineer and Rich Martin, Consultant

This article presents a methodology for measuring and improving the effectiveness of stepper overlay management on product wafers in the semiconductor industry. Measuring the effectiveness of stepper overlay management in most semicon ductor companies is generally limited to design rule compliance and/or stepper productivity issues. This paper expands on these measurements to include raw data distributions and analysis, sampling effectiveness and the level of stepper produc tivity and overlay error balance.

The research that supports the proposed measurement approach encompasses over 12 fabs with over 30 technologies. Overlay performance, stepper deployment, stepper productivity and die yield loss due to overlay error were studied. To provide an objective measurement of a fab overlay methodology and performance, measurements were made of the overall overlay design rule compliance and distribution and of the overlay variance and distribution by stepper field location. Modeled data analysis was used to assess and validate the effectiveness of the stepper control methodology, sampling level and field/target locations. Balancing stepper productivity and overlay results is a problem in most fabs. An overlay “opportunity box” is defined that allows a fab to explore overlay error ranges, lost stepper productivity, and product overlay design rule requirement by stepper deployment.

A “Fab Overlay Benchmark” database was established to provide a summary for technologies with design rules between 0.25 µm and 0.5 µm, as elaborated below.

Fab overlay benchmark database facts • 11 fabs – 7 U.S. and 4 international • 26 technologies: 0.25 µm to 0.5 µm • Calculations all done the same: - final DI raw overlay data (all test data removed) - KLASS analysis of overlay data - Overall overlay design rule compliance 22

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- field variance and robustness by stepper development - sampling: field/target locations and robustness • Stepper productivity and overlay balance studied - overlay vs. lost fab capacity vs. stepper development The poly gate process layer was selected because this layer is the most important process layer to compare fabs and it represents the “best” printed lithography layer for overlay and CDs for most fabs.

Fab overlay measurements

Four overlay measurements are introduced: Fab Overlay Snapshot, Overlay Field Variance, Modeled Data Analysis and Balancing Stepper Productivity and Overlay Error.

These measurements are highlighted in figures 1-3, and are summarized in the following sections.

Overlay Snapshot Fab Overlay Snapshot measures the overall design rule compliance and overlay distribution. A cumulative probability plot of the individual RMS target measurements provides a fast method to look at large amounts of raw overlay data. Once the design rule limit is added to the plot, the amount of final DI data that exceeds this limit can be quantified. In addition, the shape provides information about the normality of the data; the slope provides information about the width of the distribution — the steeper the slope, the tighter the distribution.

Logic fabs performed at a variance rate range of 5 to 10 percent, while memory fabs performed better with a

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formance were found to have similar and overlapping overlay distributions (shapes) that were independent of wafer field location and had small differences (spread) between field distributions at the 90th percentile. The “best” performing fabs had less than 10 nm difference at the 90th percentile.

Data Analysis Modeled Data Analysis assesses and validates the effectiveness of the stepper control methodology, sampling level and field/target locations. In this study, the KLASS 4.0 software1 was applied using the KLA-Tencor stepper specific model for all modeled data analysis. The combination of the raw and modeled data analysis provides a complete measurement of a fab’s overall overlay performance.

F i g u re 1. Fab overlay “snapshot”.

variance rate range of less that 2 percent. Due to the differences in the design densities and product requirements, logic fabs tend to be more focused on critical dimension control, while memory fabs tend to focus more on overlay control.

Field Variance and Robustness Overlay Field Variance measures the overlay variance and robustness by stepper field location. From a control and die yield perspective, a yield manager would like to see the same identical raw overlay distribution at any field location on any wafer. Fabs with good overlay per-

F i g u r e 3. Field variance and ro b u s t n e s s .

This study found that the better performing fabs regularly used large volume modeled data analysis (less than 50 lots on a single product) to make overall assessments and improvements to their stepper overlay management and performance.

Sampling Plans and Measurement Locations

F i g u r e 2. Bala ncing fab producti vi ty a nd overl ay.

One interesting part of this study was the comparison of different sampling plans and measurement locations against the resultant overlay performance results. Most fabs sampled 2 or 3 wafers per lot, selected 9 to 12 field locations per wafer, and measured 4 or 5 targets per field. The most important consideration was that the selected locations predict the overlay for the entire wafer Autumn 1999

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with a high level of confidence. On the other hand, as the overlay metrology cost of ownership is one of the lowest in a wafer fab (a “cost per wafer pass” of about $0.75), overlay is one of the lowest fab expense items. Besides, the “time to results” (measurement and analysis) to double the sampling size from 10 to 20 fields requires less than 2 additional minutes per wafer. Once a wafer is in an overlay metrology system, the fab should sample enough to make good decisions with the results.

Balancing Stepper Productivity and Overlay Error The Balancing Stepper Productivity and Overlay Error function measures the level of balance, compromise and opportunity of the fab overlay methodology, which represents one of the key fab financial decisions — lost fab capacity (stepper restrictions) verses overlay error (lost die yield). Stepper deployment options are plotted against the expected 3-sigma overlay errors and the approximated lost fab capacities. The expected stepper error ranges are calculated RMS values based on the stepper vendor specifications and deployment options.

The lost fab capacities are approximations using queuing curves2 based on difference deployment options. The accuracy of the queuing approximations for a given fab can be improved by comparing lot cycle times of layers with and without stepper deployment restrictions.

These cycle time results can then be used to provide a more custom lost fab capacity model for that particular fab. The addition of the product design rule to the plot defines an overlay “opportunity box”. This box was used to compare actual and expected (calculated) level of balance between stepper productivity and the 3-sigma overlay error range.

In the case of stepper deployment changes, it is important to understand die yield loss as a function of overlay error. ❈

Improvements”, Proceedings of 7th Annual IEEE/SEMI ASMC Conference, Cambridge, MA, 1996.

1. KLA-Tencor, KLASS 4.0 for Windows User Guide, P/N: 990-452376-00, San Jose, CA, 1996.

This article is based on the paper: R. Martin, X. Chen and I Goldberger, “Measuring Fab Overlay Programs”, Proceedings of SPIE, Vol. 3677, 1999.

2. L. Sattler, “Using Queueing Curve Approximations in a Fab to Determine Productivity

circle RS#038

4 out of 5 Perfectionists Insist On VLSI’s Thin Film Metrology Standards.

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The Measurement Standards for the Industry.

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S O L U T I O N S Yield Enhancement and Process Control Strategies for the Semiconductor Industry

SPECIAL: A FOCUS OCUS ON N COPPER OPPER

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Copper Interconnect — An Enabling Technology for Futur e Scaling Sub-0.25 µm device performance will be highly influenced by device interconnects. Optimal interconnect solutions must address performance, density and reliability requirements.

Improving Copper Process Integration Using E-Beam Inspection Automated e-beam inspection enables fabs to accurately capture new defects and increase yield learning in the transition to copper interconnects.

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C-13 Preventing Cross-Contamination Caused by Copper Diffusion New techniques can help to prevent cross-contamination caused by copper diffusion.

C-20 Non-Contact Copper and Cobalt Detection for 0.18 µm Technology A series of experiments outlines the potential effects of trace contamination.

C-26 CD SEM Measurement of Dual-Inlaid Copper Interconnect While copper deposition processes pose new challenges, they create an opportunity to collect previously unavailable information.

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C-28 Increasing Learning Rate on Copper Processes Motorola has developed a novel statistical method to optimize inspection and sampling strategies.

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Cover COPPER INTERCONNECT — AN ENABLING TECHNOLOGY FOR FUTURE SCALING

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by Arun K. Chatterjee, Senior Director, Interconnect Solutions

sub-0.25 µm technology will be highly influenced by device interconnects.1 Interconnect scaling is also a critical determinant for future increases in circuit density, especially for logic and microprocessor products. The interconnect solution for a given technology must address the performance, density and reliability requirements of a given product. In addition, as higher levels of interconnects for future logic and microprocessor products are needed (as shown in the figure 1), the interconnect strategy has to provide cost effective solutions for yield management and wafer manufacturing. In this paper we will review (1) material and process architecture considerations, (2) adoption and reliability of emerging interconnect technologies, and (3) the yield management considerations for sub-0.25 µm interconnect solutions.

Materials and device architecture

What is the sub-0.25 µm interconnect solution? Is it copper, low-k, or copper and low-k? While it may be debatable whether a lower resistance material (like copper) or lower-k inter-layer dielectric (ILD) is the best approach for 0.18 µm technologies, it is apparent that both higher-conductive material and lower-k ILD will be

Required Number of Interconnect Levels 14 Number of Metal Layers

is widely known that the perforI tmance of integrated circuits using

12 10 8 6 4 2 0 .09

.13 .18 .25 Technology Generation (µm) AI/Si02

AI/Low-k

Cu/Si02

.35 Cu/Low-k

Figure 1. Influence of material on number of metal interconnects.

required for sub-0.15 µm technologies. The path to implementing both lower-k and higher-conducting materials will depend on the product type and its design methodology. Table 1 provides an overview of this complex issue.

The columns reflect the technology generation, the rows represent various interconnect solutions. The k for low-k material is assumed to be 2.5.

The 0.35 µm technology with polycide gate, aluminum interconnect and standard SiO2 (k = 3.9) Relative Delay has been given a relative TECHNOLOGY TYPE 0.35µm 0.25µm 0.18µm 0.13µm 0.10µm delay value of 1. Any comPolycide gate + (AI & Si0 ) 1.00 1.08 1.31 2.04 3.19 bination whose value is Polycide gate + (AI & Low-k) 0.90 0.88 0.93 1.22 1.69 greater than 1 will result in Polycide gate + (Cu & Si0 ) 0.87 0.84 0.91 1.27 1.89 a slower product. Similarly, Polycide gate + (Cu & Low-k) 0.81 0.73 0.69 0.81 1.04 any combination that has a value lower than 1 will result in a Table 1a. Relative delay. faster product. Grouping the inter2

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Relative Delay 0.35µm 0.25µm 0.18µm 0.13µm 0.10µm

TECHNOLOGY TYPE Polycide gate + (AI & Si02)

0.85

0.92

1.19

1.96

Polycide gate + (AI & Low-k)

0.74

0.72

0.81

1.14

Polycide gate + (Cu & Si02 )

0.71

0.69

0.79

1.19

Polycide gate + (Cu & Low-k)

0.65

0.58

0.58

0.73

Table 1b. Relative delay

connect solutions with relative delay normalizes the effect of conductor thickness and length. While table 1a provides various alternatives, it is apparent that at 0.13 µm design rules both higher-conductive and lower-k materials are required.

of

mixed

design

rules

(transistor is one generation ahead of interconnect).

One can delay the implementation of copper and low-k materials by using mixed design rules. Smaller feature size requires SUBTRACTIVE

DAMASCENE

Ox Dep

M1 Cap Ox

M1 M1

M1

V1 M1

M1

M1

CMP (Ox)

M1

V1 M1

CMP (Ox)

V1 M1

W M1

CMP (Ox)

W M1

M2 V1 M1

M2 V1

M2 W M1

CMP (Ox)

M2 W M1

M2 V1 M1

M2 V1 M1

Major Process Steps=10

V1

M1

Major Process Steps=8

decreased metal pitch to effectively route signal lines by increasing available chandual-damascene process nels per cell. In contrast, increased metal flow. pitch improves the performance.

Therefore, keeping the interconnect design rules a generation behind that of the transistor can greatly improve product performance at the cost of product density (transistor/logic per unit area), when a given product is not limited by its bonding pad design.

The concept of Metal: Alumimum Metal: Al or Cu Metal: Copper ILD: k=3.9 ILD: k=3.9–3.0 ILD: k=3.0–2.0 .50 mixed design .40 rules is not new .30 Transition Phase — products .20 whose die sizes SIA Technology Roadmap are limited by the bonding pad .10 .08 density tend to .06 benefit from 1995 ‘96 ‘97 ‘98 ‘99 2000 ‘01 ‘02 ‘03 ‘04 ‘05 this approach.

Mixed design Figure 3. SIA roadmap rules also allow semiconductor manufacand interconnect adoption turers to effectively increase the life of trend. existing process tools and technology.

Minimum Feature (µ)

Figure 2. Subtractive vs.

However, table 1b suggests that for sub0.13 µm technology both copper and lowk material will be required.

In addition to changes in material for both conductor and inter/intra-level insulator materials, the architecture is also changing. Figure 2 shows the change in process architecture from subtractive aluminum to dual-damascene copper technology.

The dual damascene architecture not only reduces the processing steps by 20 percent, it also allows the manufacturing facility to use the current lithography tool set to scale the interconnect geometry. This is because printing and etching on an oxide insulator surface is easier than that on a reflective grainy metal surface. Therefore, the line width control and the continuity of smaller line-width for a damascene structure will be superior to that of a subtractive structure. As a result, the average product reliability for damascene metal will be higher than that for subtractive metal.

Copper and low-k ILD adoption trend

Figure 3 summarizes the present trend of interconnect solutions in general, especially for microprocessor and logic products. The X-axis represents the minimum feature size and the Y-axis represents the year of technology introduction to production per the latest SIA roadmap. It is interesting to note that both aluminum and copper will co-exist for 0.18 µm and 0.15 µm technologies. Hence, the industry will be in transition phase during these technology generations. For sub-0.15 µm technology, Active Energy METALLURGY

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REFERENCE

0.50

Books and Journals

Aluminum + 0.5% Cu doping

0.60

IBM J of R&D, VMIC Proceedings

Sputter Copper

0.80

IEDM Technical Digest, 1995, P253–256

0.65–0.85

IBM J of R&D, VMIC Proceedings

TiN/Ti/0.5% Cu doped Aluminum/Ti

Table 2. Activation energy of several interconnect material.

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ACTIVE ENERGY (eV)

Sputter Aluminum

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Metal Reservoir LARGE

MEDIUM

Metal 2

SMALL Metal 2

Metal 1 e

Table 3. Current carr ying capability for various reser voirs.

copper appears to be the dominant interconnect conducting material.

Reliability considerations

For a given operating temperature and current density the electromigration lifetime depends on both material and design factors. Copper, having a much higher activation energy, will significantly improve electromigration lifetime. Several studies2,3 suggest that for a given layout the current density required to prevent electromigration for copper could be as high as 5x106 A/cm2 compared to 2x105 A/cm2 for aluminum. However, one should keep in mind that electromigration can be increased by using refractory sandwich materials – such as, TiN/Ti/Al-Cu/Ti. However, refractory sandwich materials will increase the resistance of the conducting lines. Table 2 summarizes the current published activation energies for aluminum, copper, aluminum alloys and composite aluminum structures.

Electromigration lifetime is also a function of layout methodology for a given operation. Figure 4 shows that layout methodology can significantly increase the lifetime of a given conductor line. When the current flows towards the “A” direction, the electron will flow towards the “B” direction. Therefore, the metal reservoir will be either “small” or “medium” depending on the length of the narrower width metal line. However, if the direction of the current is reversed, the metal reservoir will be large, which will significantly increase the current carrying capability of the interconnect line. Table 3 summarizes the current

0.13µm

1X

0.25µm 0.18µm

Small

The major line monitoring and yield management challenges in the future are (1) high aspect ratio via and metal-trench with scaled geometry, (2) a new process architecture (dual damascene), (3) new materials (low-k for dielectric and copper for conductor), (4) contamination control (mainly from cobalt and copper) and (5) limited industry experience in copper dual damascene technology. In addition, technology transfer in the manufacturing ramp phase must be accomplished at higher yields for future technologies to Technology Generation remain ahead 10.0 6.0 of the com4.0 petitive curve.

2.0 Figure 5 provides the 1.0 0.6 trend in elec0.4 trical fault 0.2 density, Do, 0.1 with respect ‘80 2000 1975 ‘95 ‘90 ‘95 ‘05 YEAR IN VOLUME PRODUCTION to technology Best Practice Manufacturing migration for Memory Fabs Micro-P & Logic Fabs Logic & Memory Fabs best practice Figure 5. Electrical fault manufacturing.

0.35µm

7X 2–3X

0.50µm

Large Medium

Process control and yield management challenges

0.65µm

CURRENT-CARRYING CAPABILITY

carrying capability for different metal reservoirs.

1.0µm

METAL (Al or Cu) RESERVOIR

i

1.5µm

Figure 4. Layout methodology vs. electromigration.

Metal 1

2.0µm

e

VIA (W)

D0 ( /cm2)

Current Flow Direction A: Direction B: i

From figure 5, it is evident that, for best practice manufacturing, the fault density for 0.18 µm technology needs to be less than 0.18 per cm2. For 6- level metal technology, this translates into one defective via or contact per 3.6 billion contacts or vias.

To ensure proper line monitoring to meet this requirement, both physical and electrical on-line defect detection capabilities will be required. For on-line electrical defect detection, “non-contact” testing, e.g. voltage contrast techniques, will be needed.

Therefore, e-beam inspection technology will be very critical for future line monitoring of interconnect processing steps.

density (D o ) trend.

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M

SUBTRACTIVE (100% Crit Area)

M

CMP-Ox M

M

V CMP(Ox) V

DAMASCENE (30-40% Crit Area)

Ox Ox

Non-Killer Defects

Figure 6a. Killer vs. nonkiller defects.

M

Ox

SUBTRACTIVE (1-2% Crit Area)

M

V CMP(Ox) V

V CMP(Ox) V

M V

M V

Ox Ox

M V

M V

Ox Ox

the defect detection methodology should focus on detecting primarily the “killer” defect types. Not all defects are killers. While it may be of some use to develop a correlation between killer and non-killer defect type and distribution, it is essential that the initial focus be on detecting killer defects. For example, the defects inside the via-metal trench are more critical than the defects on the spaces between via-metal trench lines for dual damascene structures, as shown in figure 6a, where “M” represents the metal lines and “V” stands for vias.

Killer Defects

Similarly, embedded (or sub-surface) defects in ILD which were non-killer defects due to the advent of CMP technology will be killer defects as we etch metal trenches that account for 30-40 DAMASCENE percent of the die area as shown in figure 6b.

M

Ox

M

(30-40% Crit Area)

Non-Killer Defects

Figure 6b. Killer vs. nonkiller defects.

CMP-Ox M

M

Killer Defects

While e-beam technology is superior for detecting defects inside high aspect ratio “stacked” via and metal trench structures, optical inspection technology provides the most cost effective solution for embedded film defects. Therefore, future inspection strategies will require both e-beam and optical inspection tools. This in turn requires establishing a correlation between the two types of inspection technologies, based on advanced statistical models and methodologies.

Relative Defect Learning Rate

Yield Management Trends Advanced SPC Technolgy

Physical Defect Reduction Technology

Integrated YM Technology

5 PROCESS

4

MODULE CONTROL

3

SOLUTIONS

2 1 1985

1990

1995

2000

Figure 7. Defect learning rate vs. yield management methodology.

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Defect learning and process module control (PMC) solutions

The defect (electrical fault density) learning trend has been increasing steadily for the last 15 years4, as shown in figure 7.

Initially it was the adoption of SPC that helped the defect learning process. During the early 1990s, the learning process was significantly increased through the adoption of advanced defect detection technology and intelligent line monitoring methodologies. Further increases in defectivity learning have been accomplished by using advanced yield management technologies that effectively integrate defect and parametric measurement tools, analysis and review tools, and best practice yield management methodologies.

In recent years, however, it has been observed4 that both defect learning rate and defect learning cycles can be improved by controlling each process module and establishing a defect/parametric correlation between process modules — for example, CD variations with respect to film thickness variations, or void formation during copper electroplating with respect to “as deposited” barrier layer thickness for a given deposition condition. Comprehensive defect modeling with respect to process module parameters and defect source database, will enhance defect learning.

Process modules can be divided into four major categories: (1) Film (i.e, material formation phase that includes deposition, implant, diffusion, etc.), (2) Lithography (i.e., image formation phase that includes reticle, resist, and exposure technologies), (3) Etch (i.e., material removal using plasma chemistry) and (4) CMP (i.e., material removal through chemical-mechanical polishing).

For sub-0.25 µm technologies, the major source of particle type defectivity will be process induced5 as indicated in figure 8.

Therefore, defect learning from one process

C

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S

T

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R

Y

1. M.T. Bohr, IEDM Technical Digest, P241-244, 1995.

2. Y. Arita, Semiconductor World, P158, December 1993.

3. D.B. Knorr, Proc. MRS Spring Symp., P75, April 1995.

4. KLA-Tencor, Yield Management Consulting Database (unpublished), 1996-1999.

5. ICE, Midterm Status Report, 1996.

F i g u re 8. Trend of par ticle d efectivity sourc e .

module can be applied to another process module, shortening the learning cycle.

Summary

The combination of copper and low-k dielectric materials with dual damascene device architectures is the preferred interconnect solution for sub-0.15 µm technology. However, several manufacturing and yield management issues have to be optimized before we can realize the yield and cost benefits. The present key manufacturing and yield management issues are: (1) an optimized CMP solution for copper and barrier material, (2) optimized CMP selectivity of low-k dielectrics, (3) optimized void free copper electro-plating technology, (4) effective inspection technologies for high aspect ratio trenches, embedded film particles and sub-surface voids in the conductor lines, (5) intelligent correlation software and on-line electrical fault detection technology for each level of interconnect and (6) sufficient availability of experienced resources.

Timely solutions for some of the above manufacturing issues will require a closer partnership between the device manufacturers and equipment vendors. Since the major source of particle defectivity will be process induced for sub-0.25 µm technologies, a closer working relationsip between process-module equipment vendors and process-control equipment vendors will be needed to accelerate both yield learning and process module technology developments. ❈

Acknowledgements The author would like to thank the corporate marketing and yield management consulting groups for providing numerous helpful informa tion. Special thanks to Tom Long for many insightful discussions and Kern Beare for assisting in editing the manuscript.

About the Author Arun K. Chatterjee has an MS in Materials Science.

He has over 23 years of semiconductor technology and operations experience. He has held several management positions in CMOS and BiCMOS device development and process integration at Fairchild, Signetics, AMD, Data General, Synergy Semiconductor and Cirrus Logic. At Cirrus Logic, he also managed the advanced CMOS technology alliance with IBM and MiCRUS. In 1996, he joined KLA-Tencor’s Yield Management Consulting group and is currently Senior Director in Corporate Marketing focused on the company’s Interconnect Solutions strategy.

Contact Information KLA-Tencor 160 Rio Robles San Jose, CA. 95134 Tel 408.875.2372 Fax 408.875.4144 Email: arun.chatterjee@kla-tencor.com

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Improving Copper Process Integration Using E-Beam Inspection

by Patrick Dao, Staff Engineer, Motorola, APRDL This article is based on a transcription of a paper presented at the KLA-Tencor YMS seminar at SEMICON/WEST 1999.

It is generally well accepted in the industry that most of the large semiconductor houses currently use a 0.25 µm technology with aluminum metallization, perhaps one poly layer in the design, as well as up to about five layers of metal. Now, as the industry shifts into the 21st century, we’re seeing a big shift to higher layers of metal, and also designs that call for dual layer poly. But the biggest shift is from using aluminum interconnects to copper process technology.

This paradigm shift in the industry creates two different types of yield-limiting issues. The first issue has to do with the shift to dual inlaid copper technology. It is generally well known that copper technology introduces many unique copper defect types. From a yield enhancement standpoint, the number one question is whether we can discriminate the killer versus non-killer defect types that are scanned and detected in-line. As we increase the number of interconnect layers, one can clearly see that the device becomes a smaller portion of the overall process flow. So the emphasis then shifts from the front end to the interconnect yield in the back end. As Motorola exhibits leadership technology in copper processing, we realize that by improving our yield learning cycles, we can definitely bring more products to market in plain copper-based technology. Thus, we require an in-line failure analysis technique in order to accelerate our yield learning.

This article highlights how an automated e-beam inspection tool can catch both surface-related defects and embedded C-8

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defects within the via processing or the metal trench processing. For this example, we used a KLA-Tencor SEMSpec 2702 with random mode, which offers simultaneous physical and electrical in-line detection, with physical defect resolution down to 0.1 µm. Through voltage contrast imaging, we can catch electrical defects very readily. It has both a random and array mode capability. Random mode offers detect defection on a day-to-day basis, which serves many applications in our logic and DSP devices. The array mode offers defect detection on a cell-tocell basis, which we primarily use in our memory products.

It is fairly well known that copper introduces many unique defect types, which raises two questions. The first question is, how many can be electrically verified as yield limiters? The second question is, from these electrical verified yield limiters, how many of these can actually be consistently detected in-line? Currently, the traditional optical in-line inspections utilized at APRDL are inconsistent in the back end. This is because copper technology introduces what are called “cosmetic defects” — defects that are easily detected through optical inspections, and compromise the killer defect to signal-to-noise ratio. By utilizing an e-beam platform, we can take advantage of its built-in signal-to-noise advantage of current versus previous layer to catch only current layer physical defects. This naturally improves our killer defect detection. Also, because voltage contrast defects inherently have a high signal-to-noise ratio, we have a good methodology through sampling of voltage contrast defects. We are therefore confi-

dent that we can approximate the amount of voltage contrast defects that are still related.

sampling methodologies used to monitor our in-line defects, however, we reach a junction where this type of defect is poorly

Electrical Data

F a i l u re Analysis

Yield Analysis

Electrical F a i l u re

In-line Defect

=

Hit!

F i g u re 1. Bitmap overlay analys is verifies copper in -lin e defect “A” to b e a yield limiter.

Verifying a Yield-Limiting Defect This example actually reflects a real world problem seen at APRDL. We used a thin map overlay analysis technique to verify that an in-line copper defect was a yield limiter. However, it was difficult to quantify this defect, “A”, consistently using the current optical inspections, due to poor signal-to-noise ratio and resolution.

As a result, the other enhancements were delayed. Our solution was to utilize the SEMSpec to reliably detect this killer copper Defect A, and to verify the process solution to eliminate the root cause.

Figure 1 shows how bitmap overlay analysis was used to verify that the copper inline defect was a yield limiter. The image on the far right shows an electrical bit map signature (enlarged in the second image), where we correlate a physical inline defect to the electrical failure.

Through analysis we can determine that this is indeed a yield limiter.

This defect type is definitely caught inline through optical inspections. Due to

Normalized Defect Count: 1.00 Defect “A” Capture Rate: 100% Defect “A” Signal-to-Other Ratio: 7.2%

sampled in-line. Therefore, the amount of defect density for this type of yield killer is underestimated, and yield enhancement priority is focused elsewhere.

The inadequate sampling was traced back to the in-line optical inspection setup.

There were actually many previous defects flagged at the current inspection layer that were actually cosmetic. A top-down optical shot of a current metal layer with an underlying metal layer was evaluated, and many black dots were seen on the underlying metal layer. Most optical inspection tools will readily pick this up and thus confuse the number of defect counts in the overall sampling methodology. The previous defects were cosmetic and originated between consecutive inspection zones, and thus would not allow for defect source analysis to eliminate or filter them out in the sampling methodology.

As shown in figure 2, an extensive design of experiment was undertaken, using a wafer that generated a raw defect count on the SEMSpec scan using random mode,

Normalized Defect Count: 14.98 Defect “A” Capture Rate: 10% Defect “A” Signal-to-Other Ratio: 0.05%

F i g u re 2. Cop per killer defect detection.

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indicating that it had the defect of interest.

This was the normalized defect count, and we made the assumption that, in this area of the SEMSpec scan, out of all the defects classified, the Defect A capture rate would be 100 percent. This gives a Defect A signal-to-other ratio of about 7.2 percent.

If you compare that to the baseline optical zone monitor, which is currently being used, you can clearly see that the normalized defect count is about 15 times greater.

However, the Defect A capture rate is only 10 percent, compared to 100 percent for the SEMSpec. Therefore, the signal-toother ratio is definitely less than 1 percent.

Normalized Defect Count: 67.68 Defect “A” Capture Rate: 43% Defect “A” Signal-to-Other Ratio: 0.05%

the same, in comparison to the baseline optimization.

On the other end of the extreme, the signal-to-other ratio can be maximized by suppressing the noise, as was done here.

The normalized defect count now approximates what the SEMSpec count generated.

However, the Defect A capture rate is definitely much less, at 8 percent. This showed that the SEMSpec can be utilized to accurately approximate and catch the number of yield limiting defects on the surface of copper layers.

Normalized Defect Count: 1.04 Defect “A” Capture Rate: 8% Defect “A” Signal-to-Other Ratio: 0.56%

F i g u re 3. Defect count with c han ges to sensitivity.

The design of the experiment also tried to improve the signal and minimize the noise. In this case, you can maximize the sensitivity to try to improve the signal-tonoise ratio. Figure 3 shows that the sheer number of raw defect counts is overwhelming, and in the sampling methodology, it is more than likely that this type of defect would be missed. The normalized defect count increased dramatically to 67 times the number versus the SEMSpec. More of the defects were captured, although not even half of those that were detected by the SEMSpec. The defect signal-to-other ratio actually stayed

Better

As we shift to inlaid copper technology, the shift to interconnect yield accents the integrity of these inlaid features, and obtaining qualitative results using the current optical in-line inspections is challenging. One reason is that the resolution used to determine the good and marginal interconnects is insufficient. At APRDL, we utilize a specialized decoration etch technique to improve the resolution.

However, there are many drawbacks to this technique. The first drawback is that it introduces noise into the inspection results, and thus weakens confidence with the data conclusions. Another drawback is that the

Wo r s e

F i g u r e 4. SEMSpec identi fies var yi ng degre es of via interc onnect i ntegrity.

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analysis wafer is sacrificed and cannot continue on with the process for further inspection at the end of line. With the e-beam inspection tool, we have proven its value for inlaid processing in copper. The resolution between modular and good

SEMSpec identifies marginal via processes on identical stru c t u re s

figure 5. The defects flagged here clearly indicate that they were much different from the neighboring structure and the reference image in the next available die.

In other areas of random logic, we identified missing vias, which were completely

SEMSpec identifies missing vias in random logic areas

F i g u re 5. Defect detection of via issues.

interconnects is excellent, and there is no special process prep required. The scans can be done at either post via etch or the subsequent metal CMP layer. If warranted, the analysis wafers can continue with processing at the end of line for more learning.

Figure 4 shows the SEMSpec’s ability to identify varying degrees of via interconnect integrity. For example, the image on the left would normally suggest a good open via. Whereas, if you move down the scale, you can clearly see that the SEMSpec can differentiate between a marginal via, an incompletely etched via, and a closed via. This has been routinely used in APRDL to improve our via processing.

In other aspects, by leveraging the random mode capability, we’re able to identify marginal via processes on identical structures, as shown by the SEM micrograph in

SEMSpec scan showing missing vias on initial production tool perf o rm a n c e

undetected using an array mode scan or the conventional e-beam technique of just searching for missing vias.

We also used the SEMSpec to correlate electrical results with SEMSpec defects caught in-line. A plot was taken of a metal stat test structure which measures contact resistance and Ohms for contact.

For this example, the fallout was determined to be about 30 percent. The SEMSpec was then used to find certain errors within this logic circuit, and scanned. FIB cuts were also done. There were two problem areas with one via layer, and another problem with a second via layer. The FIB cut revealed two different root cause failure modes. In one case, the via was completely open, and in another, the via was marginally open. The SEMSpec was able to pick up both types of defects.

SEMSpec scan after production tool fix

F i g u re 6. Produc tion t ool fix based on SEMSpec re s u l t s .

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This should clearly show that by using an e-beam-based inspection tool, via processing can be significantly improved by utilizing the random mode capability, as well as the array mode capability of the SEMSpec.

F i g u re 7. SEMSpec

Validation of process tools

det ects voltage contra st defects at

It is clear that copper process technology presents obstacles to a production rampup. This is because different tool sets may exist between a development fab and a production fab. More often than not, in a development fab, the process module may require a transit from a different tool set to a more improved tool to continue the process development. E-beam inspections have been used to assist in the validation of process transferability between production fabs, as well as when switching to another type of development tool. The inspection tool’s ability is leveraged to analyze large areas of the device. This technique is also used to supplement current physical and parametric analytical techniques, strengthening the confidence in the process transfer.

post Metal-CMP.

F i g u re 8. SEMSpec in-line via tre n d .

Figure 6 shows a SEMSpec scan that revealed missing vias in the trenches on initial production tool performance. The tool had been deemed “transferable” and was ready to be transferred to the production fab. This was not acceptable. After the processing engineering group came up with a production tool fix, the SEMSpec scan validated that these vias were being printed correctly, so the process transfer could occur.

Another wafer was taken at post-metal CMP and scanned on the SEMSpec using a different production tool. Figure 7

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shows that the SEMSpec caught a voltage contrast defect to the metal structure in the areas that were scanned.

The initial FIB slice showed in the voltage contrast defect that there was some type of defect within this via layer. Upon magnification, it was shown to be a fill-related problem. An additional FIB slice showed that this fill-related problem wraps around the structure of the via, causing continuity problems. This type of defect increases the metal resistance and thereby causes the voltage contrast signal seen by the SEMSpec. In this way, a SEMSpec was used to identify partially open vias, which is very difficult in most conventional cross-section SEM analysis.

Using a process transferable method

An in-line via trend of the development tool is benchmarked, as shown in figure 8.

Using the SEMSpec, we were able to show that for the next five lots going through, we eliminated the voltage contrast defects, but kept it on par with the development tool. This was very crucial in our yield learning for copper.

The industry shift toward copper presents many types of issues with interconnect layers. Because the majority of the process flows resides in the back end, the back end process plays a much larger role in yield enhancement. Automated e-beam wafer inspection has been shown to be valuable in three cases. First, for improvements in copper killer defect detection in-line. Second, the identification of inlaid process issues identified weak points in the modules, and isolated the root cause through the process sections. Finally, for validation of process tool readiness by determining the transferability of the process to production fab. ❈ circle RS#029

Preventing Cross-Contamination Caused By Copper Diffusion

by Ted Cacouris, Senior Technologist, Novellus Systems

Several key developments have fostered the transition from aluminum to copper interconnects: damascene processing to surmount the difficulties in etching copper; copper electrofill technology allowing a low-cost, bottom-up fill of damascene features; and the deployment of new materials and methods that avoid the catastrophic contamination of devices. To prevent device contamination caused by copper diffusion from interconnects into the silicon, diffusion barriers such as silicon nitride and tantalum or tantalum nitride have been created.

els, leading to shorts or leaky paths between conductors; and, because copper is a deep-level trap in the silicon bandgap, high standby leakage of transistors, leading to inoperability.1–3 As illustrated in figure 1, under moderate temperatures atomic copper diffuses rapidly in silicon, having a higher diffusion coefficient in silicon than gold, silver, sodium, and iron.4 And under moderate temperatures and bias conditions, ionic copper is a fast diffuser in

Because the initial market for copper products is occupied by high-end logic devices, a trace amount of copper in unwanted places can have a severe financial impact.

Preventing contamination caused by copper diffusion from the inadvertent deposition of copper on wafer backsides poses a more daunting challenge. This problem has been addressed in part by more stringent requirements imposed on processing equipment and more demanding protocols imposed on manufacturing practices. The transition to copper is reminiscent of the earlier introduction of chemical-mechanical planarization into semiconductor manufacturing, whereby tools were initially segregated in separate, isolated areas for fear that slurry could contaminate the entire fab. This article investigates the issues raised by the semiconductor industry’s introduction of copper into the manufacturing process and discusses methods such as equipment segregation, dedicated tools, and special wafer-handling methods that help prevent copper contamination.

Effects of copper contamination

Copper diffusion in silicon devices can lead to two main types of failures: the deterioration of insulators at the interconnect lev-

many dielectric materials. As a result, any trace copper that finds its way either into silicon directly or into a dielectric can have detrimental effects. Because the initial market for copper products is occupied by high-end logic devices, a trace amount of copper in unwanted places can have a severe financial impact — 200 mm wafers populated with $300 logic chips represent a potential revenue of $60,000 per wafer.

For this reason, manufacturing plants have been reluctant to make the transition to copper and have done so only after extensive preparations. Stringent requirements have been placed on equipment suppliers to ensure that no detectable traces of copper are present on the bevels and backsides of wafers after processing. New factory protocols have been developed to heighten awareness among production personnel and to contain copper contamination. For example, copper personnel in several U.S. fabs wear distinctively colored cleanroom gowns so that they can be prevented from Autumn 1999

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entering noncopper stations and to remind them to follow copper-specific protocols.

COPPER CVD TITANIUM NITRIDE COPPER SILICON

550°C

600°C

CLEAN SURFACE

SILICON

COPPER

SILICON COPPER AND TITANIUM NITRIDE REMOVAL, SECCO ETCH

OPTICAL PHOTOMICROGRAPHS PITTED SURFACE

SILICON

SILICON

COPPER DIFFUSION

Figure 1. Diagram of a test for barrier effectiveness using blanket films in which a thin CVD titanium nitride

barrier,

sand-

wiched between copper and silicon, breaks down at 600°C, leaving a pitted silicon surface.

Factory layout can also be used to minimize opportunities for cross-contamination. Several facilities in Europe and Taiwan have been constructed with this precaution in mind. In order to clearly identify the wafers that have received copper processing, specially colored wafer carriers and conspicuous labels indicating the presence of copper products are used to segregate wafers made of different materials. Protocols require that once a wafer has entered a copper bay, it cannot return to a non-copper bay.

Sources of copper contamination

Contamination can arise from tools and equipment involved in the deposition and handling of wafers. For example, a deposition tool that coats wafers with copper films may deposit copper on the bevel of the wafer. This wafer may then be sent to a metrology tool equipped with a wafer handler that manipulates the edges of wafers processed in various areas of the fab. This wafer handler, contaminated with copper, can then cross-contaminate wafers that are destined for an etch tool. The etcher eventually becomes contaminated with copper, and the copper “virus” spreads quickly through the fab, accumulating in plasma process chambers, wet benches, and lithography steppers. Contamination can also spread by way of the wafer’s backside.

Many wafer handlers, or robots, grab or lift wafers by their backsides. Even submonolayer impurity levels of less than 1015 atoms/cm2 on wafer backsides can result in the increasing contamination of a multipurpose handler such as that used on an inline scanning electron microscope (SEM).

The damascene or dual-damascene process affords devices a certain measure of protecC-14

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tion against copper contamination. Copper diffusion barriers such as tantalum nitride, titanium nitride, and insulating silicon nitride provide on-chip protection against copper migration from interconnect structures to neighboring dielectrics and silicon.5 These materials are widely used in the copper damascene process architecture, effectively encapsulating every single interconnect, as illustrated in figure 2.

Frontside layers and processes, however, do not sufficiently protect devices against external sources of copper that may contaminate the bevel and backside regions of the wafer.

The use of dedicated metrology tools for copper processing can also help prevent cross-contamination. A common approach is to set specifications for all copper tools that limit the detectable levels of copper contamination on wafer backsides. This places the burden of cleanliness on the equipment suppliers.

Critical cross-contamination in the fab

Cassette/Wafer Handling Wafer handling is the most likely source of copper cross-contamination, since it is the most universal mechanism in a facility.

This includes not only automation equipment, such as robots, but also plastic wafer carriers, or cassettes. If copper is left on the wafer bevel as it exits a process tool, the carrier will invariably be contaminated with copper. Great care must be taken either to limit the use of wafer carriers to a specified area or to switch to clean carriers once the copper is removed from the bevel. The management of this task can be logistically complex, because most semiconductor equipment is designed for cassette-to-cassette automation — that is, one carrier handles both incoming and outgoing wafers.

Additional costs may be incurred to clean wafer carriers more frequently than otherwise required for particle control.

Shared Metrology Tools Because new metrology equipment is increasingly sophisticated and hence costly, excess capacity and redundancies are rare in this area. For this reason, the metrology area is a prime source of copper contamination. Shared metrology tools may include

in-line SEMs for critical dimension measurements, film-thickness monitors, inline electrical testing equipment, and optical defect inspection devices.

Manufacturers generally find that the acquisition of dedicated equipment for copper processing is cost-prohibitive, but they must seek to strike a balance in order to limit the danger of copper cross-contamination.

Lithography Like metrology tools, lithography tools (steppers, resist tracks, develop tracks) are so expensive that they are often designed as the rate-limiting step in the throughput models of fabs. Such tools are usually “qualified� so that they can be used interchangeably for many mask layers, allowing the dynamic balancing of capacity and redundancy in the event of a tool failure. It is thus difficult to dedicate certain lithography tools for copper interconnect layers.

Wafer Breakage No factory is immune to wafer breakage, although incidence levels have been decreased dramatically. However, protocols for cleaning tools and areas in which a wafer containing copper films has broken are crucial to preventing factorywide crosscontamination. A decontamination plan understood by all factory personnel is required for each area and tool. Such a plan must assume that the broken copper wafer has contaminated the immediate area in which the breakage occurred, mandating appropriate cleaning methods and wipedowns to remove all traces of copper contamination. For example, if a wafer breaks within a physical vapor deposition (PVD) tool, the tool must be vented and cleaned so that every surface which comes into contact with a wafer either directly or indirectly is copper-free. Unfortunately, no easy test exists for demonstrating the cleanliness of a tool short of analyzing a test wafer for copper contamination.

Tools and contamination control

Metrics for copper contamination are usually based on particle adders and trace copper impurities on wafer backsides. Most conservative fabs place such impurity levels at below 1011 atoms/cm2. Measurement

methods such as total x-ray fluorescence (TXRF), vapor phase desorption (VPD), and secondary ion mass spectroscopy (SIMS) can resolve contaminants approaching 109 atoms/cm2. However, a wide variance in measured surface impurities is typically observed when sampling virgin wafers. The establishment of a proper contamination threshold takes this variance into consideration. One fab in Taiwan has applied such a data-driven approach in setting contamination limits. In this facility many robotic wafer handlers are metallic by design and can therefore impart some metal contamination to the wafer through physical contact. To determine the level of copper contamination, TXRF or SIMS is used to sample and measure the backsides of product wafers from the Al(Cu) interconnect manufacturing line. Tests have shown that the SILICON NITRIDE BARRIER ETCH STOP equipment contaminates wafers with copper levels as high COPPER as 1012 atoms/cm2, leading the facility to TANTALUM establish a copper NITRIDE DIELECTRIC contamination speciBARRIER fication of ≤1012 atoms/cm2.

Copper seed deposition (typically by a PVD technique), copper bulk fill by electroplating, copper CMP, and any associated cleaning steps directly influence copper contamination. Through contact with a PVD tool, for example, a wafer backside can receive trace copper if the PVD copper module does not clamp and physically prevent copper from migrating to the back of the wafer during the deposition step. Also, any target- or shield-generated particles made of copper can find their way to the wafer pedestal or chuck, thereby leading to contamination of the wafer backside. CVD copper deposition is particularly vulnerable to this form of cross-contamination.

Any trace copper precursor that does not get pumped away before the wafer is lifted from the heated pedestal results in finite levels of copper deposition on the pedestal, which in turn contaminates wafers.

Figure 2. Dielectric (silicon nitride) and metal (tantalum nitride) barriers encapsulate copper in a damascene structure and protect against copper migration from

interconnect

tures

to

struc-

neighboring

dielectrics and silicon.

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Similarly, dielectric tools that are used to cap copper after a copper CMP step such as silicon nitride deposition can cause contamination if care is not taken in handling wafers with exposed copper that enter this module.

F i g u re 3. Bevel r e g i o n of a

w afe r

Controlling bevel and backside contamination

lac ki ng

b a rrier mat erial under s ome a reas of the cop-

another typical mode of copper contamination. Any copper on the wafer lacking an underlying barrier layer to prevent copper diffusion is likely to adversely affect devices, since copper is very mobile at elevated temperatures. For example, when copper is deposited on the entire face of the wafer to maximize the usable diameter (full-face coverage), it wraps over the bevel region. Although an underlying barrier material such as tantalum nitride would otherwise prevent copper diffusion, this barrier may not wrap over the bevel region as extensively as the copper layer, leaving areas exposed to copper diffusion, as illustrated in figure 3.

per surf a c e .

Etching tools that define damascene structures are also vulnerable to copper contamination. As a via is etched to open a contact to an underlying copper interconnect, the plasma etch process briefly bombards exposed copper. If care is not taken to design an etch process that does not resputter copper, copper can accumulate over time in the etch chamber, which can in turn contaminate future wafers.

F i g u re 4. TXR F measurem e nts

re vea li ng

t hat

wa fers pro cessed with the c lamshell meth od have a lower average level and s mall er sp read of c opper cont amination than those p rocessed with the wafer backsi de exposed.

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Copper deposition by means of electroplating can contaminate wafers if copper-containing chemicals are not prevented from reaching a wafer’s bevel and backside.

These surfaces can be protected by clamping and sealing the wafer hermetically during the plating operation so that only the face of the wafer, not the bevel and backside, is exposed to the process as required.

The Sabre Electrofill tool from Novellus Systems has successfully implemented such a method. By using a clamping method known as a clamshell, the tool prevents wafers from being exposed to copper-containing solutions, resulting in wafers whose backsides are free of copper.

Although contaminated wafers can be cleaned by using aggressive chemical and mechanical techniques, these methods are not as effective as simply avoiding contamination (exposure) in the first place.

Furthermore, such cleaning methods can be costly and risky. Figure 4, summarizing the results of a controlled experiment, demonstrates the advantage of protecting the wafer backside. In this example, some wafers were processed with the Sabre process and others with a more conventional approach involving the exposure of wafer backsides to plating solution mists.

TXRF measurements revealed that wafers processed with the tool’s clamshell method have a lower average level and smaller spread of copper contamination than those processed without the clamshell

method. Removing a high level of contamination mandates that a separate step be incorporated into the process flow to clean the wafers immediately after deposition, increasing processing costs.

An extensive set of TXRF data, shown in figure 5, was collected by IBM over a period of time when more than 100,000 wafers were processed through a Sabre tool. Silicon test wafers were periodically sampled during production by loading them upside down in the tool so that the wafer face came into contact with the clamping surfaces. Then they were run through a typical process sequence. A subsequent TXRF surface analysis showed a consistent copper concentration of less than 1011 atoms/cm2, which was similar to the copper concentration on control wafers that did not undergo the plating process.

Conclusion

Copper contamination presents a significant challenge to the production of on-chip copper interconnects. A thorough grasp of the potential sources of contamination has led manufacturers to develop copper-specific methods that are not only conservative but also costly. Equipment segregation, dedicated equipment such as metrology tools, and novel wafer-handling methods help prevent cross-contamination. Further refinements in copper-processing tools will ultimately greatly lessen the risk of crosscontamination, easing the transition to high-volume copper manufacturing. ❈

F i g u re 5. Copper c ontaminati on levels on th e backsi des of

mo re

t ha n

10 0, 000

waf ers p rocess ed with t he clamshel l method were less than 10 1 1 a t o m s / c m 2 .

1. AG Milnes, Deep Impurities in Semiconductors (New York: Wiley, 1973).

2. RN Hall and JH Racette, “Diffusion and Solubility of Copper in Extrinsic and Intrinsic Germanium, Silicon, and Gallium Arsenide,” Journal of Applied Physics 35, no.3 (1964): 379–385.

3. EM Conwell, “Properties of Silicon and Germanium, Part II,” in Proceedings of the IRE 46, no. 11 (New York: Institute of Reliability Engineering, 1958), 1281–1283.

4. DL Kendall and DB DeVries, “Diffusion in Silicon,” in Semiconductor Silicon, eds. RR Haberecht and EL Kern (New York: Electrochemical Society, 1969), 358–371.

5. K Holloway et al., “Tantalum as a Diffusion Barrier between Cooper and Silicon: Failure Mechanism and Effect of Nitrogen Additions,” Journal of Applied Physics 71, no.11 (1992): 5433–5444.

Acknowledgments The author would like to acknowledge the valuable contributions of Eliot Broadbent and Michal Danek of Novellus Systems in the preparation of this article.

* Reprinted from MICRO, July/August 1999. Used with permission. Copyright 1999 by Canon Communications LLC.

Ted Cacouris, PhD, is a senior technologist for the copper damascene program at the Novellus Portland Technology Center (Portland, OR).

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THEY SAY

Defect at bottom of high aspect ratio trench causes seed layer discontinuity and subsequent void in copper plating.

ALREADY THERE.

These days, there’s a lot of talk about copper interconnect technology. But not nearly enough yield. Fortunately, that’s where we can help. After all, we’re the undisputed market leader in defect and metrology systems for copper development and production. And the only company with extensive production expertise in both e-beam and optical inspection technologies.

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range of solutions – available right now – for use with any process tool set. All designed to quickly isolate yield-limiting signatures and sources. And accelerate your copper yield learning. Proof once again that more than any other company, we know how to make your journey to copper yield a productive one. For more information, please call us at 1-800-450-5308, or visit our website at www.kla-tencor.com/4copper.

©1999 KLA-Tencor Corporation.

Non-Contact Copper and Cobalt Detection For 0.18 µm Technology

by Janet Benton, Bell Labs, Lucent Technologies This article is based on a transcription of a paper presented at the KLA-Tencor YMS seminar at SEMICON/WEST 1999.

This article addresses the effect of copper and cobalt use in back-end processing trace contamination on the front end. This article will discuss the results of a collaboration between Bell Laboratories, the Silicon

F i g u re 1. Qua ntox funda mental sil icon m e a s u re m e n t s .

Research Department of Bell Labs at Murray Hill, and KLA-Tencor.

A unique window of opportunity was available just prior to the upgrade of the research fab line at Murray Hill. We were able to have the last lot of wafers that went through the line be intentionally contaminated. This enabled us to decide how we could measure trace contamination, whether it would F i g u re 2. Cob alt ki lls bul k lifetime.

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make any difference, and what it would do to the electrical properties of either the silicon or the SiO2 gate oxide. The contamination was introduced two different ways.

First, it was implanted using one MeV implant of either copper or cobalt on the back of the wafer after the oxide had been grown on the wafers.

We used both floatzone and epitaxial silicon. We then annealed the wafers at either 600°C or 1000°C. After processing, we used a KLA-Tencor Quantox to measure deep level transient spectroscopy (DLTS), total internal reflection X-Ray fluorescence (TXRF), and charge-tobreakdown (QBD) on polydots, for both cobalt and copper. In the case of cobalt, we did a second method, using the dip method. After we grew an oxide on our silicon that was either 40Å, 100Å, or 1000Å of SiO2, we dipped the wafers into a standard cobalt solution. We then followed that with a 900°C anneal for 30 minutes, and did similar techniques for characterization. What we found was that

the Quantox measurements proved to be the most valuable. Therefore, most of the data presented in this article will be Quantox measurements.

A Quantox measurement is a corona-oxidesilicon measurement. We deposit the charge, measuring the amount of charge deposited on top of the oxide. We then measure two parameters: the surface voltage and the surface photovoltage. There are multiple variations that allow us to look at the properties of the SiO2, as well as those of the silicon. We found in our particular case that the recombination lifetime was the most valuable measurement.

As shown in figure 1, after we deposit our corona, we eliminate the sample with a xenon light pulse, which increases the surface photovoltage. We then turn the xenon lamp off, and watch the decay of the photovoltage. The decay has two regimes: the high injection bulk recombination lifetime regime at the top part of the decay curve, and the medium injection regime at the lower part of the decay.

Figure 2 shows the high injection bulk recombination lifetimes for all the cobaltcontaminated wafers. We took five site measurements on each sample. The samples on the left side are from the dipped experiment. Of the first three columns, one was dipped. First, we grew a 40Å oxide, dipped it, then annealed at 900°C. The two controls are a 40Å oxide by itself and a 40Å oxide that also received the 900°C anneal. The 100Å and 1000Å dipped wafers are also shown in the left side of the figure. Those results clearly show that if you put cobalt on the surface and anneal at 900°C it goes through even the thickest oxide and kills the lifetime of the silicon underneath.

taken out and annealed at either 600°C or 1000°C. Our research showed that no matter how the cobalt is introduced, no matter at what temperature it is annealed, the silicon lifetime is dead. There are two important conclusions to be made. First, Quantox is a valuable tool for identifying small amounts of cobalt present in the material. This is not trivial because we have very few ways of knowing whether or not we have metal contamination introduced during the front end. The second conclusion is, rather surprisingly, that the cobalt is such a lifetime killer. In addition to the site measurements, we also did lifetime maps with the

F i g u re 3. Cob alt re d u c e s lifetime th roug hout bulk of FZ wafers.

High injection bulk re c o mbination lifetime (µsec) 1.5e+003 1.29e+003 1E11Co cm - 2, 600°C , 30 min

1.07e+003 857 643 429 214

600°C, 30 min contro l

0

Quantox tool, as shown in figure 3. The scale on the left is in microseconds, so we are measuring the high injection bulk recombination lifetime over the entire wafer. The control received an oxide growth of 100Å SiO2, and then was annealed at 600°C for 30 minutes in N2.

The lifetimes are relatively high, except around the edges. The other two are for the two doses of cobalt that were implanted on

1E12Co cm - 2, 600°C, 30 mi n

F i g u re

The last seven wafers in figure 2 were from the backside implant experiment. The first of those was just the plain control wafer out of the box. Then two different doses of cobalt, 1x1011 cm-2, 1x1012 cm-2, at two different anneal temperatures (600°C and 1000°C). For the last two wafers, the wafer went into the implantation machine but was not implanted — this was just to test whether the machine itself introduced any contamination; those samples were then

4.

DLT S

sh ow s

extended defects re l a t e d to cobalt conta mination.

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the backside of the wafer. During the anneals at 600°C for 30 minutes, the cobalt has diffused from the back of the F i g u re 5. High Dif f u s i v i t y of cobalt r esults in pr e c i p itat ion dur ing the c ool.

wafer through to the front and completely killed the carrier lifetime in the silicon substrate.

The question then was: in what form is the cobalt in the lattice itself? Would it be in a soluble form, or in another form? Would it collect at the top SiO2/Si interface?

What could we find out about it? DLTS helped a little bit here, as shown in figure 4. DLTS is a measurement that allows us to look at defects in the silicon lattice which have specific states in the energy gap of the silicon. So if, for instance, iron is in the sample and it is in its interstitial position, there will be a peak in the DLTS spectra.

The height of this peak will be related to F i g u re 6. Cobalt re d u c e s

the concentration of iron in the sample.

The bottom curve is our control and the sample does, indeed, have iron in it. Two peaks are shown, one marked Fei, which is iron in the interstitial position. The other, marked FeiBs, is iron interstitial sitting next to a boron atom. These are well known. In DLTS we can see metal contamination in the silicon lattice if it is in interstitial or a substitutional position.

Figure 4 also shows the DLTS spectra from two of the cobalt samples. The samples were both introduced at a dose of 1x1011 cm-2. One was annealed at 1000°C, and the other was annealed at 600°C. What can be seen here is that it is not cobalt in a soluble or a substitutional position. Also shown is a very broad DLTS peak.

Normally, broad DLTS peaks indicate an extended defect. If you have metals that diffuse fast and your process has a slow cool, you would expect the metals not to remain in solution, but rather to precipitate during the cool.

We will now detail the diffusivity of cobalt and copper. Figure 5 shows the diffusivity of most of the transition metals in silicon.

The chart shows that cobalt and copper, along with nickel, are the fastest diffusers in silicon. In this case we have introduced a

High injection bulk recombination lifetime (µsec). 600°C, 30 min

lif eti me throughout bul k of FZ waf ers.

1E11Co cm - 2

C o n t ro l

1E11Cu cm - 2

1.5e+003 1.29e+003 1.07e+003 857 643 429 1E12Co cm - 2

214 0

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1E12Cu cm - 2

metal which is a very fast diffuser and has a relatively slow cool, which is the case with most standard furnace anneals. So we do expect the cobalt and the copper to precipitate during the cool. That is not particularly surprising. What is surprising is that precipitated metals would have such a dramatic effect on the lifetime of the silicon.

Figure 6 shows the lifetime maps for our copper results. The control is in the middle, the cobalt experiments are on the left, and on the right are results from the experiments where copper was implanted on the backside of the wafers. Two things are apparant. First, in the case where we compare copper to cobalt, it is obvious that the cobalt has a much more dramatic effect on the lifetime than copper. But the copper does seem to be scaling with the amount that we put in, since the lifetime has been reduced for the one on the bottom right, where we implanted 1x1012 cm-2, more than it has been reduced at the top.

The correlation is shown even more dramatically in the set of data in figure 7.

Here our experimental points are plotted against other experiments that KLA-Tencor has performed with another fab line. We are plotting recombination lifetime versus the amount of copper intentionally introduced into our substrates. In our case we implanted it, as shown in the data points for Fab 1. In the case of Fab 2, they had dipped their sample in copper, and then determined the amount of copper by vapor-phased absorption, inductively coupled plasma spectroscopy (VPD-ICPMS).

They essentially etched off the top 0.7 µm of the silicon, then checked to see how much copper was in the vapor that was etched off. As shown, the more copper, the lower the lifetime. It will take more copper than cobalt to kill the lifetime — while 1x1012 cm-2 is not a lot of copper, it will reduce the lifetime.

One more result on the cobalt was particularly interesting. Although figure 2 shows the cobalt diffuses readily through the SiO2, it does not seem to migrate from one wafer to another during the furnace anneal.

Figure 8 shows three wafers that were put right next to each other in the furnace. The one on the left was intentionally contami-

nated using the dip experiment. The next one was the control that went through the furnace right next to the dipped one. In F i g u re 7. Concentration of c op per

cor rel a te s

with

red ucti on in bulk li fetime.

fact, the second wafer was turned around, so that the two polished sides were facing each other in the furnace. The last one had no dip and no anneal. Even though the cobalt wafer and the control wafer were right next to each other in the furnace, we saw no effect of cobalt migrating from the contaminated wafer to the next one.

Figure 9 shows how the trace contamination affects the oxide itself. The oxide, deposited polysilicon dots, was grown, then conventional CV/IV measurements were performed. QBD data, or charge-tobreakdown data was taken, implanted and

F i g u r e 8. N o evi de nc e of cob alt migration during f u rna ce a nnealing.

High injection bulk re c o mbination lifetime (µsec) 1.2e+003 1.03e+003 900°C, 30 min, fac ing Co wafer

857 686 514 343 171

Co dip, 900°C 30 min

0

annealed, and charge-to-breakdown data was taken again. The controls are the first three on the left. The copper samples at both doses, 1011 and 10 12 cm-2, and both temperatures, are the next four. The cobalt Autumn 1999

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know from the lifetime measurements that the cobalt diffused through the oxide. It appears that the cobalt on the surface diffuses through that oxide and into the silicon, killing the carrier lifetime, but surprisingly doesn’t seem to affect the quality of the oxide.

F i g u re 9. Ion im planted cop per or cobalt d oes no t change c harge to bre a kdo wn of oxides.

Figure 11 shows the tunneling voltages for the copper samples. We have floatzone and epi. The copper was only introduced by implant on the back. Although the copper diffuses all the way through the sample, it does not seem to diffuse out of the silicon and into the oxide, causing no change in Etunnel.

samples are next, and then just two controls that went through the anneals. We are comparing QBD before implanting anneal and after processing. It is clear that the copper has absolutely no effect on charge-to-breakdown. There appears to be scatter in the data, but it is unlikely that it can be associated with cobalt itself, because in some cases the cobalt seems to increase the QBD and in some cases it decreases it.

Another measurement taken using the Quantox tool is the Etunnel measurement, where a large charge is put on the sample and the surface voltage is put into saturation, and then the Etunnel is measured. This data is shown in figure 10 for all of the cobalt samples that had 100Å of oxide.

This measurement changes with oxide thickness, so only 100Å oxides are compared. For the cobalt samples, the tunneling voltage did not change, although we F i g u re 10. No ef fect of cobalt on oxide tunn eling voltage.

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The important thing about these results is that they are very specific to the process conditions. Figure 12 shows the Quantox measurement Qtot , which is the total charge on the oxide. This was measured as a function of copper in our samples. In our experiment, it doesn’t seem to matter how much copper was in the silicon–we still had the same quality of oxide. Whereas, in the case of Fab 2, the more copper put on the surface, the bigger the change in their Qtot. Therefore, although in some cases the copper will not cause a problem, in other cases it will. Further, it appears that it will be a long time before we know exactly when copper is going to be a problem to the front end of our system.

Conclusions for Cobalt It was clear in our experiment that it only takes a very small amount of cobalt to kill the lifetime. In the case of the cobalt dip experiment, we estimate that the dose was 1x109 cm-2, which is not very much cobalt.

F i g u re 11. No eff ect of copp er on oxi de tunnel ing voltage.

In fact, it is below the TXRF detection limit. All of our samples were sent out for TXRF, both before and after our measurements, and in no case were we able to detect cobalt using TXRF. Therefore, you cannot count on TXRF to determine whether there should be concern about cobalt contamination. In fact, even lower amounts of cobalt in your system will cause dramatic decreases in the lifetime of your sample.

tool for detecting the presence of cobalt, and that the TXRF is not really adequate.

Concern about cobalt contamination dictates the need for a tool that is more sensitive.

Conclusions for Copper The copper experiment showed that trace amounts of copper also kill the carrier lifetime in silicon. Further, copper introduced into the silicon bulk after oxidation does not affect the oxide characteristics, at least not QBD or Etunnel. Lastly, we concluded that processing conditions change the effect of copper on the device oxide.

In general, metal contamination during silicon device fabrication results in wide variations in electrical properties of the silicon and of the SiO2, and depends on the process flow. Therefore, careful monitoring of multiple electrical parameters is absolutely imperative. ❈ circle RS#035

F i g u re 12. Processing condition s change the ef f e c t of copp er on total oxide cha rg e .

We also saw that cobalt diffused right through the oxide, whether it was 40Å, 100Å, or 1000Å. It did not migrate from one wafer to another during a heat treatment. The cobalt was shown not to affect the oxide characteristics. It did not affect either the charge-to-breakdown or the Etunnel. Our experiment showed that the Quantox turned out to be a very powerful Autumn 1999

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CD SEM Measurement of Dual-Inlaid Copper Interconnect

by Richard Elliott, Strategic Marketing Manager, KLA-Tencor E-Beam Metrology and John Allgair, Ph.D., Litho-Metrology, Motorola, APRDL

The introduction of copper interconnect for semiconductors presents several unique challenges for critical dimension metrology in both lithography and etch processes. The dual-inlaid process introduces multi-pattern features and higher aspect ratio structures. These dual-layer structures present new challenges to the imaging and measurement capability of the CD SEM, but also offer opportunities through new indevice measurements to collect process information that has been unavailable in conventional interconnect processing.

With copper interconnect, the nature of dual-inlaid structures adds complexity to lithography and etch processing. Patterning two layers sequentially prior to metal deposition increases the aspect ratio of final structures, and forces etch depth control not previously required. Higher aspect ratio structures require thicker resists which can reduce process windows and make clearing contact holes and trenches more difficult.

In parallel to these new processing challenges, additional constraints are placed on the critical dimension metrology. The interactions now possible between the sequentially patterned contact and line layers dictate that in-device features must be measured more often or more complex duallayer test structures must be used for process control metrology.

1) Metal 1 CD 2) Via 1 CD 3) Via 1 to Adjacent Metal 1 (Oxide) Space 4) Via 1 to Metal 1 Overlay Tolerance 5) Metal 1 space

M2 1

4

2

V1 3 5

Figure 1. Process critical dimensions.

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M1

Dual-inlaid process flow

Dual-inlaid interconnect processing represents a significant departure from conventional single-layer processing. While the metal line and via steps are completely independent in aluminum metal patterning, the two steps are combined for dual-inlaid copper. Two distinct options for the metal and via steps within the dual-inlaid process are possible:

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1) The metal line areas are patterned as trenches and partially etched into the dielectric. Contacts or vias are patterned within the line trenches, then etched into the trench. The specific CD metrology challenge with this scheme is that the contact holes in resist are very deep. Excellent electron collection efficiency is required from the CD SEM in order to image and measure the holes.

2) Vias are patterned and partially etched into the dielectric. Line patterns are printed over the holes, then the lines are etched into the dielectric, and the vias are etched through the dielectric to make contact with the metal or poly below. The CD metrology challenge here is that not only are the contact holes deep, but both the linewidth and via must be measured after litho and etch.

The linewidth may be in spec, but it is still possible that the contacts have not been effectively cleared. Both must be measured and controlled.

Several dimensions are critical within the process flow. Figure 1 shows a cross-section diagram of the dual-inlaid structure. Metal width (1), metal space (5) and via width (2) are the CD measurements typically made in an interconnect process. Two additional critical dimensions exist in the structure — oxide space (3) and via overlay (4) —but are not generally measured in top-down SEM metrology. The oxide space (3) cannot be determined because the metal lines are not visible with an SEM through the dielectric layer. The via overlay (4) is not measured using conventional optical measurement techniques due to the complexity of the indevice measurement of a structure at the bottom of a deep contact hole. The improved capabilities in the newest CD SEMs such as the 8100XP enable automat-

ic measurements such as via overlay that have previously been impracticably difficult.

CD SEM capability requirements

In order to measure a dual-inlaid contact hole or trench feature at litho or etch, two key attributes are required of the metrology CD SEM. First, the SEM must be able to efficiently capture electrons from deep structures to provide clear images of the bottoms of trenches and contact holes.

These dual-inlaid structures can be up to twice the depth of corresponding singlelayer line or contact structures in conventional interconnect processes. A typical deep-trench structure is shown in figure 2.

Second, the metrology algorithm must have the capability to exclude irrelevant edges from the analysis of the measurement scan.

To measure a contact hole that is patterned in the bottom of a line trench, the trench edges must be ignored. Similarly, if the trench width is to be measured, the presence of the contact hole must be ignored.

Apparent in the figure are both specific measurement challenges, a deep trench combined with additional feature edges, as well as the presence of the via space. The measurement of this via space can provide significant information that is not available from just the metal linewidth or contact opening.

Adjacent interconnect leakage

One failure mechanism for interconnect failure is current leakage between two adjacent interconnect paths. A short can develop due to the confluence of several factors. A large Metal 1 or a large V1 CD will make leakage more likely. In addition, a misalignment between the Metal 1 and V1 layers can bring the oxide space (3) to a critical level.

The cross-section image of the interconnect structure in Figure 3 shows the possibility of encroachment between the via and underlying adjacent metal pattern. Note that the via does not have to touch the adjacent metal line for excessive leakage to occur. If the oxide space is too small, current leaking through the space will result in a failure.

This oxide space cannot be measured directly in-line — a destructive cross-section measurement is required. However, using a

CD SEM, this space can be estimated by using the metal line measurement combined with the measurement of the via to metal overlay. This measurement can be made within the actual working device, not just in a scribe line test pattern. The measurement of overlay on in-device structures requires a third unique CD SEM capability.

With curved structures, the ability to obtain multiple scans over a profile and fit a curve to a device structure is necessary. This curve fit can then be analyzed to determine the maximum or minimum space. Figure 4 shows a measurement setup that can be used to measure overlap at the bottom of the patterned via. The oxide space (3) can be calculated by this formula:

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V1 space F i g u re 2. Typi cal dual-in lai d via stru c t u re .

Oxide Space (3) = M1 space (5) - Via overlay (4)

Given this in-line measurement, correlation to the cross-section measurement can be drawn, and an appropriate in-line disposition threshold for interconnect leakage can be established. Good correlation has been measured between the oxide space inferred from CD SEM measurements, and leakage currents measured at final electrical test (Reference) which verifies the in-circuit measurement capability of the 8100XP.

Oxide space

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F i g u re 3. Cross-s ecti on of dualin lai d interc o n n e c t .

Conclusion

Copper interconnect processing has raised new challenges for critical dimension metrology and process control. The deeptrench imaging performance and metrology algorithm intelligence of the CD SEM must be such that the complex, high-aspect ratio structures generated during dual-inlaid patterning can be measured. Hidden in this measurement challenge, however, is the opportunity to increase the value of CD metrology at the interconnect levels.

Through the additional in-device measurement of via to metal overlay in combination with the traditionally measured metal and via CDs, an estimate of the propensity for interconnect leakage can be obtained.

This measurement can provide valuable information towards isolating a serious yield-limiting event. â?ˆ

F i g u re 4. CD SEM image and m e a s u rement of via overl ay. The blue lines ind icate th e locati on of the measur ed edges, while the red lines defin e the box in which the measurement is confined.

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Reference Allgair, J. et. al., SPIE’s Conference on Microlithography, 1999.

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Increasing Learning Rate On Copper Processes

by Jeff Lin, Yield Enhancement Engineer, Motorola, APRDL

In the yield-learning phase of a new process, such as copper dual damascene, one of the challenges is efficient defect detection. A novel statistical method for optimization of copper inspections and sampling strategies was introduced which facilitated increased yield learning rates on the copper process at Motorola APRDL. KLA-Tencor 2138 inspections on copper processes were initially optimized for maximum sensitivity to all defect types. As understanding of copper grew, the tendency for non-killer defects to outnumber killer defects became evident. Because a random sample of defects was sent on for further review, the percent killer defects in the sample was important. Looking beyond the standard methods for increasing the percent killer defects captured in the sample was one of the keys to bringing the copper process to yield quickly.

Killer defects are those most likely to compromise the functionality of the device.

They include large particles, bridging defects, missing patterns, residues, corro-

sion, and defects of unknown origin or composition. Non-killer defects are those less likely to affect a device, such as small defects, small particles, polish slurry, color variation, and other nuisance defects.

Examples of typical killer and non-killer defects for copper processes are shown in figures 1 and 2.

The yield enhancement tool set included a KLA-Tencor 2138 inspection system with IMPACT/Online ADC. Data was downloaded and analyzed using the Klarity analysis system.

Methodology

There are a lot of methods available to reduce the capture rate of non-killer defects on the 2138, including raising the sensitivity threshold, filtering out smaller defects, and using a larger pixel size to lower the system’s resolution. Image smoothing through filters could reduce the non-killer defect count, as could using a tuned segmented auto-threshold (SAT) inspection. ADC could be used to sort nuisance defects; then the sample could be

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F i g u re 1. K ill er defect examples from Motorola APR DL’s copper process. I n p icture 1a,

F i g u re 2 . Non-kill er defect exa mples from Motor o l a

a la rge particle has sh or ted s evera l m etal lines. Picture 1b shows a scratch. Picture s

A P R D L’s copper process. Picture 2a sh ows s lurry

1c and 1f are exa mples of residue defe cts. Picture 1d shows a sec tion of missi ng

res idue. Picture 2c s hows a small pa rti cle out in the

metal. Picture 1 e shows brid gin g of a few metal lines.

fi eld area. Pictur es 2 b a nd 2d ar e color variation.

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Settings

Size Sieve

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Table 1. Details of the five parameter sets used to optimize for killer ratios.

used for comparison to the 2138 inspection data collected later in the experiment. A SEMSpec was chosen as the reference inspection technology because its scanning electron microscope-based technology provides significantly more sensitivity than that provided by the optical-based 2138.

taken from the non-nuisance bins.

Motorola APRDL decided to try a novel statistical approach to determine which method or combination of methods was optimal, taking the sample plan and inspection time into consideration.

Four metrics were used to evaluate the effectiveness of an inspection:

After Final Optimization

600 Normalized Defect Count (from sample)

• The percent killer defects detected, or killer sensitivity, measures the percentage of killer defects detected by the inspector, referenced to the number of killer defects known to be on the wafer. For example, if a 2138 scan found 40 killer defects on a wafer with 50 known killers, the killer sensitivity would be 80 percent. The number of known killers is determined by scanning the wafer using a significantly more sensitive inspection technology.

Motorola APRDL chose to use the SEMSpec as the standard.

500 400 300 200 100 0 18 23 27 28 29 30 31 32 33 36 37 39 40 41 42 43 44 46 47 49 50 51 1

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Work Week Non-Killer Defects

Killer Defects

Figure 3A. Metal 2: killer/non-killer defects by work week. Green bars represent normalized defect counts of the sampled non-killers, while orange bars are the killers.

The improvement in sampling of killers is significant after the new method was imple-

• The killer-to-total ratio, or signal-to-noise ratio, calculates the ratio of killers found to the total number of defects detected by the inspector. For example, if the 2138 found that 40 defects out of a total of 100 were killers, the signal-to-noise ratio would be 40 percent.

• The killer normalized defect density extrapolates the killer defect density of the sample over the entire population of defects found on the wafer.

• The fourth measurement is the inspection time, including wafer handling, alignment, scanning and ADC image collection time.

The first step was to collect reference data to determine the number of “known” killer defects on the wafer. This data set would be

mented on the Metal 2 wafer.

Thus, a SEMSpec was used to scan a Metal 2 copper wafer and determine how many detected defects were killers. The assumption was that the SEMSpec caught all the killers that the 2138 would have been able to find, and more; any defects unique to the 2138 scan were assumed non-killer.

The next step involved setting up multiple inspections on the 2138, with varying sensitivity parameters. Five sets of scans were performed each day with four different pixel sizes, for a total of 20 scans. Table 1 shows the details of the five recipe settings.

Under the assumption that a large defect has a higher probability of being a killer defect, the goal was to quantify the tradeAutumn 1999

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After Final Optimization

Percent Killers in Sample

100% 80% 60% 40% 20% 0% 18 23 27 28 29 30 31 32 33 36 37 39 40 41 42 43 44 46 47 49 50 51 1

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3

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Work Week

Figure 3B. Metal 2: percent killers in sample. The improvement in sampling of killers after the new method is introduced is more evident when percent killers in the sample is plotted for the Metal 2 wafer.

After Final Optimization

Normalized Defect Count (from sample)

400 350 300 250 200 150

Results from a comparison of the five scan types, for each of the four pixel sizes, emphasized that optimizing a 2138 for high sensitivity to all defects — the old method — does not provide the highest ratio of killer to nuisance defects (signalto-noise ratio). A compromise in overall sensitivity can create a detected defect population that more accurately reflects the entire killer defect population on the wafer. After the 20 scans indicated which inspection was best suited to inspection of the Metal 2 wafer, the scan recipe was refined further using standard recipe optimization procedures, to improve killer ratio and capture rate.

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Work Week Non-Killer Defects

Killer Defects

Figure 4A. Metal 3: killer/non-killer defects by work week. Green bars represent normalized defect counts of the sampled non-killers, while orange bars are the killers. The improvement in sampling of killers is evident for Metal 3, although not as large as for the Metal 2 wafer.

After Final Optimization

100% Percent Killers in Sample

off between reduced scan time and sensitivity so that the largest pixel size (shortest scan time) providing adequate defect capture could be used. In setting up the 2138 inspections, the origin marks were chosen to duplicate the origin marks on the SEMSpec scan. Inspection comparison percentages were calculated by overlaying the 2138 data on the SEMSpec data using the Defect Source Analysis algorithm on Klarity.

Figure 3B shows the data in terms of percent killers found within the sample plan.

The improvement in percent killers sampled is even more visible.

80% 60% 40% 20% 0% 15 19 20 24 29 30 32 33 35 36 40 41 43 44 45 46 47 48 49 50 2

3

4 11 12 16 18 19 21 22

Work Week

Figure 4B. Metal 3: percent killers in sample. The improvement in sampling of killers after the new method is introduced is small but significant for the Metal 3 wafer.

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Figure 3A shows the improvement in percent killers found within the defect sample after implementation of the method described above, for a Cu Metal 2 layer.

Generated from the Klarity pareto charts, this chart uses green bars to represent normalized defect counts of the sampled nonkiller defects, while the orange bars represent normalized defect counts of sampled killers. The bias towards sampling of nonkillers is evident in the data taken before the new methodology was applied. After the new method was implemented, a higher percentage of killers was detected.

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Yield Management Solutions

When this method was applied to other layers, improvement in percent killers detected was demonstrated further. Metal 3 zone data, shown in figure 4A, shows a clear rise in sampling of killer types after implementation of the new method. In

After Final Optimization

400 Normalized Defect Count (from sample)

terms of percent killers found within a sample (figure 4B), the change for Metal 3 was not as noticeable as with Metal 2; the sampling of killers and non-killers tended to be more consistent. This can probably be attributed to the higher probability of detecting defects from previous levels at higher metal levels.

350 300 250 200 150 100 50 0 30

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Results from the Metal 5 zone again show some improvement after implementation of the new method (figure 5A). For Metal 5 the change in percent killers is more noticeable than for the Metal 3 zone (figure 5B).

Non-Killer Defects

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Killer Defects

Figure 5A. Metal 5: killer/non-killer defects by work week.

Green bars represent normalized

defect counts of the sampled non-killers, while orange bars are the killers. The improvement in

Summary

sampling of killers is clearly demonstrated for

At Motorola APRDL, a new methodology for increasing capture and sampling of killer defects has been developed and tested. First, a reference data set was determined; Motorola APRDL chose to use a SEMSpec scan as the reference. Then multiple inspection setups were created for the 2138, with various sensitivities, and various wafers were scanned using these parameters. The 2138 data was overlaid to the SEMSpec data by using the Defect Source Analysis algorithm on Klarity, with a userdefined tolerance radius. Killer sensitivity and signal-to-noise ratios were generated.

After the best inspection recipe was chosen it was refined further to improve killer ratio and capture rate.

Metal 5.

This study demonstrated that using a statistical approach allows the user to choose optimal inspection parameters for increased sensitivity to killer defects. In particular, Motorola APRDL found that implementation of this method increased the yield learning rate on new copper processes. Wafer review and data analysis became more productive, and killer defect density paretos became more accurate and understandable — especially valuable improvements in an R&D environment such as APRDL. ❈

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After Final Optimization

Percent Killers in Sample

100% 80% 60% 40% 20% 0% 30

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Figure 5B. Metal 5: percent killers in sample. The improvement in sampling of killers after the new method is introduced is demonstrated for the Metal 5 wafer.

Run inspection on defect tool at varying sensitivity parameters, while recording inspection time

Determine # of killers on wafer(s) through exhaustive review or inspection on more sensitive system (SEMSpec)

Use Klarity Defect to overlay known killers to results to determine % of killers caught

circle RS#039

This paper was first presented at KLA-Tencor’s Yield Management Solutions Seminar at SEMICON/West in July 1999. It was edited for this publication by Rebecca Howland Pinto, Ph.D., in KLA-Tencor’s WIN Division.

Repeat process until % killers caught and % killers in sample are maximized with reasonable inspection time

Select inspection that best meets user’s needs

Figure 6. Inspection Optmization Methodology

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IF CMP WAS DESIGNED TO SMOOTH THINGS OUT, WHY IS IT MAKING COPPER SO ROUGH? We all know that CMP is a way of life. But in the world of copper interconnect, it’s certainly not an easy one. After all, along with seeing what’s happening on the wafer’s surface, you need to be able to see the electrical defects below it. Fortunately, we can help.

Because when it comes to CMP, we offer the most comprehensive defect detection and metrology solutions in the industry. Our eS20, for example, is the only true production e-beam inspection system on the market, and the new standard for all copper CMP development. And with the real-time classification of our high-speed, high-sensitivity optical inspection tools, you can detect CMP excursions before yields are compromised. Add the fact that we’re the undisputed leader in copper yield diagnostics and control, and it’s no wonder we can get you out of R&D and into production faster than you ever thought possible. And that should take the edge off any CMP process. For more information, please call us at 1-800-450-5308, or visit us online at www.kla-tencor.com/4copper.

ALREADY THERE. ©1999 KLA-Tencor Corporation.

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Q&A An interview with Tom Long, vice president of corporate marketing, on KLA-Tencor’s recently introduced process module control solution for copper interconnects

Q

There’s a lot of talk in the industry about the difficulty in achieving acceptable yields with copper. What are you hearing about this from your customers?

A

There are a number of new process challenges associated with copper that relate to scale design rules, new insulator materials, the new dual damascene architecture and new deposition processes like electroplating, as well as new types of CMP processes for copper. Customers have a lot of learning to do and the yields in copper are typically less than 50 percent of what they are in aluminum today. This provides great opportunities for us to work with customers to improve their yields.

Q What do you think are

the biggest yield challenges in the transition to copper?

A The most significant yield issues

revolve around dual damascene, high aspect ratio structures and the successful filling of those structures with copper to prevent void formation. In order to eliminate those voids one has to opti-

mize the lithography, etch and film deposition processes — all of which are interrelated. In addition, the detection of defects in the dual damascene structure is different from the normal subtractive aluminum structure. With aluminum the interconnect structure is all above the surface; with copper, it is buried below. This makes defect detection much more challenging. The introduction of the eS20 in-line e-beam inspection system provides an unmatched capability to solve these problems.

Q

When do you see the semiconductor industry realizing copper yields at levels equal to aluminum processes?

A

Most customers are achieving between 5 and 50 percent of the equivalent aluminum yield with their copper processes. We believe over the period of the next year that some of the leaders will begin to approach the level of yields they have come to expect with aluminum, but only through the use of unique defect and metrology solutions such as those provided by KLA-Tencor.

Autumn 1999

Q

KLA-Tencor recently announced its CuPMC solution.

What does it consist of?

A Our CuPMC utilizes all of our

defect inspection and metrology tools and our analysis software, as well as our extensive yield management consulting and applications expertise.

These components are all focused on the yield and control problems experienced in the film, litho, etch and CMP process modules that are involved in building copper interconnects. KLA-Tencor is the only company offering such comprehensive solutions applied to the copper yield problem.

Q

How many customers do you have using or planning to use your CuPMC?

A

All of the top Cu development fabs in the world today utilize a very high proportion of our overall Cu process module control solution including defect detection, metrology control, analysis software, and applications expertise.

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Diagnosing Processing Problems through Electrical Charge Characterization

by Greg Horner, Senior Scientist; Brian Letherer, Senior Applications Engineer

Process engineers commonly require front-end electrical testers that are both sensitive to process deviations and powerful enough to diagnose any problems that arise in production. For day-to-day monitoring, these engineers usually prefer to monitor just a few electrical test parameters. However, when the process limits on these ‘front-line’ parameters are exceed ed, the electrical test equipment must be able to analyze the problem thoroughly in the shortest possible time. For test data to be meaningful, the results of the various parameters must complement each other in order to present a complete picture of the process deviation.

The KLA-Tencor Quantox system is a noncontact metrology tool capable of characterizing the electrical properties of both dielectric and silicon. It provides process engineers with conventional electrical test data without the need for metallization or other processing. It also offers the ability to improve processing capabilities by reducing the time needed to gather information for monitoring critical processes and process tools.

This system provides highly detailed information that separates the electrical charge contamination into individual categories. It provides an electrical measurement of oxide thicknesses as small as 2 nm, and produces “maps’ or “fingerprints” that provide a quick overview of wafer uniformity. It also monitors heavy metal contamination, both on the surface and in the bulk of the silicon.

Quantox combines three non-contacting techniques to perform the measurement functions. A corona discharge is used to bias the surface and emulate the function of the MOS (metal oxide semiconductor) electrical contact. A vibrating Kelvin probe monitors the wafer surface potential as a function of surface charge. A pulsed light source linked to the Kelvin probe enables the stimulus and detection of surface photovoltage, which, in turn, provides additional information on the silicon bandbending.

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These three techniques provide SPV-Q-V curves that are used to calculate and extract the system’s electrical test parameters.

Heavy metal contamination

Recently, the experience of one user illustrated the complementary nature of Quantox system’s parameters and led to the source of a processing problem.

Engineers at a logic manufacturer monitor their diffusion furnaces on a weekly basis for mobile ionic contamination with an Upper Control Limit (UCL) of 7E10 q/cm2. On one occasion (figure 1), their Qm data showed two wafers (T16 and T3) were contaminated at 1E11 q/cm2 and 7.3E10 q/cm 2 respectively. A third wafer (T8) was within specification at 5.8E10 q/cm2.

Note that the ‘first-line’ Qm measurement may have been affected due to alkali contamination (Na, K, Li) or increased oxide leakage incurred by metal contamination. To isolate the cause of the process variation in the first two wafers, they first tested all three wafers for

F i g u re 1. Mobile i onic contami nation /bulk iro n .

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F i g u re 2. Oxide re s i s t i v i t y.

F i g u r e 4. Bul k recombination lifetime .

oxide resistivity and E tunnel. These tests are designed to measure the low-field (~0.5MV/cm) and high-field (~12MV/cm) leakage characteristics of the oxides.

Figures 2 and 3 indicate that both oxide resistivity and Etunnel data for T16 and T3 were low, suggesting metal contamination of the oxide, while wafer T8 was within the fab’s SPC limits. To clarify the type of contaminant in wafers T16 and T3 further, the engineers measured the bulk minority carrier lifetime of the underlying silicon. While heavy metal contamination strongly affects bulk lifetime, alkali contamination typically has no impact on bulk lifetime. Figure 4 clearly indicates the presence of heavy metal contamination in the bulk of the silicon; the values for wafers T16 and T3 were far lower than the typical BτR Lower Control Limit of approximately 500 µsec.

the high iron samples revealed a metal washer that was beginning to corrode. They fixed the problem, then ran another set of monitor wafers to verify that the tool and the process were back in specification.

The data obtained to that point implied the presence of heavy metals in the oxide as well as in the silicon. To narrow down the type of contaminant further, they ran the Quantox system’s iron detection algorithm. Figure 1 shows that wafers T16 and T3 were contaminated with iron (Fe), while T8 was not. Since Fe in the oxide is known to increase the oxide leakage, they concluded that the contamination must have occurred during oxidation. A close inspection of the furnace that generated

PETEOS optimization for better step coverage development

At a R&D facility in the US, the Quantox system was used in the development of a new process for interlevel dielectric plasma enhanced TEOS films. Earlier publications have indicated that PETEOS grown in a low oxygen and low pressure environment exhibits improved step coverage. To test the effects of this environment on the electrical characteristics of the oxide, the R&D team grew an oxide film with lower oxygen and tested it on the Quantox system for surface voltage (VS). The data obtained (table 1) indicated the low oxygen films had lower surface charge than the baseline process. They also found that by lowering the total pressure during deposition, the Si/SiO2 interface quality also improved, as shown by the flatband voltage (Vfb) measurements detailed in table 1.

Process Baseline Low O 2 Low pressure

DVS 6.2 1.0 7.0

VFB -39 -31 -28

Stress -135 - 66 -119

Table 1. Electrical chara cteristics of low oxyg en or low pre s s u re films.

F i g u re 3. Tunnel ing field.

Initially, these results led them to conclude that this new process provided lower surface charging, as well as the improved step coverage that was originally sought.

The data encouraged them to explore this new process further by combining low oxygen and low total pressure in the same run. The new film surface voltage results, shown in table 2, again indicated low charging.

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of the flatband voltage. Since this is usually the case with leaky oxides, they next used the Quantox system to measure the oxide resistivity and found it to be 2000 times lower than that of the baseline process.

Leaky oxides were causing the corona applied on the surface of the oxide to leak away too fast for the system to make measurements. Further experiments showed that the new film was grown in a tensile condition, which explained its high leakage property.

Process Baseline Low O 2 & low pressure

VS 6.2 0.5

VFB -39 NA

Rox(Ω-cm) 5E17 2E14

Stress -135 +113

Table 2. Electrica l characteris tics of low ox ygen and low pre s s u re fil m.

As a result of these tests, the R&D team was able to get quick feedback for their process parameter development.

They concluded that an environment that combined low oxygen and low pressure produces films with significantly poorer dielectric properties than their baseline process. Relying on VS maps alone would have led them to interpret the data improperly; the leakier films showed low surface voltage because the surface charge was dissipating quickly. By characterizing the oxide fully with Vfb and resistivity measurements, and with VS maps, they were able to develop a far more complete picture of the process.

Phosphorous contamination

exposed to back-end POCL or BPSG processes, then subsequently either cleaned in the wrong tools or misrouted for use as front-end monitors. Phosphorous out-gasses readily, so when these wafers found their way into front-end furnaces, the contamination spread rapidly.

These Quantox system users were alerted to the problem when routine process monitors triggered SPC alarms.

F i g u re 6. Surface voltage map.

In one case, a process engineer was monitoring surface voltage and surface generation lifetime, and was able to confirm and trace the phosphorus problem by using the Quantox system’s Qtot parameter. Figure 5 shows results from daily monitoring of surface generation lifetime; the lot in question experienced a severe drop in lifetime to less than 100 µsec, indicating contamination on the wafer’s surface. The source of the problem was traced back to a wafer boat contaminated with phosphorus.

Figure 6 depicts a surface voltage map; the crescent shape that appears on the wafer’s upper left edge is characteristic of boat contamination, which occurs where the wafer touches the boat.

Figure 7 represents the total oxide charge (Qtot) on two locations on the same wafer, indicating non-uniformity across the wafer and confirming the presence of local charging problems. Fab managers estimated their savings due to early detection at $2.5 million.

Recently, six fabs around the world have reported a severe problem that was ultimately identified as phosphorous contamination. The source of the problem was usually traced back to misrouted wafers. In each case, either monitor wafers or dummy wafers had been

In all of these instances, without the Quantox system, the fabs were unlikely to have detected the problem until end-of-line parametric tests were performed, leading to a loss of several thousand wafers per fab. ❈

F i g u re 5. Surface generation lif etime.

F i g u re 7. Total oxi de char g e .

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circle RS#035

A R I ES C K

®

RYO INETIC C LEANING S YSTEM

A little dust... a mountain of problems.

When a wafer breaks, silicon dust contamination often destroys the entire expensive lot — until now. Now you can reclaim those dusted wafers using the

A RIES # C RYO K INETIC C LEANING SYSTEM . In actual production line evaluations, contaminated wafers, likely to be scrapped, were recovered to normal yields after running through the ARIES cleaning system. Try it. And save yourself a mountain of trouble.

Contact 612.361.7661 or www.fsi-intl.com

Metrology

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Profiling High Aspect Ratio Features for Post-Etch Metrology

by Anna Mathai, Western Regional Metrology Manager and Mustafa Oyumi, Applications Lab Manager

Plasma etching is among the most critical steps in the fabrication of microelectronics devices. It is used in a variety of processes, including the manufacture of contacts and vias, shallow trench isolation, DRAM and dual damascene. A successful etch process must manage complex trade-offs to optimize a number of parameters including critical dimension uniformity (lateral and vertical), selectivity, and a high etch rate. Failure to do so will result in poor process control and device performance.

Of the challenges involved in plasma etching, the largest barrier to consistent device performance is maintaining critical dimension uniformity. Currently, there are three ways to monitor etch depth. The most reliable and hence most commonly used technique is to cross-section the wafer and use scanning electron microscopy (SEM). This technique, however, is undesirable since it requires expensive wafers to be sacrificed. It is also time consuming, with the longer time-to-results causing more wafers in process to be at risk. The second solution is to conduct electrical tests on the wafers after the interconnect level is complete. Here again all the wafers in process are at risk. Third, atomic force microscopes (AFM) are used occasionally to monitor etch depth; however, concerns about tip quality, reliability and ease-of-use have limited their effectiveness as a solution. Clearly, there is a need for a non-destructive, reliable and easy to use technique to measure etch depths with quick time-to-results.

F i g u re 1. Schemati c profilin g of a trench in contact as well as in di pp ing mode.

necessitates that one use a robust stylus characterized by a relatively large included angle. In turn, the stylus geometry limits the aspect ratios of the features that can be resolved by the stylus. A typical work-around has been to measure test structures that are scaled up from the actual geometry. However, since plasma etching depends on the size and pattern density of the features comprising the array, measurements must be performed on the structures themselves and not on test structures.

Contact-mode profiling

Fabs have traditionally used profilers to measure post-etch step heights easily and reliably. With a profiler, as shown in figure 1, a stylus is moved lightly across the surface of a sample (contact mode). The stylus-sample interaction in contact mode generates lateral or shear forces. The need to limit, as well as the ability to withstand this shear force 30

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Dipping-mode profiling

To enable high aspect ratio measurements, a new mode of profiler operation has been developed in which a scan is comprised of a series of discrete steps. The stylus is lightly lowered into contact with the sample, a data point is obtained, and the stylus is lifted away from the sample. After the appropriate lateral motion, this sequence of events is repeated until the profile or image

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F i g u r e 2. HRP image of 0.35 µm geometr y

F i g u re 3. Cross-section through centers o f

F i g u re 4. SEM cr oss-section of 0.35 µm

conta cts , post-etch .

the co ntacts in f igure 2.

g e o m e t r y contacts, post-etch .

Figure 2 shows a dipping mode image of a 0.35 µm contact near the center of the wafer. The image was built up in a raster fashion with a dipping mode profile scan along the x-direction and stepping over the y-spacing between subsequent profiles. The image shows that the bottom of the contact is clearly resolved.

Figure 3 shows a cross-section through the centers of the contacts in figure 2, with the depth measured as 1.105 µm. Figure 4 shows a SEM cross-section image of a 0.35 µm contact, from approximately the same location on the wafer as the data in figure 2.

is complete, as shown in figure 1. In this way, the shear force generated during the sample-stylus interaction is minimized. This enables the use of fine styli with included angles of less than 100, and radii of curvature of 10-20 nm.

Here, we discuss a generation high-resolution profiler, the HRP-240, which provides the ability to measure the depth of high aspect ratio features up to 4:1 at 0.25 µm geometry, while maintaining the reliability and ease-of-use of a traditional profiler.

Table 1 summarizes the HRP measurements from 0.35 µm and 0.5 µm contacts at eleven sites on a wafer, approximately equally spaced along the center line and numbered from left to right. The table also summarizes results from SEM cross-section images at two locations. There is good agreement between the HRP and SEM data.

Measuring high aspect ratio contacts

Contacts are holes in the inter-level dielectric (ILD) which, when filled with metal, make contact between the transistors and the first metallization layers (M1).

Vias are similar to contacts except they connect two metallization levels. Contact or via depth is important to monitor to avoid poor electrical performance resulting from an under-etch or damage to the underlying structure resulting from an over-etch.

Depth of 0.35 µm contacts (µm) HRP-240

SEM

In conclusion, we have demonstrated the capability of the next generation high-resolution profiler, the HRP-240, as a viable Depth of 0.5 µm contacts (µm) alternative to scanning HRP-240 SEM electron microscopy for monitoring the post-etch 1.083 depth of contacts and vias. ❈ 1.113

Site 1

0.995

Site 2

0.996

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1.018

1.147

Site 4

1.058

1.198

Site 5

1.055

1.125

Site 6

1.105

1.028

Site 7

1.113

1.233

Site 8

1.106

1.250

Site 9

1.077

1.240

Site 10

1.090

1.201

Site 11

1.039

1.000

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Acknowledgements 1.210

1.172

1.188

The authors thank Mark Wilcoxson and Bi-ming Yen of Lam Research for wafers, SEM results and valu able insights. They also thank their colleagues, Tom McWaid and Mike Young, at KLA-Tencor.

1.140

Table 1. Summar y of HRP-240 and SEM measurem ents of 0.35 µm and 0.5 µm data at eleven sites acro s s a wafer.

Autumn 1999

Yield Management Solutions

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Lithography

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Perspective: What Shall We Work On Now?

by Jim Wiley, Technical Director, RAPID Division

The mask industry is slipping into trouble. We have to face a broad array of technical challenges over an extremely accelerated roadmap. We’ve experienced two SIA roadmap accelerations in recent months. The new “International Roadmap Committee” has proposed that the roadmap should reflect a 70 percent shrink every two years. If the industry operates on that timetable, IC manufactur ers will be ramping production of 90 nm DRAM features and 65 nm microprocessor gates in 2003. Some people are assuming that generation would be the insertion point for next-generation lithography. In five years, our customers might need a complete infrastructure for NGL masks, and today we don’t even know which ones. If I were an R&D director in a mask shop, I wouldn’t know what to work on.

At the NGL workshop in December 1998 in Colorado Springs, the attendees examined four technologies: SCALPEL, EUV, X-ray, and ion beam projection lithography.

In all four cases, masks represent a severe challenge, more so than the source, the optics, the resist, or the alignment. The feasibility and the cost of masks will strongly influence the industry’s choice of an NGL technique. Whichever candidate wins, lithography in the post-optical era will account for an increasing percentage of the cost of IC manufacturing, and masks will account for an increasing percentage of the cost of lithography.

The four NGL mask types differ substantially — mask writing doesn’t change much, but inspection, processing, and metrology, not to mention particle protection and handling systems, would be dramatically different for each type. It would be expensive and time-consuming to develop a complete tool set for all of them. SEMATECH has decided to focus on SCALPEL 32

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and EUV. But the proponents of X-ray and ion beam projection lithography continue to work on masks for those technologies. Mask makers and mask equipment makers can place bets on one horse or the other, but the safest way to protect their shareholders’ interests is to prepare to support any one of the four contestants. (In fact, they may have to support more than one. Highvolume manufacturers will strongly favor EUV lithography because it offers the highest throughput. But manufacturers of ASICs, custom logic, and low-volume microprocessors will find EUV masks too expensive.)

The consensus at the NGL workshop was that none of the four NGL technologies will be ready when 193 nm lithography runs out of steam; therefore, the semiconductor industry will inevitably have to establish a 157 nm generation of optical lithography. To develop masks for 157 nm lithography, we have to solve some interesting materials problems. Quartz is opaque.

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Calcium fluoride has a large coefficient of thermal expansion, which would make overlay difficult. Some people are advocating fluorinated silica, which might have adequate transmission at 157 nm. No one seems to know of a good pellicle material.

published value divided by the Mask Error Enhancement Factor (MEEF). The MEEF is increasing, and the tightening of specifications is accelerating dramatically.

That challenge alone could keep the mask industry busy for the next few years.

Meanwhile, we have some near-term problems. At International SEMATECH’s Optical Extensions Workshop in January, it became clear that several semiconductor manufacturers are preparing to move phase shift technology into manufacturing. Some of them have told me that they’ve purchased fewer than ten phase shift masks. That means they’re now basing their plan of record on masks which were made in R&D mode. For perspective, consider that some of the participants at the NGL workshop said that proponents of any post-optical technique would have to build at least 300 masks to demonstrate feasibility.

The mask community doesn’t have enough resources to deal with all these issues. NIST, DARPA, and SEMATECH have wisely made significant investments in advanced mask technology, but there isn’t enough money available to develop a complete infrastructure for PSM, 157 nm optical masks, and four types of NGL masks within five years. Even if cash were not an issue, I don’t think the industry has enough facilities and experienced people to meet all these challenges in a timely manner.

I’m afraid the IC manufacturers will soon say to the makers of masks and mask equipment, “We’re moving PSM into the production mainstream. Within six months, we want you to be able to deliver reasonable quantities of high-quality phase shift masks at low costs with short delivery times.” Mask makers will have to launch a major development effort to create a reliable manufacturing process which can assure fast delivery of alternate aperture phase shift masks. They’ll have to learn to coat resist with low defect levels and to etch quartz in a controlled manner. They’ll need production-worthy tools for inspection, repair, and metrology. I’m not sure they can acquire all the required capabilities as quickly as the chip makers would like.

Even “simple” binary masks are confronting us with technical challenges. Mask requirements for CD control and defect sensitivity are tightening up even faster than wafer linewidths are shrinking because of the nonlinear pattern transfer that occurs at low k1 lithography. The authors of the SIA roadmap may recast the specifications for CD’s and defects as the previously

Within the mask community, we have no meaningful mechanism for limiting the scope of our R&D activity, partly because the selection of mask types hinges on broader issues such as the selection of a new lithography infrastructure. I think we have to help our customers understand that it would take ten years and a billion dollars to solve all these problems. We have to look for ways to focus and avoid working on dead ends, such as 230 mm masks and mask types that will never reach the marketplace. Together with the IC lithography community, we must realistically face the cost and time of mask equipment and process development, not just the ultimate cost of ownership of advanced masks.

We need to implement an industry-wide strategic planning process, establish a comprehensive advanced mask plan of record, and drive the creation of a compatible industry-wide funding model with firm, long term, financial commitments. I think we need to draw a cut line and say, “We’ll fund everything above this line to a successful conclusion, and we won’t work on this other stuff.” What shall we work on now? ❈ The content for this perspective was first published in the April, 1999 edition of BACUS News, to readership primarily comprised of mask manufacturers and micro-lithographers.

KLA-Tencor Trade Show Calendar December 1-3, 1999 February 2-3, 2000

SEMICON/Japan, Makuhari, Japan Display Works, San Jose, California

February 10-11, 2000

CMP-MIC, Santa Clara, California

February 15-17, 2000

SEMICON/Korea, Seoul, Korea Autumn 1999

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Analysis

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Automatic Defect Sizing Gives Near-SEM Accuracy

by Alexander E. Braun, Associate Editor, Semiconductor International

In-line defect inspection and classification’s goals are defect reduction and yield prediction. Some fabs consider all defects a problem and aim to reduce overall defectivity levels. Others focus yield prediction to enable key decisions, such as increasing wafer starts, to compensate for an expected yield loss and scrapping lots early on in the process to prevent a costly investment in wafers with low expected yield. Still others do both.

The industry has developed complex yield models to make accurate yield predictions.

These vary from fab to fab, with many customized to suit a particular IC manufacturer’s product mix and device types. Regardless of the model, however, three inputs are needed to accurately predict yield in all models: the number of defects detected in-line, their classifications and their size.

sophisticated, if the sizing is inaccurate or fudged as a default value, the model produces a “blurry” yield estimate.

Traditionally, the most accurate method to get accurate sizing data has been SEM measurement. This requires moving the wafer out of the inspector to an off-line

Today’s patterned wafer inspection tools and ADC systems have made the first two inputs relatively accurate. However, sizing is generally inaccurate and can result in erroneous yield predictions (figure 1) because fabs relied on in-line sizing outputed by inspection tools. In-line size error can vary considerably, depending on the inspector used, with darkfield tools being less accurate than brightfield. And even brightfield systems’ sizing capability is inherently limited by the inspection pixels used, which are typically large (0.62 to 0.39 µm) because of manufacturing throughput constraints associated with smaller, high-resolution pixels.

An analogy to the situation is the “image stabilization” feature in video cameras.

Before it, regardless of how good the optics, zoom, electronics, tape or other camera components were, if the operator moved while shooting, the image was blurred. Yield models are the same way: no matter how 34

Autumn 1999

Yield Management Solutions

F i g u re 1. By providing near-SEM-equivalent accuracy, the HRDC sizing module enables users to detect small sizing errors that would otherw i s e result in large yield prediction errors, leading to better processing decisions.

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SEM. This is costly in terms of throughput and possible added contamination through the extra handling.

KLA-Tencor has come up with the industry’s first defect sizing capability as an optional module for its IMPACT ADC platform. It allows users to get “common-denominator” sizing of defects detected by any inspection system. Because KLA-Tencor’s on-line High-Resolution Defect Classification (HRDC) solution classifies defects at the highest optical magnification possible, detailed size information can be extracted to provide accurate and consistent defect sizing across all inspection platforms.

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models, resulting in accurate predictions; and the ability to increase or decrease fab wafer starts based on accurate yield predictions. The system is easy to implement and will provide customizable or automatic reports. ❈ circle RS#015 Reproduced with permission from SEMICONDUCTOR INTERNATIONAL, June 1999. Copyright 1999 Cahners Business Information. SEMICONDUCTOR INTERNATIONAL is a trademark of Cahners Business Information. All rights reserved.

The HRDC can extract up to nine different size features at 0.13 µm resolution. The result is near-SEMequivalent sizing accuracy, without requiring an additional step. The advantages of this new capability are consistent sizing across different inspection tools (brightfield, darkfield, etc.); accurate input for yield

FROM THIS

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In R e c o r d Ti m e Add our yield management consulting services to your fab engineering team’s expertise.

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and random defect reduction techniques.

Giving you access to proprietary benchmark databases. Yield analysis tools. And sampleplanning software that can provide a critical edge in today’s highly competitive marketplace.

For more information call 408-875-2696 or email YMC@kla-tencor.com

Y I E L D M A N AG E M E N T C O N S U LT I N G circle RS#026

Analysis

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The Importance of Variable Wafer Tilt for Defect Classification

by Sheldon Moll, Ph.D., Consultant

The scanning electron microscope-based Defect Review Tool (DRT) has now become an essential component of a suite of instruments dedicated to Statistical Process Control in the modern fab. More recently, the tool has transitioned from an engineering-type instrument — requiring full operator attention — to a true, automated in-line monitor. The DRT supplements the laser scan or light optical image-based inspectors (defect detection tools) by performing an operator-free Automatic Defect Classification (ADC) of individual defects. It is clear that the DRT must yield highly accurate defect classifications in order to maintain high in-line yields.

F i g u r e 1. Photoresist 45 º t i l t .

F i g u re 2. Photoresist 0 º t i l t .

F i g u re 3. Photores ist 0 º t i l t shado w perspective.

Defect review tools are available today with wafer handling stages allowing variable wafer tilt, no tilt at all, or only a fixed, nonadjustable tilt. The purpose of the following information is to demonstrate the imaging improvement and consequent classification accuracy benefits which derive from a DRT wafer stage allowing fully variable tilting.

Three-dimensional perspective

A natural attribute of the SEM is its ability to form magnified images of three-dimensional objects which not only appear “natural” to the human eye, but also allow a direct, quantitative measure of their physical dimensions. An understanding of the height dimension of an object can be determined directly from a tilted view. A top-down, or untilted view, does not directly reveal the magnitude 36

Autumn 1999

Yield Management Solutions

of the object’s “z” — the height dimension of the posts.

For example, a cylinder viewed end-on appears to be a simple circle and can falsely be indentified as such.

Figure 1 is a SEM micrograph of a group of photoresist structures destined, after further processing, to become the vias of an IC. The post-like structures are readily apparent in this image taken with the wafer tilted 45º with respect to the electron beam.

Figure 2 shows the same structures with the electron beam “looking” top-down — a zero tilt orientation.

The posts appear only as reticulated ovals and the image yields no indication of their vertical profile.

It must be understood that SEM images appear as if viewed from the direction of the scanning incident beam. However, from the standpoint of dark and light areas and shadows in the image, the electron detector (or detectors) serves the eye only as the illumination source.

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F i g u re 4. ADC particle defect 0 º.

The quality of the data from a DRT production line monitor depends directly upon the accuracy of the defect classification. For example, false identification of this defect as a flake — when it is actually a multilayered particle — is clearly of little help to statistical process control.

The conical growth structure of the defect imaged in figure 6, aided in its classification from a top-down

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better accuracy in defect morphology identification and classification.

Does this mean that a DRT with only a single, non-variable tilt would be appropriate? No — such is not the case. A wafer-handling stage with a variable tilt, allowing selection of an angle specifically suited to the structure or process level to be run, is essential in many cases.

Figure 10 is a top-down (zero tilt) image of a trench exhibiting a 0.1 micrometer defect, as well as the fact that the trench is not totally cleaned out.

F i g u re 5. ADC particle defect 45º .

Image perspective may be enhanced somewhat by the presence of shadows or directional illumination. The electron detectors may be designed and arranged to produce a directional illumination or shadowing effect which would allow a moderate understanding of the three-dimensional structure even if it is only imaged in a top-down orientation.

The image in figure 3 was again obtained with no wafer tilting — but with a detector configuration which allowed some directional illumination and shadowing.

The height (z) dimension of the posts may be suspected from the shadows. Only the tilted view of figure 1 allows a clear determination of the post-like structure. A more practical example, taken from an actual ADC review, is shown in figures 4 and 5. A top-down view suggests that the defect is a simple flake-like structure, while the tilted view clearly reveals its multilayered, process-related structure.

Figures 11 and 12 show the same area at progressively higher tilts of 30º and 45º. The aspect ratio of the

F i g u re 6. ADC particle defect 45 º.

F i g u re 8. ADC stru c t u re defect 0º .

F i g u re 7. ADC particle defect 0 º.

view (figure 7), provided none of this kind of information.

The defect in the top-down image of figure 8 appears to be simply some sort of staining. When tilted, however (as in figure 9), the defect is easily seen as a three-dimensional eruption probably related to an older, sub-surface particle.

Use of selectable tilt in defect redetection

The prior information suggests that simply operating at a wafer tilt of 40º or 45º is the indicated path to Autumn 1999

F i g u re 9. ADC stru c t u re defect 45 º.

trench is such that the particle is hidden at a 30º wafer tilt angle, and an inspection at 45º would hide the incomplete cleanout. In this case, a DRT operated at a low-tilt angle would be most suited to this process level.

Yield Management Solutions

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The tilt angle appropriate for the most accurate review would seem to depend upon the wafer’s process level or CMP step. It seems clear that a DRT with only a fixed tilt stage, or one with no tilt capability at all, could not provide the flexibility to accurately review the varied defect or process problems which might be encountered in-line.

A further example of charge reduction when a surface particle was tilted is shown in figures 15 and 16.

Enhancing Electron and X-ray Emission with Tilt

F i g u re 13. ADC charging defect 0 º.

Control of Sample Charging with Tilt Charging effects in the SEM, revealed by unusual changes in image brightness apparently

F i g u re 14. ADC charging defect 45 º.

F i g u re 10. Trench defects 0 º.

F i g u re 11. Trench defects 30 º .

F i g u re 12. Trench defect s 45 º.

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Autumn 1999

unrelated to sample topology or chemistry, can cause the pattern recognition software of the ADC tool to misidentify such contrasts as defects. It is well known that tilting a sample in the SEM usually reduces electron charging and even allows the use of higher incident electron beam energies. The reason for this is quite simple. The incident electron beam entering the sample at an angle deposits its charge closer to the specimen surface, allowing buried electrons to more easily escape. Specimen charge storage and its effect upon electron emission and image brightness variation is thus reduced.

Figure 13, taken at 0º tilt, clearly shows the image brightness and contrast changes caused by the charging of a non-conductive defect as well as charging of the oxide layer of the wafer itself. Individual vias, not associated with the defect, are also imaged differently and may be falsely identified as defects.

Tilting to 45º eliminates the charging (figure 14).

Yield Management Solutions

As discussed above, when a sample is tilted with respect to the incident beam, electron penetration in terms of distance below the surface is reduced. Excited low-energy and high-energy electrons, as well as X-rays, travel shorter paths to the surface. Thus, the strength of these exiting “signals” is increased; and the information they carry is more representative of the sample surface layers, as opposed to the deeper bulk.

Figure 17 is a comparison of X-ray spectra obtained from a silicon wafer with a 0.5 µm surface particle (figure 18) of titanium silicide when the wafer was not tilted or tilted at 40º. The spectrum obtained at tilt is clearly higher in intensity, allowing better analytical sensitivity. More importantly, the

F i g u re 15. ADC charging particle 0 º.

F i g u re 16. ADC charging par ticle 45 º.

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spectrum at tilt exhibits a larger Ti/Si ratio which is more representative of the Ti silicide particle chemistry. When the specimen is not tilted, a greater excitation of the substrate yields a mixed spectrum relatively higher in Si.

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tion of thin films and foreign particulates by X-ray can also be improved by selecting the proper geometrical configuration. ❈ circle RS#031

Figure 17. Titanium silicide particle X-ray spectra 0 º (yellow) vs. 45 º (red).

Figure 18. Titanium silicide particle.

Defect at Flat view 0º Tilt

Summary

Automatic defect location and classification throughput can proceed at an appropriate rate which is independent of the tilt angle of the stage. However, the efficiency of re-detection after inspection and the accuracy of defect classification can be greatly improved for a given process level by selecting the proper wafer tilt. The chemical identifica-

Defect at Flat view 45º Tilt

Defect at 45º Tilt and 30º Rotate

H O W Y O U L O O K AT T H I N G S I S V E R Y I M P O R TA N T It can cost you time and money—or it can save you time and money.

There’s a very important new challenge in the semiconductor industry today.

challenge. The 4300+ is the only in-line ADC SEM

How to achieve superior defect imaging and the highest

capabilities. And with image acquisition of less than one

accuracy in classifications. Advanced geometries, copper

second—it’s also the fastest. For more infor-mation,

interconnects and dual-damascene processes all demand it.

please call us at (800) 225-1161, ext. 1943 or visit our website at www.kla-tencor.com.

And now the 4300+ defect review tool meets this

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available that provides both 0- 45º tilt and 360º rotation

Best of YMS

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Defect Detection for the 21st Century

by Laura Peters; Senior Editor, Semiconductor International

For defect reduction and yield improvement in the 21st century, engineers face challenges of process integration that will require a new understanding of defects. Defect complexity increases, so that no one type of inspection tool will be able to fill all the needs of defect inspection, classification and eradication.

Areas of particular concern will include new failure modes for integrated low-k dielectric and copper interconnect systems, defect examination in contracts and vias and dopant distribution control. Stress measurements may be used as a systematic process control parameter in advanced devices. These are some of the conclusions of Rajendra Singh, director of the Center of

Silicon Nanoelectronics and of Materials Science and Engineering at Clemson University (Clemson, S.C.), who presented his findings at KLA-Tencor’s Yield Management Solutions Seminar in July.

According to Singh, atomic roughness of interfaces will play a critical role in determining defect type and distribution. The ubiquitous optical microscope will be gradually replaced by optical review stations and scanning electron micro-

F i g u re 1: Trends relating pr ocess temperature and time in t e rms of stress, perf o rma nce, reliability a nd yield .

Table 1.

Potential technology solutions for patterned wafer inspection Technology node

Process R&D phase

Yield ramp phase

Volume production phase

250 nm

1994 (83 mm) Optical imaging

1996 (167 mm) Optical imaging Light scattering

1998 (250 mm) Optical imaging Light scattering

180 mm

1996 (60 mm) Optical imaging SEM-based

1998 (120 mm) Optical imaging Light scanning

2000 (180 mm) Optical imaging Light scattering Holography

150 mm

1998 (50 mm) SEM-based

2000 (100 mm) Optical imaging Light scattering Holography

2002 (150 mm) Optical imaging Light scattering Holography

130 mm

2000 (43 mm) SEM-based

2002 (86 mm) Optical imaging Light scattering Holography

2004 (130 mm) Optical imaging Light scattering Holography Novel

100 mm

2003 (33 mm) SEM-based EUV, X-ray Novel

2005 (47 mm) UV imaging UV scattering UV holography Novel

2007 (100 mm) UV imaging UV scattering UV holography Novel

Source: SEMATECH

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Yield Management Solutions

scopes, visible to ultraviolet inspection tools, and scanning probe micr oscopes.

As the industry transitions from oxynitride capacitor dielectrics in DRAMs to high-k dielectrics such as Ta2O5 and BaSrTiO3, defect characterization for amorphous materials must adapt to characterize polycrystalline materials. The composition and roughness of the metal/dielectric interface in metal gates comprised of W or W xNy become critical. Threedimensional doping profile techniques will be needed to characterize shallow junctions created by solid phase epitaxy or other methods.

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Yield Management Seminar Series A valuable venue for innovative ideas Decreasing silicon allowance for silicides places new requirements on the quality of the silicon/silicide interface for minimal roughness.

Porous low-k materials are inherently non-homogeneous in structure, unlike SiO2. Singh explained that tantalumbased barrier materials for copper may introduce stress-related reliability concerns, and pinholes and non-uniformity-related defects in barrier layers become a greater issue below 40 nm in thickness.

Table 1 illustrates the expected extension of current patterned wafer inspection methods and the timeline for bringing new technologies into R&D phases, yield ramp-up and volume production. In the interest of minimizing thermal budget, processes must be created to reduce the activation energy and use in-situ measurements to maximize performance, throughput and yield (figure 1), expecially for large diameter wafers. â?ˆ Reproduced with permission from SEMICONDUC TOR INTERNATIONAL, November 1998.

Copyright 1998 Cahners Business Information.

SEMICONDUCTOR INTERNATIONAL is a trademark of Cahners Business Information. All rights reserved.

KLA-Tencor’s Yield Management Solutions Seminars (YMS2) focus on value-added, integrated solutions for yield management and process control. Key topics include CMP, lithography, in-line monitoring and yield strategies, with an emphasis on copper.

To reserve your space at the upcoming YMS2, contact Judy Dale by email at: judy.dale@kla-tencor.com.

Date: Time: Location:

Wednesday, October 20th 9:00 a.m. to 6:00 p.m.

Hyatt Regency Austin on Town Lake

For future YMS 2, please complete and return the enclosed business reply card.

Call for future papers

Papers should focus on using KLA-Tencor tools and solutions to enhance yield through increased productivity and performance.

Topics of interest include defect inspection, lithography, CMP, film measurement and yield management strategies.

If you are interested in presenting a paper at one of our upcoming yield management seminars, please submit a one page abstract to: Judy Dale by fax at (408) 875-4144 or email at: judy.dale@kla-tencor.com.

YMS2 at a Glance DATE December 2 February 16 April 5

LOCATION Makuhari, Japan Seoul, Korea Munich, Germany

Autumn 1999

ABSTRACT DEADLINE September 1, 1999 November 1, 1999 January 7, 2000

Yield Management Solutions

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Product News eS20 Automated E-beam Inspection System

The eS20 is an automated high-speed electron beam inspection system for both R&D and in-line production wafer monitoring. Electron-beam inspection is a critical technology to address today’s yield challenges because of its ability to detect defects within high aspect ratio structures (residues, underetch, particles, stringers, etc) and defects associated with high aspect ratio fills (voids). The eS20 detects all critical defect types at all critical layers at high speed, accelerating development of sub-0.18 µm technologies and copper processes. In addition, the system provides the vital link that IC manufacturers need to develop comprehensive in-line monitoring strategies for new processes, that leverage both e-beam and optical inspection technologies. circle RS#029

HRP-240etch Automated Surface Profilometer

The HRP-240 ETCH is the latest evolution of the versatile HRP series of highresolution surface profilometers. The HRP-240ETCH measures high aspect ratio features at sub- 0.25 µm levels using a unique scanning methodology. This methodology eliminates shear on the stylus, enhancing stylus reliability and enabling the use of smaller styli. The HRP-240ETCH provides reliable, repeatable, and cost effective measurements for applications such as STI etch, dual damascene trench etch, and DRAM recess measurements. In addition to high aspect ratio depth metrology, the HRP-240ETCH builds upon field-proven capabilities in CMP polishing using its dual stage scanner for both macro and micro scanning. circle RS#005 AMRAY 4300+ Defect Reduction Tool

The KLA-Tencor 4300+ Defect Reduction Tool is an advanced, fully automated Scanning Electron Microscope (SEM) designed for defect review and analysis in a high-volume wafer production environment. The 4300+ automation feature assures optimum alignment on both patterned and unpatterned wafers. With variable wafer tilt capabilities of 0º to 45º and rotation of 360º, the 4300+ provides true-perspective images.

With optical inspection and a comprehensive defect management system, the 4300+ not only gathers defect excursion information but also analyzes and reports the results. Additionally, by porting the KLA-Tencor SEM-based IMPACT ADC onto the 4300+, the end-user realizes a significant cost-of-ownership benefit.

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8100XP-T E-beam Metrology System

The 8100XP-T offers unique capabilities to meet today’s advanced metrology requirements for thin film head wafer applications. The 8100XP-T system combines secondary and backscattered electron imaging for precise pattern recognition and focusing at zero throat with advanced measurement algorithms, for unsurpassed correlation to final electrical measurements. Reticle measurements are also possible.

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8100XP-ABS E-beam Metrology System

The 8100XP-ABS offers unique capabilities to meet today’s advanced metrology requirements for thin film head slider applications. The 8100XP-ABS system combines unique charge reduction electronics with customized handling solutions to provide state-of-the-art metrology and inspection capabilities.

With the highest throughput and lower cost of ownership, the 8100XP product family provides ideal tools for the tough demands of both manufacturing process control and engineering qualification. circle RS#004

365UV-HR High-NA UV Reticle Inspection System

The 365UV-HR meets the requirements for high volume 0.18 µm manufacturing and for the early development of the 0.13 µm generation. It allows users of current generation reticles to achieve very high defect sensitivity on critical layers, which is essential when using low and very low k1 lithography techniques. The 365UV-HR includes new high-NA optics, high-speed data preparation and rendering, plus advanced defect detection algorithms for OPC and PSM reticles.

circle RS#017

AITTFH In-line Patterned Wafer Defect Inspection System

AITTFH is the industry’s first fully automated inspection system designed to detect yield-killing defect types generated in the thin film head manufacturing process. Replacing current manual inspection methodologies, where operator’s make process control decisions based on a less than 1 percent sampling of wafers containing up to 20,000 devices, the AITTFH automatically detects and classifies critical defect types, based on full wafer inspections. This helps prevent further investment in low-yielding wafers and dramatically reduces scrap further downstream in the manufacturing process. With exceptional defect sensitivity and high throughput of 65 wafers per hour, the AITTFH allows advanced production and engineering analysis enabling the continuous process improvements required as design rules for thin film heads move towards smaller geometries. circle RS#004

2139 In-line Patterned Wafer Inspection System

Offered as a new system or as an upgrade to existing 2135/38 inspection systems, the 2139 is optimized for line monitoring applications during photolithography and etch processes, as well as for engineering analysis. With up to 20 percent higher sensitivity made possible with the addition of a new 0.16 µm pixel size, and 40 percent higher capital productivity, the 2139 extends the capability of the 2100 series for inspecting the latest generation of sub-0.18 µm semiconductor devices. Productivity improvements include job queuing, fast edge-die inspection, an easy-to-use NT user interface and recipe management software. Also available on the 2139 is KLA-Tencor’s new Real-Time Classification (RTC™) solution, which classifies defects as the wafer is being inspected.

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Yield Management Solutions

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OF COURSE WE’RE READY FOR THE FUTURE. WE’RE ALREADY THERE. Getting through today’s immense technological challenges is hard enough without worrying about what’s coming next. That’s why helping to make sure you’re ready for tomorrow’s difficult technology transitions is at the core of everything we do.

Naturally, that means we spend a lot of time thinking ahead. Way ahead. It also means we’re working with you to plan for every possible twist and turn our turbulent world can take. Not an easy task, to be sure. But with more than 20 years of designing and manufacturing the world’s highest-quality defect and metrology process control equipment, we are uniquely positioned in the industry to partner with you, and to anticipate future challenges that could affect your business. All so that when you need to make a critical move, we’re there to help, every step of the way. Time and again, that’s meant a distinct competitive advantage for our customers. And it’s been an essential component in achieving their technological and business goals. For all the ways we can do the same for you,call us at 1-800-450-5308,or visit www.kla-tencor.com.

Because no one can promise to know what tomorrow will hold.

But we can promise to help get you ready for it.

ALREADY THERE.

©1999 KLA-Tencor Corporation

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