CD SEM Measurement of Dual-Inlaid Copper Interconnect by Richard Elliott, Strategic Marketing Manager, KLA-Tencor E-Beam Metrology and John Allgair, Ph.D., Litho-Metrology, Motorola, APRDL
The introduction of copper interconnect for semiconductors presents several unique challenges for critical dimension metrology in both lithography and etch processes. The dual-inlaid process introduces multi-pattern features and higher aspect ratio structures. These dual-layer structures present new challenges to the imaging and measurement capability of the CD SEM, but also offer opportunities through new indevice measurements to collect process information that has been unavailable in conventional interconnect processing. With copper interconnect, the nature of dual-inlaid structures adds complexity to lithography and etch processing. Patterning two layers sequentially prior to metal deposition increases the aspect ratio of final structures, and forces etch depth control not previously required. Higher aspect ratio structures require thicker resists which can reduce process windows and make clearing contact holes and trenches more difficult. Metal 1 CD Via 1 CD Vi a 1 to Adjacent Metal 1 (Oxide) Space Vi a 1 to Meta l 1 Overlay To l e r a n c e Metal 1 space
In parallel to these new processing challenges, additional constraints are placed on the critical dimension metrology. The interactions now possible between the sequentially patterned contact and line layers dictate that in-device features must be measured more often or more complex duallayer test structures must be used for process control metrology. Dual-inlaid process fl
g u r e 1. Process cr iti cal imensions.
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Dual-inlaid interconnect processing represents a significant departure from conventional single-layer processing. While the metal line and via steps are completely independent in aluminum metal patterning, the two steps are combined for dual-inlaid copper. Two distinct options for the metal and via steps within the dual-inlaid process are possible: Autumn 1999
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1) The metal line areas are patterned as trenches and partially etched into the dielectric. Contacts or vias are patterned within the line trenches, then etched into the trench. The specific CD metrology challenge with this scheme is that the contact holes in resist are very deep. Excellent electron collection efficiency is required from the CD SEM in order to image and measure the holes. 2) Vias are patterned and partially etched into the dielectric. Line patterns are printed over the holes, then the lines are etched into the dielectric, and the vias are etched through the dielectric to make contact with the metal or poly below. The CD metrology challenge here is that not only are the contact holes deep, but both the linewidth and via must be measured after litho and etch. The linewidth may be in spec, but it is still possible that the contacts have not been effectively cleared. Both must be measured and controlled. Several dimensions are critical within the process flow. Figure 1 shows a cross-section diagram of the dual-inlaid structure. Metal width (1), metal space (5) and via width (2) are the CD measurements typically made in an interconnect process. Two additional critical dimensions exist in the structure — oxide space (3) and via overlay (4) —but are not generally measured in top-down SEM metrology. The oxide space (3) cannot be determined because the metal lines are not visible with an SEM through the dielectric layer. The via overlay (4) is not measured using conventional optical measurement techniques due to the complexity of the indevice measurement of a structure at the bottom of a deep contact hole. The improved capabilities in the newest CD SEMs such as the 8100XP enable automat-
ic measurements such as via overlay that have previously been impracticably difficult. CD SEM capability r
equirements
In order to measure a dual-inlaid contact hole or trench feature at litho or etch, two key attributes are required of the metrology CD SEM. First, the SEM must be able to efficiently capture electrons from deep structures to provide clear images of the bottoms of trenches and contact holes. These dual-inlaid structures can be up to twice the depth of corresponding singlelayer line or contact structures in conventional interconnect processes. A typical deep-trench structure is shown in figure 2. Second, the metrology algorithm must have the capability to exclude irrelevant edges from the analysis of the measurement scan. To measure a contact hole that is patterned in the bottom of a line trench, the trench edges must be ignored. Similarly, if the trench width is to be measured, the presence of the contact hole must be ignored. Apparent in the figure are both specific measurement challenges, a deep trench combined with additional feature edges, as well as the presence of the via space. The measurement of this via space can provide significant information that is not available from just the metal linewidth or contact opening. Adjacent interconnect leakage
One failure mechanism for interconnect failure is current leakage between two adjacent interconnect paths. A short can develop due to the confluence of several factors. A large Metal 1 or a large V1 CD will make leakage more likely. In addition, a misalignment between the Metal 1 and V1 layers can bring the oxide space (3) to a critical level. The cross-section image of the interconnect structure in Figure 3 shows the possibility of encroachment between the via and underlying adjacent metal pattern. Note that the via does not have to touch the adjacent metal line for excessive leakage to occur. If the oxide space is too small, current leaking through the space will result in a failure. This oxide space cannot be measured directly in-line — a destructive cross-section measurement is required. However, using a
CD SEM, this space can be estimated by using the metal line measurement combined with the measurement of the via to metal overlay. This measurement can be made within the actual working device, not just in a scribe line test pattern. The measurement of overlay on in-device structures requires a third unique CD SEM capability. With curved structures, the ability to obtain multiple scans over a profile and fit a curve to a device structure is necessary. This curve fit can then be analyzed to determine the maximum or minimum space. Figure 4 shows a measurement setup that can be used to measure overlap at the bottom of the patterned via. The oxide space (3) can be calculated by this formula:
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V1 space F i g u re 2. Typi cal dual-in lai d via stru c t u re .
Oxide Space (3) = M1 space (5) - Via overlay (4)
Given this in-line measurement, correlation to the cross-section measurement can be drawn, and an appropriate in-line disposition threshold for interconnect leakage can be established. Good correlation has been measured between the oxide space inferred from CD SEM measurements, and leakage currents measured at final electrical test (Reference) which verifies the in-circuit measurement capability of the 8100XP.
Oxide space
H
F i g u re 3. Cross-section of dualinlaid int erc o n n e c t .
Conclusion
Copper interconnect processing has raised new challenges for critical dimension metrology and process control. The deeptrench imaging performance and metrology algorithm intelligence of the CD SEM must be such that the complex, high-aspect ratio structures generated during dual-inlaid patterning can be measured. Hidden in this measurement challenge, however, is the opportunity to increase the value of CD metrology at the interconnect levels. Through the additional in-device measurement of via to metal overlay in combination with the traditionally measured metal and via CDs, an estimate of the propensity for interconnect leakage can be obtained. This measurement can provide valuable information towards isolating a serious yield-limiting event. â?ˆ
F i g u re 4. CD SEM image and m e a s u rement of via overlay. The blue lines indicate the locati on of the measur ed edges, while the r ed lines defin e the box in which the meas urement is confined.
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Reference Allgair, J. et. al., SPIE’s Conference on Microlithography, 1999.
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