Autumn99 measuringfab

Metrology

F

E

A T

U

R

E

S

Measuring Fab Overlay Programs

by Xuemei Chen, Senior Software Design Engineer and Rich Martin, Consultant

This article presents a methodology for measuring and improving the effectiveness of stepper overlay management on product wafers in the semiconductor industry. Measuring the effectiveness of stepper overlay management in most semicon ductor companies is generally limited to design rule compliance and/or stepper productivity issues. This paper expands on these measurements to include raw data distributions and analysis, sampling effectiveness and the level of stepper produc tivity and overlay error balance.

The research that supports the proposed measurement approach encompasses over 12 fabs with over 30 technologies. Overlay performance, stepper deployment, stepper productivity and die yield loss due to overlay error were studied. To provide an objective measurement of a fab overlay methodology and performance, measurements were made of the overall overlay design rule compliance and distribution and of the overlay variance and distribution by stepper field location. Modeled data analysis was used to assess and validate the effectiveness of the stepper control methodology, sampling level and field/target locations. Balancing stepper productivity and overlay results is a problem in most fabs. An overlay “opportunity box” is defined that allows a fab to explore overlay error ranges, lost stepper productivity, and product overlay design rule requirement by stepper deployment.

A “Fab Overlay Benchmark” database was established to provide a summary for technologies with design rules between 0.25 µm and 0.5 µm, as elaborated below.

Fab overlay benchmark database facts • 11 fabs – 7 U.S. and 4 international • 26 technologies: 0.25 µm to 0.5 µm • Calculations all done the same: - final DI raw overlay data (all test data removed) - KLASS analysis of overlay data - Overall overlay design rule compliance 22

Autumn 1999

Yield Management Solutions

- field variance and robustness by stepper development - sampling: field/target locations and robustness • Stepper productivity and overlay balance studied - overlay vs. lost fab capacity vs. stepper development The poly gate process layer was selected because this layer is the most important process layer to compare fabs and it represents the “best” printed lithography layer for overlay and CDs for most fabs.

Fab overlay measurements

Four overlay measurements are introduced: Fab Overlay Snapshot, Overlay Field Variance, Modeled Data Analysis and Balancing Stepper Productivity and Overlay Error.

These measurements are highlighted in figures 1-3, and are summarized in the following sections.

Overlay Snapshot Fab Overlay Snapshot measures the overall design rule compliance and overlay distribution. A cumulative probability plot of the individual RMS target measurements provides a fast method to look at large amounts of raw overlay data. Once the design rule limit is added to the plot, the amount of final DI data that exceeds this limit can be quantified. In addition, the shape provides information about the normality of the data; the slope provides information about the width of the distribution — the steeper the slope, the tighter the distribution.

Logic fabs performed at a variance rate range of 5 to 10 percent, while memory fabs performed better with a

F

E

A T

U

R

E

S

formance were found to have similar and overlapping overlay distributions (shapes) that were independent of wafer field location and had small differences (spread) between field distributions at the 90th percentile. The “best” performing fabs had less than 10 nm difference at the 90th percentile.

Data Analysis Modeled Data Analysis assesses and validates the effectiveness of the stepper control methodology, sampling level and field/target locations. In this study, the KLASS 4.0 software1 was applied using the KLA-Tencor stepper specific model for all modeled data analysis. The combination of the raw and modeled data analysis provides a complete measurement of a fab’s overall overlay performance.

F i g u re 1. Fab overlay “snapshot”.

variance rate range of less that 2 percent. Due to the differences in the design densities and product requirements, logic fabs tend to be more focused on critical dimension control, while memory fabs tend to focus more on overlay control.

Field Variance and Robustness Overlay Field Variance measures the overlay variance and robustness by stepper field location. From a control and die yield perspective, a yield manager would like to see the same identical raw overlay distribution at any field location on any wafer. Fabs with good overlay per-

F i g u r e 3. Field variance and ro b u s t n e s s .

This study found that the better performing fabs regularly used large volume modeled data analysis (less than 50 lots on a single product) to make overall assessments and improvements to their stepper overlay management and performance.

Sampling Plans and Measurement Locations

F i g u r e 2. Bala ncing fab producti vi ty a nd overl ay.

One interesting part of this study was the comparison of different sampling plans and measurement locations against the resultant overlay performance results. Most fabs sampled 2 or 3 wafers per lot, selected 9 to 12 field locations per wafer, and measured 4 or 5 targets per field. The most important consideration was that the selected locations predict the overlay for the entire wafer Autumn 1999

Yield Management Solutions

23

F

E

A T

U

R

E

S

with a high level of confidence. On the other hand, as the overlay metrology cost of ownership is one of the lowest in a wafer fab (a “cost per wafer pass” of about $0.75), overlay is one of the lowest fab expense items. Besides, the “time to results” (measurement and analysis) to double the sampling size from 10 to 20 fields requires less than 2 additional minutes per wafer. Once a wafer is in an overlay metrology system, the fab should sample enough to make good decisions with the results.

Balancing Stepper Productivity and Overlay Error The Balancing Stepper Productivity and Overlay Error function measures the level of balance, compromise and opportunity of the fab overlay methodology, which represents one of the key fab financial decisions — lost fab capacity (stepper restrictions) verses overlay error (lost die yield). Stepper deployment options are plotted against the expected 3-sigma overlay errors and the approximated lost fab capacities. The expected stepper error ranges are calculated RMS values based on the stepper vendor specifications and deployment options.

The lost fab capacities are approximations using queuing curves 2 based on difference deployment options. The accuracy of the queuing approximations for a given fab can be improved by comparing lot cycle times of layers with and without stepper deployment restrictions.

These cycle time results can then be used to provide a more custom lost fab capacity model for that particular fab. The addition of the product design rule to the plot defines an overlay “opportunity box”. This box was used to compare actual and expected (calculated) level of balance between stepper productivity and the 3-sigma overlay error range.

In the case of stepper deployment changes, it is important to understand die yield loss as a function of overlay error. ❈

Improvements”, Proceedings of 7th Annual IEEE/SEMI ASMC Conference, Cambridge, MA, 1996.

1. KLA-Tencor, KLASS 4.0 for Windows User Guide, P/N: 990-452376-00, San Jose, CA, 1996.

This article is based on the paper: R. Martin, X. Chen and I Goldberger, “Measuring Fab Overlay Programs”, Proceedings of SPIE, Vol. 3677, 1999.

2. L. Sattler, “Using Queueing Curve Approximations in a Fab to Determine Productivity

cir cle RS#038

4 out of 5 Perfectionists Insist On VLSI’s Thin Film Metrology Standards.

If you’re responsible for thin film thickness measurements, you want them to be right. And you definitely don’t want to be embarrassed by a metrology tool that decides to drift at a critical time.

That’s why perfectionists insist on VLSI’s suite of thin-film metrology standards. For silicon dioxide and silicon nitride. The broadest selection in the industry.

And now, oxide standards are available for 4.5nm and 7.5nm! It’s a VLSI exclusive.

So if you’re a metrology perfectionist, flaunt it! Call now for your free “Good Enough ISN’T” button along with your free VLSI catalog...

VLSI Standards: (800) 228-8574.

Or on the Internet: www.vlsistd.com

The Measurement Standards for the Industry

24

.