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Thin is In Solving the Challenges of Thin Film Metrology at 65 nm and Beyond Arun R. Srivatsa, KLA-Tencor
Shrinking process windows and a variety of new materials and processes associated with the transition to 90 and 65 nm technologies, as well as the stringent requirements and costs associated with 300-mm manufacturing, place new demands on thin film process control and necessitate the migration to increasing on-product metrology. This article reviews both recent advancements in spectroscopic ellipsometry, as well as new techniques that enable semiconductor manufacturers to meet the thin films process control challenges of 65 nm and beyond. Introduction
With each node, windows for critical processes such as anti-reflective coatings (ARCs) and gate dielectric thickness continue to shrink. A rule of thumb is that the metrology error should not exceed 10 percent of the process window; consequently, metrology windows continue to shrink, increasing the demands on tool matching and repeatability. At the 90 nm and 65 nm nodes, we also see the introduction of a variety of new materials1-4 and processes, placing new demands on thin film process control. These include the introduction of siliconon-insulator (SOI) and silicon germanium (SiGe) based substrates, high-k-based capacitor dielectric stacks, heavily nitrided oxides for gate dielectric, low-k dielectrics, and copper metallization in the back end. The cost of 300 mm wafers, the desire for “lights-out” fabs, and chemical-mechanical planarization (CMP)-driven requirements necessitate a migration to increasing on-product metrology. On-product metrology implies more multi-layer, multi-parameter measurements without compromises in the metrology window for each layer. Spectroscopic ellipsometry (SE) is the “workhorse” of the semiconductor industry to control a variety of deposition, etch, and CMP processes in both the front end and the back end. This article reviews both recent advancements Winter 2005
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