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S O L U T I O N S Yield Acceleration Strategies for the Semiconductor Industry

SPECIAL ISSUE: ISSUE: A Focus on Lithography 15 15 COVER COVER STORY STORY — — A N A AUTOMATED UTOMATED M METHOD ETHOD FOR FOR AN O OVERLA VERLAY Y SAMPLE AMPLE P LAN LAN O OPTIMIZATION PTIMIZATION 38 38 E EFFECTIVE FFECTIVE D DEFECT EFECT M MANAGEMENT ANAGEMENT IN IN THE LITHOGRAPHY ITHOGRAPHY CELL CELL THE L 50 SPECTROSCOPIC PECTROSCOPIC C CRITICAL RITICAL DIMENSION IMENSION (SCD) METROLOGY ETROLOGY FOR FOR CD CD C CONTROL ONTROL AND STEPPER TEPPER CHARACTERIZATION HARACTERIZATION AND S

Speci al

Focu s

UV Inspection of EUV and EPL Reticles Inspection of EUV and EPL reticles pose several technical challenges and risks to todayâ&#x20AC;&#x2122;s mask makers. This study demonstrates the feasibility of optical inspection of Next Generation Lithography (NGL) reticles at the 100 to 140 nm nodes, and offers recommendations for changes in mask design that can optimize their inspectability.

25 A Defect-to-Yield Cor relation Study for Marginally Printing Reticle Defects Reticle defects can play a significant role in overall device yield; however, some marginally printing mask errors may not actually result in yield loss. The challenge is to detect and quantify the impact of these marginally printing reticle defects. This study examines several available methods. 32 Investigation of 193 nm Resist Shrinkage During CD SEM Measurements 193 nm resists are known to shrink during CD SEM measurements. The large size and non-linear behavior of this shrinkage must be characterized and understood if CD SEM metrology is to be correctly applied in advanced lithography processing. This paper describes a study in which recommendations for the best measurement conditions were developed, along with speculations on possible models for the observed shrinkage mechanisms.

15 An Automated Method for Overlay SamplePlan Optimization

38 Effective Defect Management in the Lithography Cell Technology advances within the lithography area are placing greater demands on defect management. The introduction of sub-wavelength, low Îş1lithography has shrunk the size of the focus-exposure process window and thus has placed tighter constraints on absolute tool stability within the litho cell. Effective defect management is critical when new processes are combined with these strict operating conditions.

Tighter design rules and process complexities have made effective sample planning a necessity for todayâ&#x20AC;&#x2122;s fabs. Through quantitative analysis and modeling, this paper demonstrates an automated and systematic approach to identifying the optimal sample plan. Validated with fab results, the methodology proves to be successful not only in improving stepper control accuracy, but also in reducing yield loss and unnecessary rework.

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Cover image by Mike Garnica and Carlos Hueso, KLA-Tencor

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50 Spectroscopic Critical Dimension (SCD™) Metrology for CD Control and Stepper Characterization Smaller device dimensions and tighter process control windows force CD metrology tools to detect and measure changes in feature profiles that are becoming critical to inline process control and stepper evaluation for sub-0.18 µm technology. Spectroscopic CD is an optical metrology technique that can address these needs. 56 Using Pattern Quality Confi rmation to Control a Metal-Level DUV Process With a Top-Down CD SEM As critical-feature patterning processes increase in complexity and sensitivity, conventional CD measurements may not afford the level of process control required for effective device production. By comparing recorded top-down SEM images to a predefined reference image, Pattern Quality Confirmation (pQC) enables a more detailed analysis of measurements captured by KLA-Tencor 8xxx series CD SEMs.

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64 AIT XP High-throughput scanning for inspecting patterned wafers Surfscan SP1 DLS Unpatterned-wafer inspection system for 0.13 and 0.10 µm design rules 65 iADC Inline Automatic Defect Classification Component of IMPACT XP SpectraCD Non-destructive Critical Dimension Metrology System 66 PRECICE In-situ Film-Thickness and End-Point Control for Cu CMP ASET-F5x Wafer Bow Wafer Stress Capability (WBWS) Film and Stress Metrology for 300 mm Monitor Wafers Klarity ACE 5.5 Advanced Correlation Engine Advanced Yield Analysis Software 67 Printability Analysis Stepper Simulator Characterize and Simulate Printability of Defects on Advanced Photomasks PROLITH 7.1 Advanced Optical Lithography Simulation Advanced Optical Lithography Modeling Capabilities Yield Management Solutions is published by KLA-Tencor Corporation. To receive Yield Management Solutions, contact Corporate Communications at: KLA-Tencor Corporation 160 Rio Robles San Jose, CA 95134 Tel 408.875.3000 Fax 408.875.4144 www.kla-tencor.com

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Editorial: The Changing Role of Inspection and Metrology in Lithography

For literature requests, call: 800.450.5308

12 Yield Management Seminar Series

©2001 KLA-Tencor Corporation. All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation. Products in this document are identified by trademarks of their respective companies or organizations.

24 Spotlight on Lithography 49 Got a Litho Question? Ask the Experts 62 KLA-Tencor Trade Show Calendar Fall 2001

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Editorial

The Changing Role of Metrology and Inspection in Lithography Metrology and inspection have been called “non-valueadded” operations in the past, but it is clear that any fab that does not use these tools effectively will see significant losses in yield, bin-sort performance, scrap, and rework. Inspection and metrology’s role has become one of “non-value-subtracted,” as well as one of real value added. Like defect inspection, metrology is a strategic weapon for competitiveness, and for process capability and viability. Especially in lithography, where the small and shrinking process window creates challenges in manufacturability, a fab must view metrology as part of the overall lithography system.1 Metrology provides the visibility to understand where the optimum process lies, and where it is moving. Inspection and measurement provide information that helps engineering to map out the process’s response surface, and also provides confidence in the shape of that surface. This provides the context for yield learning, which is defined as yield improvement rate, or the change in average yield over a period of time, typically one month. (This may also be applied to rework or scrap.) To positively and predictably impact yield, the process engineer must understand the components which contribute to yield loss. The best practices among fabs include a prioritization of the yield detractors, and then focussing on improving or fixing the top detractors. It is only by reducing the impact of each 1 Ashkenaz, Scott, editorial in YMS Summer 2000, Vol 2, Issue 3

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(and moving it to the end of the Pareto chart) that predictable progress can be made. In the case of metrology, it is also essential to define a budget. For example, many fabs are struggling to fit their process into a 40 nm or 50 nm overlay budget, without a full understanding of each component of the budget. As described above, with the budget defined (along with the proper way to statistically combine the components), it then becomes easy and obvious where to focus improvement resources. This issue of the Yield Management Solutions magazine illustrates many of the ways that inspection and metrology are used in lithography and other process modules to bring the process into focus, and to assist in improving it, with great economic benefit for the fab. Overlay is proving to be one of the major challenges for 0.13 µm design rules (not to mention for 0.18 µm). KLA-Tencor, working with several fabs, has identified the impact of improper sampling for overlay estimation. In some cases, common (improper) sampling across a wafer can consume 25 nm out of a 40 nm budget, and can cause several percentage points of yield loss! However, by doing a proper systematic analysis, this sampling bias can be reduced below 10 nm or less. Defect issues in the litho cell are well beyond the point where manual inspection can provide useful information. While defect reduction methodologies are well established in all other process modules in the fab, lithography has lagged in best practices for defect yield learning;

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S O L U T I O N S

EDITOR-IN-CHIEF Uma Subramaniam MANAGING EDITOR Siiri Tuckwood

this is in part due to the ongoing reliance on manual inspection. Fabs that have implemented photocell monitoring (PCM) and macro ADI, along with defect reduction methods, have seen dramatic improvements in overall manufacturing costs. Another area where metrology can provide significant cost benefit is in offloading time-consuming and costly self-test operations of process tools. KLA-Tencor and ASML have worked together to provide a solution that reduces the non-productive time of the stepper/scanner, resulting in higher litho cell productivity, without significant impact on metrology productivity. While inspection and metrology do help to identify and lessen the impact of process excursions by providing quick response, they also are now essential in making progress with yield learning. It is through the intelligent application of cost-optimized sampling and the structure of proper process models, that the process engineer may identify critical defects or variation sources, identify their causes, and move them lower in the Pareto chart. Without these tools, analyses and actions, manufacturing costs would be higher. The best-known methods described in this issue show how inspection and metrology have become “non-value-subtracted.”

C ONTRIBUTING EDITORS Scott Ashkenaz Aparjot Dehal Indira Rangarajan Dave Hattorimanabe Tom Salinas A R T DI R E C T O R A N D P RODUCTION MANAGER Carlos Hueso D E S I G N C O N S U LTA N T Michael Garnica C I R C U L AT I O N E D I T O R Rolando Gonzalez

KLA-Tencor Worldwide C O R P O R AT E H E A D Q U A RT E R S

KLA-Tencor Corporation 160 Rio Robles San Jose, California 95134 408.875.3000 I N T E R N AT I O N A L O F F I C E S

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The Editors

KLA-Tencor (Israel) Corporation Migdal Ha’Emek, Israel 972 6 6449449 KLA-Tencor Japan Ltd. Yokohama, Japan 81 45 335 8200 KLA-Tencor Korea Inc. Seoul, Korea 822 41 50552 KLA-Tencor (Malaysia) Sdn. Bhd. Johor Bahru, Malaysia 607 557 1946 KLA-Tencor (Singapore) Pte. Ltd. Singapore 65 782 6788 KLA-Tencor Taiwan Branch Hsinchu, Taiwan 886 35 335163 KLA-Tencor Limited Wokingham, United Kingdom 44 118 936 5700

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Lithography S

UV Inspection of EUV and EPL Reticles Donald W. Pettibone, KLA-Tencor Corporation Alan R. Stivers, Components Research, Intel Corporation P. J. S. Mangat, Motorola *DigitalDNAâ&#x201E;˘ Laboratories Michael Lercel, NGL MCoC, Photronics/IBM Anthony Novembre, Bell Laboratories, Lucent Technologies

A UV inspection tool has been used to image and inspect Next Generation Lithography (NGL) reticles. Inspection images and simulations have been used to provide feedback to mask makers so that inspectability of NGL masks can be optimized. SCALPEL masks have high optical contrast and look much the same in reflection as conventional chrome-on-glass masks do in transmission. EPL stencil masks can be imaged well in reflection, but defects below the top surface (in the cutouts) may not be detectable optically. EUV masks made to date tend to have relatively low contrast, with line edge profiles that are complex due to interference effects. Simulation results show that improved EUV inspection images can be obtained with a low reflectivity absorbing layer and the proper choice of buffer layer thickness.

Introduction

A partnership, partially sponsored by NIST-ATP Cooperative Agreement #70NANB8H44024, has been formed to retire the technical risks associated with optical inspection of EUV and SCALPEL reticles. The members of this partnership are KLA-Tencor, Lucent Technologies, the EUV-LLC, Photronics, and Dupont Photomasks. The EUV-LLC is comprised of AMD, Infineon, Intel, Micron, and Motorola. In addition, Motorola has provided SCALPEL masks to the program. This program has three phases, each about one year in duration. In the first year, KLA-Tencor built a research tool and gathered information to support modeling efforts. In this, the second year, we are imaging and inspecting NGL reticles. The main goal this year is to establish the feasibility of optical inspection of NGL reticles at the 70 and 100 nm nodes. In the third year, KLA-Tencor plans to design a production prototype inspection system for NGL reticles. 6

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The emphasis to date in this program has been on providing feedback to mask makers so that mask design can be optimized for inspection. A number of NGL reticles have been imaged with a specially modified UV inspection system. Based on images and simulation results, recommendations have been made for changes in mask design that can improve the inspectability of NGL masks. Images and preliminary inspection results on some NGL masks will be presented in this paper. Simulations have been carried out which indicate that EUV masks can be optimized for inspectability. In particular, the absorber reflectivity at the inspection wavelength should be minimized, and the buffer layer thickness can be chosen to improve contrast. Research tool description

The research tool used in these studies is based on a KLA-Tencor high-NA UV inspection system. The operating wavelength is 364 nm, with a minimum pixel size of 150 nm. The system has been modified to accept all NGL reticle types. Due to the fact that NGL reticles do not have pellicles, special care has to be taken to avoid contaminants. A reticle SMIF pod developed by Asyst Technologies can be used to keep the reticles clean when not undergoing inspection. A transfer station has been built to transfer reticles from the SMIF pod to special

adapters that are mounted in the inspection tool. New computing capabilities have been added to the research tool, resulting in improved defect sensitivity, which is needed to meet the defect sensitivity requirements of NGL. NGL images and inspection results

SCALPEL SCALPEL (Scattering with Angular Limitation Projection Electron-beam Lithography) is an Electron Projection Lithography (EPL) technology developed by Lucent Technologies1. The mask is constructed from a 200 mm diameter silicon wafer on which a thin silicon rich nitride (SiN x) layer, typically 100 nm, and a metal scattering layer, typically 30 nm of tungsten (W) and chromium (Cr), are deposited. The silicon wafer is patterned and etched to produce areas of freestanding membranes. The remaining silicon substrate forms a grillage structure and provides support and mechanical strength (Figure 1). The mask pattern is etched into the metal (scatterer) layer and the mask is imaged in transmission by scanning a 1 mm x 1 mm 100 kV electron beam along the membrane stripes, with adjacent stripes being stitched together at the wafer. The mask image is projected with 4X-reduction electron optics onto a resist-coated wafer. At UV wavelengths the membrane is transparent, so defects on the backside of the membrane are visible provided they are not behind the metal pattern. The SCALPEL masks that were tested had trapezoidal struts that were wet etched. This permits inspection in either reflection or transmission mode. However, it is highly desirable to have vertical wall struts so as to maximize the usable space on a mask, which will be based on a 200 mm wafer when SCALPEL goes into production. Vertical struts pose an inspection problem for transmission imaging or for imaging from the backside (strut side) of the mask, the front side of the mask having the metal scatterer on it. This is because the vertical walls vignette the high-NA components of the light that are needed to obtain good resolution and high defect sensitivity. This results in spatial variations

of both resolution and image intensity, with up to 75 percent loss of light at a corner of two intersecting struts. Therefore, reflection imaging from the front side of the mask is the preferred inspection mode for vertical strut SCALPEL masks. We report here inspection results for three SCALPEL masks. The first, SCALPEL1, designed and fabricated by Lucent Technologies, is made up of a stack of 27 nm of Won six nm of Cr on a 100 nm SiNx membrane, with the substrate being a four-inch silicon wafer. The struts are formed by an anisotropic, wet potassium hydroxide etching of <100> Silicon wafers. The membranes are 1.1 mm by 12.1 mm on a side. The base pattern of this programmed defect mask is a wiring pattern comprised of 3.0-micron lines and spaces. There are three types of defects: a bridge between lines, a break of a line, and a pindot between lines, at seven different nominal sizes ranging from 200 nm to 800 nm in 100 nm increments. Figure 2 shows reflection and transmission images of the smallest pindot. The contrast of the defect observed in reflection mode is about twice that observed in transmission. The wiring pattern exhibits good contrast to noise in both reflection and transmission. The line edge profiles are monotonic, with no edge ringing in the reflection image. This is due to the fact that the SCALPEL mask stack is thin compared to a wavelength, about one-tenth of a wavelength at UV. Inspection results are shown in Table 1. All but the smallest defects were found consistently in the six transmission inspections that were run.

Transmission

Reflection

F i g u r e 2. UV images o f Lucent SCALPEL mask with 200 nm nominal pind ot defect.

Type/Size 200 nm 300 nm 400 nm 500 nm 600 nm 700 nm 800 nm Bridge

Break

Spot

Tabl e 1. SCA LPEL1 in spec tio n results ( 6 inspections, transmission). F i g u re 1. SCALPEL mask layout and cr oss sect ion.

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Reflected

Transmitted

40 nm

80 nm

120 nm

160 nm

40 nm

Nominal Sizes

80 nm

120 nm

160 nm

Nominal Sizes

F i g u re 3. SCA LPEL2 mask (Pho tronics /MCoC), defects A1, A3 , A5,

F i g u re 4 . SCALPEL3 mas k (Mo torola), d ef ec ts A1, A3, A5, A7 ,

A7, 400 nm L/S.

20 0 nm L/S.

The second mask, SCALPEL2, was made by Photronics/ MCoC. It has a programmed defect pattern designed by KLA-Tencor on a four-inch silicon wafer with trapezoidal struts. The mask stack is 27 nm of W on five nm of Cr on a 150 nm membrane of SiNx. There are 14 defect types at ten different defect sizes. Figure 3 shows a series of pinhole defects in a wiring pattern of 400 nm lines and spaces, which would print on the wafer at 100 nm lines and spaces. The nominal defect size in these defects ranges from 80 nm to 320 nm in 80 nm increments. The defect visibility is better in the reflection images than in transmission.

obtain mask contrast. We have imaged one stencil mask made by Photronics/MCoC (Figure 5). The reflection image of the top surface of the stencil mask shows good contrast and resolution. The transmission image shows poorer resolution and very low signal levels, on the order of a few percent. Therefore, it is likely that stencil mask inspection may not be possible using an optical system because defects that are not near the top surface of the

The third mask, SCALPEL3, made by Motorola, has the same programmed defect pattern as SCALPEL2, though it also includes the patterns scaled to smaller sizes. It is based on an eight-inch silicon wafer with trapezoidal struts. The mask stack is 30 nm of tantalum silicon nitride on 10 nm of Cr on a 100 nm SiNx membrane. The base pattern shown in Figure 4 has 200 nm lines and spaces, which would print as 50 nm lines and spaces on the wafer. The nominal defect size in these defects ranges from 40 nm to 160 nm in 40 nm increments. Again, better contrast is seen in the reflected images.

Transmission, high contrast

In summary, SCALPEL masks, in reflection, look much the same as conventional chrome on glass masks do in transmission. The programmed defects we have studied to date show better visibility in reflection than in transmission. Programmed SCALPEL defects in the 100 to 140 nm size range are visible.

EPL Stencil Masks One type of EPL uses a stencil mask and images transmission electrons through the mask to the wafer with a 4x reduction.2 However, unlike SCALPEL, which uses a scattering layer to obtain mask contrast, stencil cutouts are made through a 2.0 Âľm thick silicon membrane to 8

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Reflection

F i g u re 5. Stencil mask ( Ph otronics/MCoC), reflection and transmission images , 400 nm line widths .

mask may not be detectable at the needed sensitivity levels. More work needs to be done to verify this.

EUV A general description of EUV lithography is provided in Reference 3. EUV masks are made at 4X, and are composed of an absorbing metal layer on top of a buffer layer on top of an EUV reflecting mirror (Figure 6). This mirror is composed of alternating layers of Si and molybdenum (Mo), and typically forty pairs of layers are used to obtain a reflectivity of approximately 65 percent at the EUV wavelength of 13.4 nm. The buffer layer is there to prevent damage to the multilayer during the absorber etch process and mask repair process. The patterned EUV masks are first inspected for hard defects after the absorber etch. The defects are then repaired, and the buffer layer is subsequently etched. A second inspection is performed after the buffer layer is etched. The absorber and buffer layer height add up to an optical path difference (OPD) of between approximately

Nominal Size(nm)

F i g u re 6. EUV mask cross section.

120 nm to 180 nm, which is of the order of one-half of the UV or DUV inspection wavelength. Therefore, in reflection inspection images, the OPD difference between light reflected off of the absorber and light reflected off of the ML is about one wavelength. This rapid phase variation typically results in a pronounced dark fringe in the inspection image at the absorber-ML edges, unless the reflectivity of one of the materials is much higher than the reflectivity of the other. This effect will be discussed in the section on optimization of EUV masks. The first mask we inspected, EUV1, was designed and made by Intel, and has a programmed defect pattern with wiring and contact defects of varying types and sizes. The mask stack has 105 nm of titanium (Ti) absorber, on 85 nm of silicon dioxide (SiO2) buffer layer, on a silicon wafer substrate. Silicon is a reasonably good match to the EUV multilayer in terms of UV reflectance. The SiO2 has been etched on this mask, so it is only present under the absorber layer. Figure 7 shows reflection images of an absorber protrusion defect in the 400 nm/800 nm line/space pattern. The defect is 0.5-microns wide and protrudes into the space a distance of 80 nm, 100 nm, 140 nm, and 200 nm. The Protrusion A defect sizes have been confirmed with SEM measurements. Note that all of the defects are visible in the images. The dark fringes mentioned earlier are evident in these images. Inspection results for the 400/800 line/space pattern are shown in Table 2. Defects towards the bottom of the table that were not detected were checked with a SEM. These defects were shown to be either undersized or to have not resolved on the reticle at

PA 08 (80 x 500 nm)

PA10 (100 x 500 nm)

PA14 (140 x 500 nm)

Type Intrusion A Intrusion B Protrusion A Protrusion B Space Wiring Bridge Corner Hole 1 Corner Hole 2 Corner Hole 3 Hole 2 Hole 3

200

140

100

6 6 6 6 6 6 4 6 6 6 3

6 6 6 6 6 4 0 0 0 0 0

0 5 6 6 5 0 0 0 0 0 0

0 0 0 4 0 0 0 0 0 0 0

Table 2. EUV1 inspection results, 6 inspections, 400 nm lines/800 nm spaces.

Another mask, EUV2, was made by Motorola. The mask stack is 30 nm of Cr on 100 nm of silicon oxynitride (SiON) on 10 nm of Cr, on a Si/Mo reflective multilayer. The buffer layer (SiON) has been etched. In Figure 8 we present images of a 400 nm L/S test pattern. In this image a 4X blow-up of five lines is shown. Dark interference fringes around the Cr absorber lines are evident. We used TEMPEST, a software program that solves Maxwellâ&#x20AC;&#x2122;s equations for the case of monochromatic radiation incident upon a scattering structure in concert with aerial imaging software from Panoramic Technology5, to calculate and simulate the UV inspection image of EUV2. This simulated image is also shown in Figure 8, and we can see that the dark fringes are predicted by the simulation. In the next section, these simulation tools are used to understand and optimize the absorber line edge profiles, leading to improved inspectability of the EUV masks. Optimization of EUV masks

Work in the area of optimizing EUV mask inspectability has been done by Tejnil and Stivers 6. This work has focused on finding materials with good contrast. In

PA20 (200 x 500 nm)

F i g u re 7. EUV1 mask (Intel ), pro t rusion defect images . 4X Blowup

all. For the defects that were well resolved on the reticle, we were able to repeatedly detect defects in the 100 nm to 140 nm size range.

TEMPESTsimulation F i g u re 8. EUV2 (Motorola) images and TEMPEST simulation, 400 nm L/S.

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F i g u re 9. TEMPEST simulati ons of Ultraviolet High Resolution (UV HR) lin e profi les of absorbers of var ying reflectivity and width.

addition to the mean contrast of the absorber material being an important factor, the rapid phase ramp of the reflected light due to the mask topography significantly impacts the visibility of the absorber lines during inspection. In Figure 9 we show simulated images from a set of absorber lines of varying width. The lines have a width of, from left to right, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, and 500 nm. These simulations were run with the absorbing material being either Cr or titanium nitride, and with an absorber height of 50 nm, with no buffer layer under the absorber. The Cr has a reflectivity of 0.66 (in thick sections) and the TiN has a reflectivity of 0.22, both at a wavelength of 364 nm. The multilayer reflectivity has been taken to be 0.50. We can see how the edge interference changes the appearance of the line images. In the broad lines the Cr is brighter than the multilayer, as expected from their relative contrast. As the line narrows, the dark fringes merge and we undergo a contrast reversal. This makes it difficult to interpret the images. The *ave greater visibility than the Cr lines. Further simulations have been carried out which indicate that an absorber reflectivity of ten percent or less would be very desirable in terms of improving the line visibility. Conventional masks that use Cr with an antireflection coating can achieve such a low reflectivity. It is worth noting that it is somewhat easier to find candidate absorber materials with low reflectivity at DUV wavelengths than at UV wavelengths. When the buffer layer is present, its thickness can be optimized for maximum line image contrast. In Figure 10 we show simulations of a constant width absorber 10

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line on varying heights of buffer layer, ranging from 40 nm to 80 nm in 10 nm steps. We see that the visibility of the line is a strong function of the height of the buffer layer. This effect is easily explained by the reflected light interference that happens when a small scatterer is positioned above a mirror that is normally illuminated. Interference minima occur when the scatterer is positioned at half-wave multiples above the mirror, and maxima are a quarter-wave away. The buffer layer height is thus an important variable that needs to be controlled to optimize line visibility. Summary

In this paper we have demonstrated the feasibility of optical inspection of EUV and SCALPEL masks. We have imaged masks made by several sources and carried out limited inspections of the masks that had programmed defects. SCALPEL and EUV mask defects in the range of 100 to 140 nm were consistently detected. In order to meet the stringent ITRS roadmap requirements for defect sizes that are 80 nm at the 100 nm node and 55 nm at the 70 nm node, we will extend this work to DUV (257 nm wavelength) inspection in the coming year. We will also optimize the defect detection algorithms specifically for EUV and SCALPEL reticles to further improve sensitivity. We have supported NGL mask development with images and inspections from the research tool. A valuable collaboration has been established that provides rapid feedback to the mask developers based on the mask images and inspection results.

F i g u re 10. T E M P E S T simulation of var ying b uf fer layer t hickness.

Using simulation tools and inspection images, we have found that EUV mask inspectability may be optimized. Specifically, it is desirable that the mask absorber reflectivity at the inspection wavelength be reduced to approximately 10 percent. In concert with this, the mask buffer layer thickness can be optimized so that the absorber visibility is enhanced.

for work on the EUV1 mask and for helpful technical discussions. Finally, we would like to thank Yalin Xiong, Jacobus Koster, and Matt DiLorenzo of KLA-Tencor Corporation for their technical support of the research tool used in this work.

EPL stencil masks may not be inspectable optically. The problem is that very little light is transmitted deep into the membrane cutouts, so that if a defect were to be 1 to 2 microns below the surface of the mask, it would not be visible in an optical inspection image. This should be regarded as a tentative conclusion since we have only inspected one such mask.

1 . J. A. Liddle, et al, “The SCALPEL Lithography System”, Japan. J. Appl. Phys., 34, 12B, 6663 (1995). 2 . Hans C. Pfeiff e r, “PREVAIL - IBM’s E-Beam Technology for Next Generation Lithography”, SPIE Vol. 3997, 206 (2000). 3. John E. Bjorkholm, “EUV Lithography - The Successor to Optical Lithography?”, Intel Technology Journal, Q3’98. 4. A l f red K. Wong, “Rigorous Three-dimensional Ti m e - D omain Finite-Difference Electromagnetic Simulation”, Ph.D. d i s s e r-tation, Engineering- Electrical Engineering and Computer Sciences, University of California at Berkeley, 1994. 5 . Panoramic Te c h n o l o g y, www. p a n o r a m i c t e c h . c o m . 6 . Edita Tejnil and Alan R. Stivers, Components Researc h , Intel Corporation, private communication.

At DUV wavelengths the SCALPEL membrane is nearly opaque. This poses a problem for inspection of backside SCALPEL defects. As mentioned earlier, vertical wall struts hamper inspecting SCALPEL masks in transmission from the frontside or in reflection from the backside. If front side optical inspection at UV or longer wavelengths proves not to be sensitive enough to detect printing backside defects, it may be necessary to develop another inspection technique for backside inspection. Acknowledgements

The authors would like to thank Bing Lu and K. Smith of the Motorola *DigitalDNA™ Laboratories, and PSRL, Motorola Labs, Tempe AZ for making NGL masks used in this work. We would also like to thank Edita Tejnil, Components Research, Intel Corporation,

References

A version of this ar ticle was originally published in SPIE Pro c e e d i n g s 4186, pp. 250-258 (2001) entitled “UV Inspection of EUV and SCALPEL Reticles” by Donald W. Pettibone, Noah Bareket, KLA-Tencor Corporation; Ted Liang, Alan R. Stivers, Components Research, Intel Corporation; Scott D. Hector, P. J. S. Mangat, Motorola * DigitalDNA Labs.; D. J. Resnick, PSRL M o t o rola Labs.; Micheal Lercel, Mark Lawliss, Chris Magg, NGL M C o C , P h o t ronics/IBMN; Antho ny N ovembre, Reginald Farro w, Bell Labs, Lucent Te c h n o l o g i e s .

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Yield Management Seminar A valuable venue for innovative ideas KLA-Tencor’s Yield Management Seminars (YMS) focus on value-added, integrated process module control solutions for defect reduction, process parametric control and yield management. Key topics include navigating the transition to the sub-0.13 µm technology node, with special emphasis on copper/low-κ interconnect, sub-wavelength lithography, and the 300 mm wafer. To register online for the upcoming YMS, please visit us at: http://www.kla-tencor.com/seminar Date: Wednesday, October 17, 2001 Time: 10:00 am – 6:00 pm Location: Four Seasons Hotel, Austin, Texas

Call for future papers Papers should focus on using KLA-Tencor tools and solutions to enhance yield through increased productivity and performance. If you are interested in presenting a paper at one of our upcoming yield management seminars, please submit a one-page abstract to: Cathy Silva by fax at (408) 875-4144 or email at cathy.silva@kla-tencor.com.

YMS at a Glance

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October 17

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December 6

Makuhari, Japan

February 6

Seoul, Korea

Spring 2001

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An Automated Method for Overlay Sample Plan Optimization Xuemei Chen, Moshe E. Preil, KLA-Tencor Corporation Mathilde Le Goff-Dussable, Mireille Maenhoudt, IMEC, Leuven, Belgium

In this paper, we present an automated method for selecting optimal overlay sampling plans based on a systematic evaluation of the spatial variation components of overlay errors, overlay prediction errors, sampling confidence, and yield loss due to inadequate sampling. Generalized nested ANOVA and clustering analysis are used to quantify the major components of overlay variations in terms of stepper-related systematic variances, systematic variances of residuals, and random variances at the wafer, field, and site levels. Analysis programs have been developed to automatically evaluate various sampling plans with different number of fields and layouts, and identify the optimum plan for effective excursion detection and stepper/scanner control. For each sample plan, the overlay prediction error relative to full wafer sample is calculated, and its sampling confidence is estimated using robust tests. The relative yield loss risk due to inadequate sampling is quantified, and compared with the cost of sampling in determining a cost-optimal sampling plan. The methodology is applied to overlay data of CMP processed wafers. The different spatial variation characteristics of oxide and metal CMP processes are compared and proper sampling strategies are recommended. The robustness of the recommended sample plans was validated over time. The sample plan optimization program successfully detected process change while maintaining accurate and robust stepper/scanner control. Introduction

Shrinking design rules and increasing process complexity have imposed tighter tolerance on overlay control. The number of transistors on a single wafer is increased by more than a factor of four due to increasing wafer size and shrinking feature sizes. In addition, the effects of process non-uniformity coming from deposition and polishing become a significant part in the total overlay budget. As a result, accurate characterization and effective reduction of the variation components of overlay errors, especially spatial variation across a wafer, becomes essential to achieving maximum net good dice per wafer1, and hence yield. Adequate and cost-effective spatial sampling is, therefore, required to detect process excursions and provide confident assessment of the systematic and random components of overlay errors for effective process control. With the increased data points of interest and process complexities, a systematic and automatic sampling optimization approach is necessary. In this paper, we describe an automated method for overlay spatial sampling plan optimization based on spatial variation analysis, overlay prediction error minimization, sample confidence tests, and yield modeling. The optimized sampling plan Fall 2001

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achieves a balance between the following objectives in overlay control: • It selects fields that minimize overlay prediction errors while maintaining adequate sampling confidence for lot disposition. • It quantifies the major components of overlay variations in terms of variance components, stepper/scanner correction parameters, and spatial signatures of interfield residuals. • It quantifies the impact of sample plans on yield risk and cost reduction. • It is robust enough to detect process changes over time while maintaining accurate stepper/ scanner control. In the following sections, we present the strategies and analysis modules used to achieve the above goals, and validate the methodology with applications to overlay data of CMP processed wafers. Overlay field selection strategy

The diagram in Figure 1 summarizes the inputs, analysis modules (with sub-modules), and outputs of the automated sample plan optimization program. Overlay data is collected using a KLA-Tencor 5xxx overlay metrology tool for three to five lots, five to seven wafers per lot, with every field measured at a given layer on a specific product from a stable process flow. Spatial variation analysis is applied to the full-wafer data to provide a comprehensive characterization of the overlay variance components and process signatures. Such decomposition of overlay errors into sources of variances provides guidelines for selecting fields that reduce overlay prediction errors and are least affected by process induced nonlinear errors. The full-sample overlay measurements are then used as reference data 16

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for evaluations of overlay prediction errors and sampling confidence for each sub-sampling plan as specified in a text file. Finally the yield modeling module estimates the risk/cost impacts of sampling plans. The program iteratively applies these analysis modules to the sub-sample plans and identifies the optimal sample plan that achieves minimal overlay prediction errors, sufficient sampling confidence, and minimum yield loss. A summary chart is then generated, which indicates the key metrics used in the optimization of sampling plans of different number of fields and spatial layouts.

Spatial variation analysis of overlay errors As the major objectives of overlay sampling are excursion detection and variation reduction through proper stepper/scanner correction, a comprehensive understanding of the sources of variation in the baseline process is essential. Table 1 summarizes the typical sources of overlay variation from a physical point of view. As shown, overlay variation exhibits itself in several dimensions (systematic vs. random; spatial vs. temporal) at a number of different scales (lot-to-lot, wafer-to-wafer, field-to-field, and site-to-site). Proper decomposition of the measured variations into these meaningful components enables us to allocate the sampling and process

control efforts more appropriately. Specifically, systematic variations can be reduced or compensated by applying proper stepper/scanner matching and correction, and improving process uniformity; whereas random variations can be reduced by timely detection of excursions at the appropriate time-space scale, and reducing the sources of uncertainties accordingly. Using similar concepts as in this section, we have developed a “generalized nested ANOVA” model for overlay to effectively quantify the source components of overlay variation as tabulated in Table 1. Compared to conventional nested ANOVA, the generalized nested ANOVA method is effective in decomposing what might otherwise be taken as random noise with large variance into separate systematic and random contributions at specific scales. The spatial variation analysis module includes applying the generalized nested ANOVA to both raw overlay data and the residuals after stepper/scanner correction. First, the total systematic and random components in the raw overlay data are separated at the site-to-site, fieldto-field, and wafer-to-wafer levels. Then a spatial regression model (commonly known as the stepper correction model) is fitted to the raw data to remove the systematic variations due to stage and lens distortions in the exposure system. This results

F i g u re 1. In put/out put stru c t u re and analysis modules of the sample plan optimizati on pro g r a m .

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Table 1. Decompos iti on of sources of over lay vari ations into t ime-s pace an d s ystematic-ra ndom component s a t diff e rent scales.

in residuals that contain systematic variations induced by process nonuniformity, other systematic variations not accounted for by the regression model, and random variations. The generalized nested ANOVA is then applied to the residuals to assess the remaining systematic field-to-field and site-to-site variations, the former being characteristic of the process signatures while the latter being indicative of the lens and reticle signatures. Combining results from the aforementioned two-step generalized ANOVA, a complete decomposition of spatial variations of overlay errors is obtained. An example is shown in Figure 2a. (As the data used in this example are from a single lot, no systematic wafer-to-wafer

variance can be calculated in this case.) As indicated by the figure, after removal of the systematic stepper errors, a large portion of the systematic field-to-field variance remains, reflecting the spatial characteristics of the process layer, as shown by the vector plot of interfield residuals in Figure 2b. The process signatures are useful not only for process diagnosis, but also for selecting sample field locations that are least biased by nonlinear process effects, hence reducing the overlay prediction errors, as calculated in the prediction error evaluation module. Figures 2b and 2c illustrate a clustering analysis of the interfield residuals. In Figure 2c, the cumulative probability curve of the interfield residuals is plotted.

F i g u re 2 a. Spatial variation decomposition of overlay

data.

F i g u re 2 b. Spatial signatures of interfield residuals.

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The curve has three distinctive slopes, which indicates multiple mode distribution of the interfield residuals. The transition points in the cumulative probability curve separate the fields into clusters, which form spatial zones in the vector plot, as indicated by the color codes in Figure 2b. Fields in zones 1 and 2 are less affected by nonlinear process effects, while fields in zone 3 are most affected by the process nonuniformity. Including fields from zone 3 would bias the estimates of stepper/scanner correctibles, and should be avoided in a sampling plan that aims to have minimum overlay prediction errors. Our analysis showed that in a stable

F i g u re 2 c. Clustering analysis of interfield

residuals.

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process, field-to-field variation is the major variance component of overlay errors. As indicated in Figure 2a, it is significantly larger than wafer-towafer and site-to-site variation. This forms the basis for us to focus the overlay sampling optimization at the field-to-field level, i.e., determining the optimal number of fields and spatial layouts for overlay sampling. However, if the wafer-towafer or lot-to-lot variations are significantly larger in an unstable process, it will be necessary to understand the root cause and pattern of such variations, and focus the sampling efforts to the reduction of variations over time. Nevertheless, the spatial variation analysis method presented in this study can still be used in such situations to assess the variation components and the changes in the spatial signatures of the process, and would be a useful tool for process diagnostics.

Overlay prediction errors evaluation Ideally, the most accurate stepper correction can be obtained by sampling every field in the wafer. However, this is not realistic. In this study, we try to find the sub-sampling plans that best approximate the full wafer-based correction. First, the fullwafer overlay data is modeled to produce a reference estimate of the true stepper/scanner correctibles. Subsets of the data are extracted to represent various sampling plans according to a sample plan specification. Each sub-sample data is modeled to generate the sub-sample estimates of stepper/scanner correctibles (all of the modeling is done using standard overlay models contained in the KLA-Tencor overlay analysis software). These estimates are then used to predict overlay errors at every site on the wafer, and the difference in the predicted overlay errors based on full-wafer and sub-sample model estimates is referred to as the overlay

prediction error. The maximum overlay prediction error across a wafer is estimated by adding the mean prediction error and three sigma of the residuals based on each sample plan. In Figure 3, the effects of sampling plans on overlay prediction errors are shown in a summary chart. In this chart, the maximum overlay prediction errors relative to the full wafer sample are plotted for different sampling plans. The x-axis lists the different sampling plans evaluated, with the first point being the full wafer sample, which has a prediction error of zero. From left to right, the maximum prediction errors for sample plans with increasing numbers of fields are plotted. For plans with the same number of fields, different field locations are also evaluated, and the layouts that yield the best and worst prediction errors are highlighted with their field location maps and other decision metrics. As can be seen, as the number of fields increases, the overlay prediction errors converge to that of the full wafer sample. By increasing the number of fields from four to 12, the overlay prediction error can be reduced by more than half. In addition, there is a larger variation in the prediction errors with respect to field locations for

smaller number of fields than for larger number of fields. Even though it is possible to find a sample plan that gives small prediction errors with fewer fields, such a plan would be more susceptible to variations at the field locations used. As shown in later sections, such a plan may not meet the other criteria used in the sample plan optimization, and may have insufficient sampling confidence and robustness with respect to process change. Besides the maximum overlay prediction errors, the summary chart in Figure 3 also indicates the other metrics used in the sample plan evaluation: p-values of robust tests and estimated yield loss. As discussed later in the paper, for the example data, a sampling plan with eight or more fields, including fields from the edges and center would be recommended to achieve better than one percent relative yield loss at an overlay tolerance of 50 nm. The effectiveness of variance reduction based on each sample plan can be assessed by examining the residuals resulting from the stepper/scanner correction. In Figure 4, we plot the three-sigma values of residuals across wafers, for each sample plan. As shown, selecting fields that min-

F i g u re 3. Summar y chart of samp ling p lan opti miza tion.

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plish the objectives of exposure tool control and lot disposition.

Yield implications of sampling plans

F i g u re 4. Res idua ls result ing from sa mple plan o ptimiza tion.

imize the overlay prediction errors yields residual distributions comparable to full wafer fit. The overlay data used in this example exhibit higher variations in the Y direction than in the X direction. Optimal sampling plans should minimize the residual distributions in both directions. Minimizing the magnitudes of the overlay vectors can effectively achieve this requirement, as was done in this study. The total prediction errors of sampling plans can be attributed to errors in estimating individual stepper correction parameters, as shown in Figure 5.

Sampling Confidence Tests Lot disposition decisions are usually based on an evaluation of the sample overlay distributions. It is, therefore, important that the sample data be representative of the full wafer overlay. In other words, the probability distributions of the sample data and the full wafer data should not be significantly different at a desired confidence level. We use robust tests (also called non-parametric tests) to ensure that the optimal sample plan provides sufficient confidence for lot disposition. Median tests are used to compare the centers of the sample and full-wafer distributions; dispersion tests are used to compare the spreads of the two distributions.

Both tests donâ&#x20AC;&#x2122;t assume normal distributions for the data being compared, and hence are suitable for overlay data, which contain higher systematic variances. If the p-value of such test is less than 0.05, the null hypothesis that the two samples are the same can be rejected at the 95 percent confidence level. An optimal plan should satisfy both tests. Example results of dispersion tests applied to different sampling plans are shown in Figure 6. At 95 percent confidence level, any plan that falls below the horizontal line is unacceptable, meaning it has a significantly different probability distribution than the full wafer data set. The p-values of robust tests are also indicated in the summary chart shown in Figure 3, and are combined with the overlay prediction errors in the optimization program to select plans that accom-

The impact of sampling plans on yield is twofold: on one hand, cost-optimal sampling plans that effectively detect variance excursions can reduce the material at risk (yield loss) and unnecessary rework (opportunity cost). On the other hand, adequate spatial sampling provides accurate characterization of the systematic variation components; hence it improves the feedback control of the processes and enhances yield. As discussed before, the sample plan optimization program selects fields that minimize the overlay prediction errors relative to full wafer sampling. Overlay prediction errors due to inadequate sampling would result in inadequate stepper correction and thus higher overlay errors. The yield loss due to inadequate spatial sampling of overlay can be estimated as in Figure 7a. Here we define net yield loss due to overlay as the average percentage of sites cross a wafer that have overlay errors exceeding the design tolerance. Using a full-wafer overlay data set, we apply various sampling plans, and calculate the stepper correction parameters based on each sampled data set. The cumulative probability function of overlay errors cross wafers is then calculated after applying the stepper correction based on each sample plan. As shown in Figure 7a, for a given overlay tol-

F i g u re 5. Over lay prediction err ors attributed to err or s in estimating individ ual correction coeff icients based on ea ch samp le p lan.

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F i g u re 6: Disp ersion tests of sampling pl ans

erance, the stepper correction based on the full-wafer sample plan results in the lowest yield loss, whereas the overlay distribution without applying any stepper correction has the highest yield loss. Any sub-sampled plans (e.g. Sample Plan i) would result in a net yield loss between these two bounds. The difference between the yield loss of full-wafer sample plan and that of the sub-sample plan, denoted as relative yield loss in Figure 7a, is indicative of the yield loss due to inadequate sampling. Based on the above assumptions, we calculate the relative yield losses as a function of overlay sampling plans and tolerances. The relationships are shown in Figure 7b. As design rules

shrink, the yield loss due to inadequate sampling increases significantly. More sample fields are required to meet tighter overlay tolerance. In this example, for an RMS overlay tolerance of 85 nm or greater, all sample plans can achieve a relative yield loss of better than two percent. However, as the overlay tolerance shrinks, the difference in yield loss between fullwafer and sub-sample plans increases sharply. Only those sampling plans with 12 fields or more can achieve relative yield loss of less than two percent for tighter overlay tolerances. Fewer field plans, for example, four-field plans, result in insufficient stepper correction and the resulting overlay errors can only meet an overlay tolerance of greater than 70 nm.

F i g u re 7 a. Model of yield loss due to inadequate overlay sampling.

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With this yield model, we can also relate the estimated yield loss to overlay prediction errors, as shown in Figure 8. Yield loss increases exponentially as overlay prediction errors increase due to insufficient sampling. This implies that, for an overlay RMS tolerance of 50 nm, a sampling plan with a prediction error of no more than 10 nm is necessary to achieve a yield loss of less than one percent. This can only be achieved by sampling eight or more fields as the summary chart in Figure 3 suggests. In this way, the yield loss reduction achieved by better sampling is quantified, and a cost effective sampling plan can be identified by weighing the increased yield loss risk against the cost of in-creased sampling (using Figure 8 and 3). It is worth noting that a one-percent reduction in yield loss (material at risk) could result in significant financial returns. For example, if we assume that a fab has 7000 wafer starts per week, with a $5000 value for each wafer, and a 40 nm overlay budget, then a one-percent yield loss reduction has a revenue potential of $19 million per year. As design rules shrink, the yield benefits of effective sample planning can be much higher. On the other hand, the overlay metrology COO (cost of ownership)

F i g u re 7 b. Impacts of sampling plans increase as overlay tolerance shrinks.

This case study validated the benefits of the sample plan optimization approach in characterizing variation components and identifying sampling strategies based on spatial process characteristics.

Robustness of sampling plans

F i g u re 8. Estimat ed yi eld impact of overlay p rediction erro r.

is one of the lowest in a wafer fab. This is due to low capital costs, low operational expenses and high wafer throughput. At a “cost per wafer pass” of about $0.75, overlay is one of the lowest fab expense items. In addition, the “time to results” (measurement and analysis) to double the sampling size from 10 to 20 fields requires less than two additional minutes per wafer. Once a wafer is in an overlay metrology system, the fab should sample enough to make confident overlay control decisions, with minimal yield loss impact due to inadequate sampling. With the automated, systematic approach developed in this study, we can quantify the various decision variables, and optimize the sampling strategy to achieve tighter design rules with lower yield loss risk. Fab results

Optimizing overlay sample plans for CMP processed layers Using the analysis modules described above, we evaluated the sampling strategies for CMP processed wafers. Full-wafer overlay data was collected for the same product at several layers to compare the effects of oxide CMP and metal CMP. An ASML PAS5500/300 stepper was used for the experiment, and the ASM run model in the

KLA-Tencor KLASS 4 software was used to estimate the stepper correction models. Spatial variation analysis and overlay prediction error evaluation results are shown in Figure 9. As can be inferred, the major differences between oxide CMP and metal CMP include: • With metal CMP, the proportion of site-to-site variance relative to field-to-field variance is much higher than the oxide CMP layer, also the variances have more random components than systematic components (whereas other layers show more systematic variances) • Intrafield modeling errors for metal CMP are higher compared to oxide CMP, and are more sensitive to sample field locations • Interfield residuals of metal CMP are more symmetrically distributed across the wafer with radial variation, whereas oxide CMP exhibits localized pattern • With fewer-field sample plans, there is a larger variation in overlay prediction accuracy with respect to sampling plans for metal CMP than for oxide CMP processed wafers. Sampling plans with more fields are required for metal CMP processed wafers to achieve the same overlay prediction errors as oxide CMP. Fall 2001

As the sample plan optimization method developed in this study is based on full-wafer measurements at one point in time, it is important to evaluate the robustness of the spatial sampling plans over time, in terms of stepper control accuracy and process change detection. We measured split lots over time to assess (1) if the best sample plans with different number of fields identified initially can maintain small overlay prediction errors; (2) if the spatial variation analysis can properly detect any process change. In Figure 10, the standard deviations of the overlay prediction errors for split lots processed over a year are plotted for the best sample plans with various numbers of fields. As the result suggests, stepper corrections based on sample plans with fewer fields are more susceptible to being biased by process variations at the field locations sampled. The robustness of optimal sampling plans improves with increased number of fields, and a minimum number of fields need to be measured to assure the robustness of sample plans in the long term. Spatial variation analysis as shown in Figure 11 indicates that the method is effective in detecting and characterizing process changes. Two lots—lot A and B processed before and after a process improvement—are analyzed. The variance decomposition indicates significant reductions in the systematic variances of residuals and random variances, implying the effects of process improvement. The change in systematic variances attributed to stepper errors is relatively small, which indicates a stable stepper control during

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F i g u re 9. Over lay samp le p lan optimi zation for oxi de and tun gsten CMP pr ocessed wafers.

the experiment period. The spatial variation decomposition method developed in this study properly separates the systematic and random contributions from stepper and other processes, and is a key building block for an effective sample plan strategy. Conclusion

Through quantitative analyses and modeling, we demonstrated that more effective sample planning is a necessity

for a fab to meet tighter design rules and achieve robust stepper control with reduced material at risk. We have developed an automatic and systematic approach to identify the optimal sample plan, with the proper number of fields and spatial layout, based on comprehensive components, overlay prediction errors, sampling confidence, and relative yield loss due to inadequate sampling. The methodology proved to be effective and robust

over time in detecting process change and maintaining accurate stepper control. References 1 . W.H. Arnol d and J. Gre en ei ch, “ Im p a c t of S te p p e r O v e r l a y o n A dva nc e d D e si gn Rul es ” , OCG M i c rolithography Seminar Pro c e e dings, pp. 87-105, 1993. 2 . R. Elliott, R. K. Nurani, D. Gudmundsson, M. Preil, R. Nasongkhla, and J.G. Shanthikumar, “Critical Dimension Sample Planning for sub-0.25 micron Processes”, in the proceedings of Advanced Semiconductor Manufacturing Conference and Workshop, p.139-142, September 1999. A version of this article was originally presented at SPIE Conference, February 25 - March 2, 2001, Santa Clara, California, USA. as Chen, X., Preil, M., Le Goff-Dussable, M., Maenhoudt, M., “An Automated Method for Overlay Sample Plan Optimization Based on Spatial Variation Modeling,” Metrology, Inspection, and Process Control for Microlithography XV, SPIE 4344-31, 2001.

F i g u re 10. Robust ness of overlay pre d i c t i o n

F i g u re 11. Spa tial variat ion analyses of l ots

e rrors of optimal sa mpling p lan s.

in dic ating process impro v e m e n t .

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complexity. As a result, in a 6-month period, engineers were able to move from zero yield on one of every four devices manufactured to finding every critical reticle defect. And bring their 0.13µm ramp yield issue under control faster and more efficiently than they ever thought possible. To see what you’ve been missing, please visit www.kla-tencor.com/tera, or call 1-800-450-5308. ©2001 KLA-Tencor Corporation

Accelerating Yield

Critical Dimensions and the Feature Model With fear of stating the obvious, the measurement of a lithographic feature size, or critical dimension (CD), is, well, critical. The issues of measurement precision and accuracy, especially in an environment without established standards, present a complex picture to the metrology tool user. To help bring clarity to one small piece of the bigger CD measurement puzzle, I’d like to discuss an important issue that rarely receives attention: the feature model. Our discussion will center around the measurement of long line- or space-type patterns in lithography, but the concepts apply broadly to any CD measurement. A cross-section of a photoresist profile has, in general, a very complicated two-dimensional shape (see Figure 1, for example). Measurement of such a feature to determine its width has many complications. Let’s suppose, however, that we have been able to measure the shape of this profile exactly so that we have a complete mathematical description of its shape. How wide is it? It takes only a little thought to realize that the answer depends on how you define the width. The original shape of the photoresist profile is simply too complex to be unambiguously characterized by a single width number. The definition of the width of a complex shape requires the definition of a feature model1. A feature model is a mathematical function described by a conveniently small number of parameters. For our application, one of these parameters should be related to the basic concept of the width of the resist profile. The most common feature model used for this application is a trapezoid (Figure 1). Thus, three numbers can be used to describe the profile: the width of the base of the trapezoid (linewidth, w), its height (profile thickness, D), and the angle that the

side makes with the base (sidewall angle, q). To be perfectly general, the position of the feature (defined, for example, by the centroid Chris A. Mack, of the feature model) can be KLA-tencor specified and the shape can be made asymmetrical by allowing a different sidewall angle for each side. Obviously, to describe such a complicated shape as a resist profile with just three numbers is a great simplification. One of the keys to success is to pick a method of fitting this feature model to the profile that preserves the important properties of the profile (and its subsequent use in the device). Thus, we can see that, even given an exact knowledge of the actual photoresist profile, there are two potential sources of error in determining the critical dimension: the choice of the feature model and the method of fitting the feature model to the resist profile. Consider Figure 2, which shows resist profiles through focus exhibiting different curvatures of their sides. Using a trapezoidal feature model will obviously result in a less than perfect fit, which means that the criterion for best fit will influence the answer. What is the best feature model and best method of fitting the feature model to measured data for a given application? I’ll discuss this issue in the next edition of this column. References: 1 . SEMI Standard SEMI P35-0200E, Te rminology for M i c rolithography Metro l o g y.

F i g u re 1. Ty pical phot ores ist pr ofile and its correspon din g “best

F i g u r e 2. Resist profiles at the extremes of focus show h ow the

fi t” tra pezoi dal feature model.

c u rv a t u re of a pattern cross-s ecti on can cha nge.

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Lithography S

A Defect-to-Yield Correlation Study for Marginally Printing Reticle Defects Jeff Erhardt, Khoi Phan, Eric Backe, Quang Tran, Beverley Fletcher, Advanced Micro Devices C. Bradford Hopper, Spotfire Systems Ingrid Peterson, Aaron Zuo, KLA-Tencor Corporation

This paper presents a defect-to-yield correlation for marginally printing defects in a gate and a contact 4X DUV reticle by describing their respective impact on the lithography manufacturing process window of a 16 MB Flash memory device. The study includes site-dependent sort yield signature analysis within the exposure field, followed by electrical bitmap and wafer strip back for the lower yielding defective sites. These defects are verified using both reticle inspection techniques and review of printed resist test wafers. Focus/Exposure process windows for defect-free feature and defective feature are measured using both inline SEM CD data and defect printability simulation software. These process window models are then com pared against wafer sort yield data for correlation. A method for characterizing the lithography manufacturing process window is proposed which is robust to both marginally printing reticle defects and sources of process variability outside the lithography module.

Introduction

High yield for a leading edge, sub-0.25 µm technology depends greatly on the manufacturing process window at critical lithography layers. This process window can be strongly impacted by marginally printing, or “soft” reticle defects. Two hurdles must be overcome when evaluating a new product mask: the first is the ability to detect errors on the reticle, and the second is to understand the yield impact of any defects. There are several ways in which lithography engineers attempt to characterize the impact of reticle errors on the manufacturing process window. As a first step, the manufacturer can use reticle inspection tools, such as the KLA-Tencor STARlight™ system, to detect the existence of reticle defects. After the reticles are received in the fab, the fab engineer can use automated defect inspection tools to review printed wafers. While these methods may be successful in identifying possible errors, the

yield impact of these defects can be difficult to quantify. The printability of reticle CD errors depends not only on the defect size, but also on the shape and proximity to other features. Moreover, it is likely that the effect of these defects is influenced both by product-specific sensitivity and interaction with non-lithography process modules. It is important, then, to develop robust techniques for detecting and characterizing the true process window of marginally defective reticles. Problem background

During the course of normal yield analysis, several lots were found to have a reticle site-dependent yield signature in which one of eight production die (site 7) had considerably depressed yield, as shown in Figure 1. It was immediately suspected that some sort of reticle defect was responsible for these repeated failures in site seven. Consequently, an effort was mounted to repeat the incoming Quality Check (QC) procedure for critical layer reticles of this particular product. The QC procedure consists of reviewing all critical reticles and test wafers printed from these masks for defects. This process did not reveal any obvious errors. Fall 2001

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F i g u re 1. Normalized distribution of functional die by reticle site for a typical lot. Si te 7 sho ws dramaticall y l ower y ield.

While the initial lithography investigation was ongoing, product engineering continued with end-of-line failure analysis. The analysis included using a custom test program that allowed the bit-level failures to be aggregated across multiple non-functional die. The output from this program indicated that, for site 7, two locations consistently failed more often than the rest, as illustrated in Figure 2. Taking note of these failing bit locations, chemical deprocessing of these wafers was carried out. Figure 3 shows the results of the strip-back process which revealed a single undersized contact that appeared likely to be the cause of the yield loss.

F i g u re 3. Wafer strip-bac k SEM revealed an undersized contact.

memory product reticles. The second goal was to understand the reasons for the shortcomings in quality control of incoming reticles. The final goal was to assess the impact of these defects on the process window in order to estimate the potential yield loss for the wafers already in progress. The first repeater defect was found on a post-gate etch product wafer. Though the standard defect scan by KLA-Tencorâ&#x20AC;&#x2122;s 2132 inspection system at gate resist mask and after etch failed to detect the repeater defect, a technician was able to identify it during a manual SEM review. Following this operator feedback, a Photo Track Monitor (PTM) was run using the gate mask. The Photo Track Monitor (PTM) or Photo Cell Monitor (PCM) is commonly used as a lithography

F i g u re 2. Orig inal electrical test r esults showing two columns fail dras tic ally mo re often tha n a ll others.

Lithography Analysis

Before the strip-back analysis was complete, the intra-field site-dependent yield information and bitmap coordinates were used to launch a lithography investigation. The first goal was to locate the repeater defect on the flash 26

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F i g u re 4. KLA-Tencor 2132 defect map for gate PTM (lef t) and K L A - Tencor 8100 SEM image of the ga te maskâ&#x20AC;&#x2122;s repeat er defect.

F i g u re 5. Proc es s wind ow si mul atio n of non-defec tiv e and de fecti ve gate f ea tures u sing Av a n t i â&#x20AC;&#x2122;s Aeri al Image Ana lysis s oft ware on Sta rl i g h t S L 3 optica l i mages.

defect monitor and new reticle qualification check. The PTM sequence uses patterned photoresist on a flat silicon wafer followed by automated die-to-die defect inspection. Since this defect was caused by CD variation, the PTM wafer needed to be slightly underexposed to make the printing worse and, therefore, easier for the inspection tool to detect. In addition, the 2132â&#x20AC;&#x2122;s sensitivity for the PTM recipe was increased to a setting much higher than that commonly used for product wafer inspection. This was possible because the printed resist-on-silicon wafer had a much better signalto-noise ratio than the topographically diverse product wafers. Figure 4 shows the resulting defect map and SEM image of the CD variation defect.

for non-defective and defective features, using this simulation software. While the gate mask investigation was in progress, strip-back analysis determined that the electrical failure was in fact due to an undersized contact. Similar to the defective gate case, a contact reticle error was not detected either before or after etch on product wafers. Further more, the standard contact PTM with resist pattern on silicon did not detect this defect. However, with the aid of bitmap coordinates and SEM images from the strip-back analysis, the 2132 recipe was re-optimized to the highest sensitivity to achieve successful detection. Again, this high-sensitivity recipe could not be used for product wafers due to excessive background

After this first repeater defect was identified, the gate reticle was re-inspected through the pellicle using the STARlight SL3 reticle defect inspection tool. The defect was much easier seen in reflection mode compared to transmission imaging. This is common for repairs, since they leave a stain easily apparent in the reflected image. The reticle was then sent back to the mask vendor and SEM measurements confirmed the defect to be a repair. Once the defect image is captured by the STARlight inspection system, printability simulation can be used to predict how features and defects on the reticle will print on actual wafers. 1, 2 The reduced process window for the gate defect was simulated in this manner, using transmission data from the STARlight scan. Figure 5 shows the comparison of predicted process windows

F i g u re 6. KLA-Tencor 2132 defect map for contact PTM waf er showing und ers ized contact.

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F i g u r e 7. Proces s window simulation for non-defective a nd defective contact feat ures using Av a n t ! ’s Aerial Image Ana lys is software on KLA -Te n c o r ’s 353 optical ima ges.

noise. Figure 6 shows the defect map for a contact PTM wafer with the repeater defect successfully detected. As demonstrated by the strip-back results, the defect in this case was a single undersized contact. Since this defect was not contamination, the STARlight SL3 contamination inspection tool did not detect this defect as would be expected. The reticle was subsequently sent to KLA-Tencor to be inspected using die-to-die mode on KLA-Tencor’s 353UV tool. This pattern inspection successfully detected the undersized contact. As in the gate case, the printed CD difference between nondefective and defective contacts was simulated using results from the STARlight scan. An example of the process window estimation by aerial image simulation is shown in Figure 7 using Avant! software in conjunction with the 353UV reticle transmitted image.

the actual functionality of the die, allowing an evaluation of the true process space when the lithography defect is combined with inline process variation outside of the lithography module. Figure 8 shows the Focus/Exposure CD graph for the defective gate feature with overlaid process window for non-defective and defective features assuming ±10 percent CD control. This graph shows a significant reduction in the allowable process window for the defective feature compared to all others. Note, however, that a small process space exists which allows within-specification printability of non-defective and defective features on the same wafer. Inline SEM images were taken to compare non-defective and defective gate pattern features at opposite ends of the focus spectrum for worst case

Experiment

Once the presence and location of the reticle defects was confirmed on the printed Photo Track Monitors, a correlation study was run to compare the available detection methodologies. The study compared the predicted results from the lithography simulation software, inline defect inspection, and develop inspection CD measurements on printed FEM (Focus Exposure Matrix) wafers. To enable the yield comparison, an identical focus exposure matrix was run on the defective layers using full-flow production wafers. These electrically testable, product-based FEM wafers enable comparison between the empirically measured process window and 28

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F i g u re 8. Focus/exposure process window for CD defect on Poly mas k DUV resi st wa fer.

F i g u re 9a. Electrically tested end-of-line process space for non-defective

F i g u re 9b. Electrical ly tested end-of-line process space for defective

die on gate-lay er pro duction FEM wafers.

exposure conditions. Though the printability of this defect was noticeably worse at positive relative focus, it did not appear to cause a silicon bridge at masking or after etch.

best opportunity for successful processing of both features occurs at a normalized dose of 1.12 and focus of 0.3.

After running the gate-layer focus exposure matrix, the product wafers received standard processing through the end of the line. The wafers were then electrically tested to determine the functionality of the product die. The results of this electrical testing are shown in Figure 9. In the figures, each pie icon represents the sort-bin distribution of all die processed at a given focus/exposure combination. Figure 9a includes all die with no repeater defects, and Figure 9b includes those with the known reticle error. Within each array, the approximate process window for functional die is highlighted in bold. From these maps, we can see that, although the functional process space for the defective die is reduced, a significant process window remains intact. Next, a similar product wafer focus exposure matrix was run using the defective contact layer reticle. Figure 10 shows the Focus/Exposure CD graph for the defective contact with overlaid process window for non-defective and defective features assuming Âą10 percent CD control. In contrast to the gate defect case, this inline CD measurement suggests that there is no possible process that will allow in-spec printing of both the non-defective and the defective feature. According to this measurement, the

After completion of the inline analysis, the contact layer FEM wafers were finished with standard processing followed by electrical testing. Figure 11 shows the distribution of sort results for these wafers. The functional yield for all known non-defective die and the defective die is shown in Figures 11a and 11b, respectively. In contrast to the defective gate case, there is almost no allowable process window for this reticle error. The single functional point on the defective die occurs at a relative dose of 1 at nominal focus.

F i g u re 10. Focus/Exposure process window f or defective featur e on Contact mas k DU V r esis t wa fer.

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F i g u re 11a. Electrically tested en d-of -line process spa ce for non-

F i g u r e 11b. Electrica lly tested end-of -lin e process spa ce f or defec tive

defect ive di e on contact-layer productio n FEM wafer s.

di e on contact-layer productio n FEM wafer s.

Discussion

the simulation results, there should be no allowable process space for this reticle sizing error. The yield results agree, exhibiting only a single functional die at the center point of the contact masking process.

Recall that this investigation began with a single electrical failure and the subsequent detection of a single gate-layer repeater defect. It was not until after the precise location of the failure was determined electrically that the problem was confirmed to be due to a contact mask error. The known presence of two reticle errors, one subtle and the other slightly more obvious, along with one gross electrical failure, presented an ideal opportunity to study the process window of these defects and analyze why neither problem was initially caught. For both the defective gate and contact cases, the inline process window measurement and the printability simulation correlate very well to the end-of-line yield. Using the criteria that the lithography must allow simultaneous in-spec processing of both non-defective and defective features, the inline gate CD measurement predicted that successful printing was possible within a reduced window. Likewise, the simulation results predict the existence of an overlapping process window. In fact, the product wafer yield results agree with both of these estimates. As predicted by the inline product wafer CD measurement, the defective die yield is enhanced at higher exposure doses. As the lithography process moves toward the opposite end of the window, the defective dieâ&#x20AC;&#x2122;s yield begins to fall off while the non-defective die continue to yield. The contact example tells a similar story. According to both the inline measurements and 30

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Reticle-quality verification faces two major hurdles. The first is to determine the existence and location of the reticle defect; the second is to quantify its impact on the functionality of the device. This exercise has suggested that inline characterization techniques can do a reasonable job of predicting the yield impact of a known reticle defect. However, it says nothing about the ability to detect these subtle errors in the first place.

F i g u re 12. A t iered appr oach to reticl e-quality verification.

As we have seen here, the currently installed tools for reticle and patterned-wafer inspection gave mixed results in the ability to reliably detect these defects. The newergeneration inspection tools, however, have been shown to detect this class of defects reliably. More importantly, the wafers inspected typically represent only one point in the allowable process space and exclude any variability outside of the lithography module. To address these issues, the use of electrically tested product FEM wafers has proven very useful. The product based Focus Exposure Matrix provides valuable information at several levels. First, for reticles with more than one die per field, it provides process sensitivity information at the functionality level. Second, at the bit level, this technique can help to identify specific defect hot spots. Both of these outputs evaluate the full range of lithography process variation as well as interactions with other process modules. Conclusion

Reticle defects can play a significant role in overall device yield. However, some “soft” mask errors may not actually result in yield loss. Detecting and quantifying the impact of these marginally printing reticle defects poses a significant challenge. This work has examined several of the methods available to identify and evaluate these types of defects. It has shown those early detection techniques such as printability simulation and inline CD measurement correlate well with end-of-line yield. However, these techniques are obviously useful only after defects are successfully detected. Finally, the use of electrically tested product wafer FEMs at critical lithography layers has proven to be very valuable for in-depth product characterization. To overcome the limitations and build on the strengths of each of these characterization techniques, we propose the implementation of a tiered approach to new productmask evaluation. Figure 12 illustrates how each of these methods might be implemented in different

phases of the product development lifecycle, where each tier acts as a screening step for the next. At the mask shop, reticle scans coupled with printability simulation provide the first layer of defense. Once the masks are received in the fab, defect scans and criticaldimension measurements may eliminate additional errors. Finally, as the product development begins to mature, electrically tested FEM wafers can identify additional process interactions and product sensitivities. Acknowledgments

The authors would like to thank Bernie Matt, Terrence Tong, Jack Thomas, Mark Ramsbey, and Dave Koon at AMD for their support of this work; Margo Gill and Amalia DelRosario for their excellent deprocessing and imaging of the subnominal contact; Mike Pochkowski at KLA-Tencor and Douglas Bernard at Avant! for the simulation work; Ed Hou and Bob Lane at KLA-Tencor for help with the KLA-Tencor 353UV and STARlight inspections, and Darren Taylor at Photronics (Allen, TX) for the KLA-Tencor 8100 Reticle SEM inspections. References 1 . Donald Pettibone, Mohan Ananth, Maciej Rudzinski, Sterling Watson, Larry Zurbrick, Hua-Yu Liu, Linard Karklin, “Wafer Printability Simulation Accuracy Based on UV Optical Inspection Images of Reticle Defects”, Proc. SPIE Symp. Optical Microlithography XIII, Santa Clara, Calif o rnia, March 1999, Vol. 3677, pp. 711-720. 2 . Ingrid Peterson, Kaustuve Bhattacharyya, Enio Carpi, Darius Brown, Martin Verbeek, Douglas A. Bern a rd, “Investigation of Fast and Accurate Reticle Defect Assessment Methods using STARlight™ for Chrome-on-Glass (COG) Reticle Defects”, Proc. Of Photo Mask Japan, April 2000, Yokohama, Japan

A version of this article was originally published in the proceedings of the th 11 Annual SEMI/IEEE Advanced Semiconductor Manufacturing Conference and Workshop, September 12-14, 2000, Boston, Massachussetts, USA.

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Yield Management Solutions

Lithography

Investigation of 193 nm Resist Shrinkage During CD-SEM Measurements Thomas Hoffmann, Greet Storms, Monique Ercken, Mireille Maenhoudt, Ivan Pollentier, Kurt Ronse, IMEC, Belgium Franck Felten, Evelyn Wong, Jonathan England, KLA-Tencor, Europe

193 nm resists are known to shrink during CD-SEM measurements. The large size and non-linear behavior of this shrinkage must be characterized and understood if CD-SEM metrology is to be correctly applied in advanced lithography processing. This paper describes a study in which recommendations for the best measurement conditions were developed and speculations on possible models for the observed shrinkage mechanisms could be made.

Introduction

It is well known that 193 nm resist features change size permanently during CD-SEM measurements.1-5 The size of the shrinkage, often up to 40 nm, should be compared to the CD metrology budget of 1 nm for features in the 100 nm design rule node, when 193 nm lithography is expected to enter production for critical layers. 1 The several classes of 193 nm resist chemistry (COMA, acrylate, cyclo-olefins, VEMA) and layer schemes (single, thin imaging layer and hybrid) all exhibit shrinkage to varying degrees depending on their formulations, process history and measurement conditions. Shrinkage is observed to progress in a nonlinear way with applied e-beam dose and understanding the mechanisms that contribute to this shrinkage is complex. Several studies2, 3 have been reported the attempt to improve this understanding as a basis to improve the resist materials. As yet, complete elimination of e-beam-initiated shrinkage has yet to be achieved. This effect has largely been overcome in 248 nm resist metrology, but we may expect similar or worse effects in some 157 nm materials. It is, therefore, important to understand and minimize resist shrinkage in order to be able to meet the challenges for production worthy CD-SEM metrology of advanced materials. This 32

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paper discusses investigations of shrinkage effects carried out in joint work between IMEC and KLA-Tencor in a study to develop recommendations for CD-SEM conditions that can minimize shrinkage. Experiments

This study investigates a 193 nm resist exhibiting above-average e-beam shrinkage. Wafers were uniformly exposed several days prior to CD-SEM measurements using an ASML 5500/900 argon fluoride scanner at IMEC. Trenches with a nominal CD of 150 nm were measured using five to ten fresh sites for each experiment. It should be noted that resist shrinkage cause the reported trench CD measurement values to increase. A first set of CD-SEM measurements were carried out at KLA-Tencor, San Jose on an 8200-R CD-SEM and these were repeated and extended in IMEC on 8100XP and 8100-ER systems. It has already been widely reported that e-beam exposure of the measurement position must be minimized. Therefore, a standard 193 nm resist measurement recipe was created with a low-magnification pattern recognition step (magnification of 6.25kX, 24 Âľm field of view (FOV)) to identify the region to be measured. The e-beam spot size was then automatically focused in a region away from the measurement site. A highermagnification pattern recognition step (magnification 12.5kX, 12 Âľm FOV) was then used to identify the exact area of the trench to be measured.

CD-SEMs have traditionally carried out measurements by analyzing high-magnification images of the feature to be measured. However, KLA-Tencor CD-SEMs directly collect the linescan (the intensity of the detected electrons signal as the electron beam is scanned across the feature) from the measurement location using an electron beam which is scanned at 120 Hz, four times the industry-standard TV rate. In this application, this technique has the advantages of being faster than when having to acquire complete images, and, more importantly, minimizes the total sample dose. For the measurements reported in this study, 768 linescans were collected at 128 locations equally spaced over 720 nm of the feature. The reported CD measurements were calculated from the average of these linescans using a 50-percent derivative algorithm. Experiments were carried out to investigate the effect of beam conditions and recipe parameters on shrinkage. Early measurements considered 10 static measurements (the sample is not moved between repeated measurement cycles), but the number of measurements was later extended, up to 1500 in some cases, to investigate more fully the various shrinkage mechanisms.

F i g u re 1a. The trench CD variation when using a 600 eV, 10pA beam.

Observations

Figure 1 shows the increase in trench CD over 250 static measurements made using a 600 eV, 10pA beam. Three regimes of shrinkage can be identified as reported elsewhere.3 Each regime can be fitted by an exponential term, each with a characteristic half dose analogous to a half-life in radioactive decay. In the data of Figure 1, there can be seen: i)

an initial fast-shrinkage, with a half-dose of nine measurements;

ii) an intermediate-term shrinkage with a half-dose of 55 measurements; iii) a long-term shrinkage with a half-dose of 540 measurements.

Variation with Landing Energy Shrinkage has previously been reported to change in an absolute way, rather than as a percentage of feature size.1 This implies that the shrinkage is a surface effect, which is easily understood due to the limited penetration depth of the electrons from the CD-SEM. In this study, decreasing the electron-beam energy reduced the size of all the shrinkage mechanisms. This is demonstrated in Figure 2, which shows comparative data to Figure 1 for measurements taken with a 400 eV beam. This dependency can be understood because the interaction volume is smaller and less energy is deposited in the resist as the energy decreases. Estimates of the range taken from published range tables 6 show that expected electronpenetration depths are consistent with energy dependence seen in the data. It should be noted that the lower energy data shows greater scattering because the smaller number of secondary electrons emitted from the sample has reduced the signal-to-noise ratio of the linescan signals.

The intermediate and slow contributions are shown below the data.

F i g u re 1b . The first 100 poi nts of t he trench CD cur ve. The fas t and

F i g u re 2. The equi va lent trench CD curve to Figur e 1a , b ut measure d

i n t e rmedia te cont ributions are shown b elow the data.

using a 400 eV, 10pA beam.

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F i g u re 3. Th e variation of th e trench shrinkage with beam current.

Dose Dependency Beam Current —First experiments on ten static mea-

surements indicated that beam current had little effect on the shrinkage. This surprising result has been reported in work elsewhere. 4 Figure 3 shows shrinkage measured for three beam currents over a larger range of measurements. It must be pointed out that the interpretation of the data in this study is complicated by the fact that we do not know the size of the undosed feature being measured. The first static measurement already includes some unknown amount of shrinkage. Fresh samples have to be used for each experiment, and the CD control across the wafer (measured to be ±9 nm 3σ) does not allow data from each experiment to be compared without having to consider an offset between the collected data sets. The offsets between the sets of data in Figure 4 have been made so that the intermediate shrinkage region for all the beam currents overlap, in agreement with the early observations that this regime is independent of beam current. Under this interpretation, the fast shrinkage mechanism is observed to increase with beam current. The long-term shrinkage mechanism also changes with beam current. At 40pA, a higher than normal beam current, the trench can be seen to narrow once the other mechanisms have stabilized. An alternative analysis of the beam current data with different applied offsets could lead to the conclusion that all the shrinkage regimes depended on beam current. The precision of the data did not vary greatly until the beam current was reduced to 5pA. This reflects the reduced signal-to-noise at this low beam current, analogous to the trend with beam energy. Effect of Scan Overlay after Each Measurement —An early experiment attempted to determine if a time delay placed between successive static measurements would

change the rate of shrinkage by altering the induced temperature of the resist. A variable time delay between static measurements was introduced by using an option known as scan overlay. In this option, an image of the measured feature was acquired after each measurement at the magnification at which the measurement was defined (75kX, 2 µm FOV in this case). The measured linescan was then displayed over this image. Changing the time could be used to delay the period between successive static measurements. No difference in the intermediate shrinkage was observed when this delay was changed between one and five seconds, but it soon became apparent that the image acquisition itself was causing a difference. Figure 4 shows the overlap of shrinkage curves for the first 100 measurements with scan overlay, compared to the first 500 measurements without scan overlay. For clarity, only the fitted trend for the measurements without scan overlay is shown. In this figure it has been assumed that the scan-overlay step creates the same shrinkage as four measurement only sequences. Therefore, the horizontal scale for the data for measurement plus scan overlay has been multiplied by a factor of five. The dose applied to the wafer during imaging is different from the dose during a measurement by a factor of two. This implies that doses applied in different timescales have caused different amounts of shrinkage. Proposed Model for 193 nm Shrinkage

Using the above interpretation of the data, it is possible to speculate on what processes might be occurring in the resist during electron bombardment. Confirmation of this model will require further experiments, including the use of complementary techniques to those used in this study, and it is hoped that the suggestions below

F i g u re 4. The shrinkage over the fi rst 100 measurements with sca n overl ay (red dot s) compared to th e trend (bl ack li ne) of the first 500 m e a s u rements without scan over lay. The beam conditions were 600eV, 10pA.

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might stimulate such further investigations and discussions. The fast mechanism appears to change with energy and beam current, suggesting that it is related to the incident power. The mechanism may be a short-lived, thermally activated process such as the release of certain molecules, perhaps solvent, from near the surface of the resist before the surface has stabilized. This mechanism can be reduced after UV treatment of the surface.3 The intermediate mechanism is saturated with current, and has a lifetime of tens of microseconds. Perhaps this is cross-linking. When an electron impacts the resist, it will undergo many interactions with molecules as it slows down. Some of these interactions create radicals on the resist molecules. The process appears to be so efficient that, in the range of beam currents used in a CD-SEM, all possible radicals are created. The radicals may form cross links before they decay. After the first few dose events (approximately 20 in this study), the surface is cross-linked, and so the fast mechanism is suppressed. Once all the cross-links within the e-beam interaction zone have been made (after approximately 200 measurements in this study), the intermediate shrinkage mechanism stops. Electrons in the e-beam hit the sample on the tens of nanoseconds scale. Therefore, altering the beam current changes events in this timescale. The proposal that beam current does not change the intermediate shrinkage mechanism suggests that the intermediate mechanism is saturated and longer-lived than tens of nanoseconds. During a measurement, the beam returns to the same spot on the sample approximately every ten microseconds. If the radicals have not decayed in this time, the returning beam cannot produce more radicals. During an image acquisition, the beam returns to the same spot on the sample at a slower rate, approximately every ten milliseconds. If the radicals have now decayed, the returning beam will now be able to re-create them. Therefore the increased shrinkage induced during imaging compared to measurement suggests the radicals have a lifetime longer than tens of microseconds, but shorter than ten milliseconds. The slow shrinkage mechanism also proceeds at the same time the above two mechanisms are progressing. This mechanism may be mass loss. There are suggestions that this could be molecular scission or solvent removal.2, 3 The mass loss gives slower shrinkage, which only becomes apparent after the medium mechanism has finished, but continues for a longer dose. When the

resist has stabilized, carry-over can also become evident. This is presumably due to the same mechanism (carbonization or â&#x20AC;&#x153;chargingâ&#x20AC;?) seen in 248 nm metrology. At the lower beam currents typically used for metrology, the trench continues to widen as mass loss dominates over carry-over. At extreme beam currents, such as 40pA investigated in this study, excessive carry-over can actually dominate over shrinkage. Under the normal beam current conditions in the KLA-Tencor CD-SEM, the amount of carry-over is low and hard to observe. Best Measurement Conditions

Irrespective of the explanation for the different mechanisms occurring in the resist, the above work can be used to make recommendations for 193 nm resist measurements. Lithographic performance is best characterized by measuring feature dimensions before induced shrinkage. In production, after-develop inspection (ADI) is used to control and predict the after-etch inspection (ACI) feature size. The etch environment may quickly cause the resist to shrink in a similar way to which it shrinks in the CD-SEM. It is tempting to suggest that, under these conditions, measuring the fully shrunken dimension at ADI might give a reasonable prediction of the ACI dimension. In a related theme, suggestions have been made that resists could be stabilized, presumably both against e-beam-and etchinduced shrinkage, by introducing a pre-conditioning process such as UV irradiation, e-beam cure, or thermal processing.2, 4 However, measuring the un-dosed feature size does not require the assumption of systematic process offsets that are well controlled under all manufacturing conditions and does not incur an increased process cost. In determining zero-dose dimensions, it is vital to consider sources of random and systematic error in the measurements. We can attribute random errors to vari ations in linescans caused by the usual effects that contribute to static and dynamic precision in a CD-SEM. Systematic errors may be attributed to uncertainties in the fits of successive measurements leading to the estimate of the CD of the undosed feature. In 248 nm resist metrology, systematic errors could largely be ignored, and the best conditions chosen to optimize dynamic precision. For 193 nm resist metrology, the systematic errors can no longer be ignored. To reduce systematic errors, multiple measurements should be taken in a dose regime where the medium term mechanism dominates. An e-beam current of 10pA will allow reduced contributions to the systematic errors from the Fall 2001

Yield Management Solutions

fast shrinkage mechanism and still allow good signalto-noise to be obtained. A beam energy of around 500 eV should be the optimum balance point between “dynamic” and “systematic” errors. Choosing 400 eV would not give enough signal-to-noise ratio for good statistics on the linescans, and challenges the creation of truly robust production recipes. 600 eV may be tolerable, but higher energies would cause greater systematic uncertainties. Manual measurements cannot be used because the uncontrolled dosing of samples would lead to variations in shrinkage. Pattern recognition and focus steps can be set up in remote locations and at low magnifications to avoid shrinkage at the measurement site. Image refresh at the measurement magnification must be avoided at all costs. Once collected, the trend of the data has to be corrected for shrinkage. A linear fit (such as that used in 248 nm resist metrology) would no longer be sufficient, as the fast shrinkage has to be accounted for. Accurate correction of this fast shrinkage is likely to give the most problems in future metrology. The coefficients of the fit would depend on the resist and measurement conditions.

to speculate on possible mechanisms that could occur in the resist during e-beam exposure, but further work is required to refute or confirm this model. Independent of the mechanisms, recommendations have been made for the best conditions to use for 193 nm resist metrology in which the balance between systematic and random error contributions has been considered. The above measurement conditions will be applied to automated focus exposure measurements of 193 nm resists and then in investigations of early 157 nm resists.

It is interesting to note that the early literature of 193 nm metrology includes several studies in which the intermediate regime has quickly been exceeded due to the high doses applied to samples. While this allows measurements to be taken in the region of slow shrinkage and would lead to measurements with low random errors, correction of systematic errors would be difficult. The use of non-image based metrology and four times TV rate scanning in KLA-Tencor CD-SEMs allows collection of many measurements before the intermediate regime is exceeded. Care must be taken when benchmarking the capabilities of different CDSEMs. By overdosing the sample and choosing a beam current at which carry over balances mass loss, it would be possible to show 193 nm measurements that appear to exhibit little initial shrinkage and then a low carryover regime over a long set of measurements. The precision would look very good, but there would be a penalty in accuracy.

References

Summary and Future Work

This work has shown that three regimes have to be accounted for in the shrinkage of a particular 193 nm resist. A fast regime is the most difficult to account for because it is so short-lived and uncertain in magnitude. This creates difficulties in both interpreting the data of this study and for the corrections in metrology. Based on one interpretation of the data, it has been possible 36

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Acknowledgements

The authors would like to acknowledge the help of Diziana Vangoidsenhoven, Myriam Moelants, Nadia Vandenbroeck, and Christie Delvaux (IMEC) for wafer processing and exposure, and the many people at IMEC and KLA-Tencor for their useful discussions on this work, in particular Rob Watts, Amir Azordegan, Gian Lorusso, and Gianni Leonarduzzi.

1. I. Pollentier, M. Ercken, A. Eliat, C. Delvaux, P. Jaenen, K. Ronse, “Front-end of line development using 193 nm lithography”, Proceedings SPIE Micro e l e c t ronic and MEMS Technology Conference 2001 2. M. Neisser , T. Kocab, B. Beauchemin, T. Sarubbi, S. Wong, W. Ng, “Mechanism Studies of Scanning Electron M i c roscope Measurement Effects on 193 nm Photoresists and the Development of Improved Linewidth Meas u rement Methods”, Proceedings Interface2000, p. 4352 3. T. Kudo, J. Bae, R. Dammel, W. Kim, D. McKenzie, M. Rahman, M. Padmanaban, W. Ng, “CD Changes of 193 nm Resists During SEM Measurement”, Pro c e e d i n g s SPIE Microlithography Conference 2001 4. L. Pain, N. Monti, N. Martin, V. Ti r a rd, A. Gandolfi, M. Bollin, M. Vasconi, “Study of 193 nm Resist Behavior Under SEM Inspection : How to Reduce Line-width Shrinkage Effect ?”, Proceedings Interface2000, p. 233-248 5. B. Su, A. Romano, ‘Study on 193 nm Photoresist Shrinkage After Electron Beam Exposure”, Proceedings Interface2000, p. 249-264 6. L. Reimer, “Image Formation in Low-Voltage Scanning E l e c t ron Microscopy”, SPIE (1993) p52

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commitment to faster yield ramps. As a result, the fab’s director identified our partnership as critical in helping reach 200 mm-equivalent yields on their very first 300 mm customer lots. Just another reason why more fabs depend on us to help make yield ramps – and ROI – look their very best. For more information, please visit www.kla-tencor.com/300mm, or call 1-800-450-5308. ©2001 KLA-Tencor Corporation

Accelerating Yield

Lithography S

Defect Management for 300 mm and 130 nm Technologies Part 2: Effective Defect Management in the Lithography Cell Scott Ashkenaz, Ingrid Peterson, Paul Marella, Mark Merrill, Lisa Cheung, Anantha Sethuraman, Tony DiBiase, Meryl Stoller, Louis Breaux, KLA-Tencor Corporation

As lithography becomes more complex with thinner resists and sub-wavelength optics, the value of implementing an effective defect-management program has increased. Defect excursions in the photo cell can be corrected by reworking wafers, affording manufacturers the opportunity to fix problems without scrapping wafers, which further enhances the value of defect control in this area. The second in a three-part series, this article focuses on lithography defect reduction and control by implementing a straight forward methodology that combines backside inspection, photo cell monitoring (PCM), after-develop inspection (ADI) for macro and micro defects, and image qualification for reticle defect control.

Introduction

Technology advances within the lithography area are placing greater demands on defect management. The introduction of subwavelength, low-k1 lithographyâ&#x20AC;&#x201D;critical for todayâ&#x20AC;&#x2122;s high-performance devicesâ&#x20AC;&#x201D;has shrunk the size of the focus-exposure process window, and thus has placed tighter constraints on absolute tool stability within the litho cell. The litho cell is defined as the cluster of process equipment that accomplishes the coating (surface prep, resist spin, edge-bead removal, and soft bake), the alignment and exposure, and the develop (post-exposure bake, develop, rinse, and hard bake), of the resist. The latest processes involve spinning the new resists in extremely thin, uniform films, exposing the films under conditions of highly optimized focus and illumination, and finally removing the resists completely and cleanly. With new processes, under these strict operating conditions, effective defect management is critical.

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Yield Management Solutions

Adding to these technical advances are the market forces of strong competition, softer demand, and requirements for shorter product life cycles and faster return on investment. One of the tactics for addressing these pressures is to turn to 300 mm wafers. However, with all the economic benefits that 300 mm wafers confer, their larger diameter poses even greater challenges for uniform processing. This places further constraints on the process window and defect control. Another means for tackling current economic pressures is to utilize more automation. While this affects all equipment within the litho cell, the primary gap in the inspection area has been automation of the macro inspection steps. The benefits of automated macro inspection include higher defect capture, better repeatability, and having a permanent record of the data for in, depth analysis and archival. Today the semiconductor process itself contributes the largest number and variety of defects, and a significant portion of the total defects originates within the lithography cell. From a defect-management perspective, the lithography cell has some unique characteristics. First, defects in the photo process module have the widest range of sizes, from full-wafer to sub-optical, and with the largest variety of characteristics. Figure 1

Edge-Bead Removal • Missing • Wrong width • Miscentering

Hot Spots Contamination • Particles • Foreign materials Coatings • Comets • Striations • Spin • Lifting • Splashback & bubbles • No resist coat

Develop • Scumming • Developer spots • Resist collapse • No develop

Scratches • Handling errors • Tool misadjustment

Exposure • Missing fields • Focus error • Gross misalign • Gross blade errors • No exposure

F i g u r e 1. Lith ography process con trol re q u i res high capture of all yield -limit ing macr o defect types.

gives a summary of the most common kinds of lithography-related defects. These fall into the categories of coating problems, focus and exposure defects, developer defects, edge-bead removal problems, contamination, and scratches. Second, photo is the only area of the fab besides CMP in which defect excursions can be corrected by reworking the wafers. The opportunity to fix defect problems without scrapping wafers is best served by a defectinspection strategy that captures the full range of all relevant defect types. In this paper we will show that a macro inspection combined with a high-numerical aperture (NA), high-resolution imaging inspection system is best suited to this application. Third, to some extent, the lithography cell remains a defect frontier. In most areas of the fab, leading-edge defect-management tools and methodology have already been adopted, but in the lithography area defectivity is often under-managed. For example, recent studies have shown that replacing manual inspection for macro defects by automated inspection can result in an increase of one to two percent in real yield. This paper will show that further yield increases can be realized by implementing a straight forward methodology that combines backside

inspection, photo cell monitoring (PCM), after-develop inspection (ADI) for macro and micro defects, and image qualification to check reticle integrity. Current technology advances and market pressures are re-emphasizing the need for effective defect management in the lithography area. Fabs must detect and identify the sources of defects, and correct tool issues before committing product wafers. In production, defectivity must be monitored tightly so that defect excursions can be acted upon immediately to minimize yield loss. In this paper we focus on lithography defect reduction and control by describing the tools and methodology for optimum defect management, and substantiating the recommendations with case studies and modeling. Overview of Methodology and Strategy

Defect management can be broken down into three basic components: • Initial process optimization • Routine monitoring of the tools and processes • Monitoring and disposition of product wafers Fall 2001

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F i g u re 2. KLA -Te n c o r ’s i nsp ecton and metr ology tool set for l itho cel l monit ori ng.

Each of these components is associated with a set of inspection tools and sampling strategies that addresses its unique requirements. Figure 2 summarizes the inspection points and inspection tool set that monitor the lithography cell.

Process optimization When a new process is under development, defect sources are greatest in number and variety, and include both systematic and random types, many of which may be previously unknown. This is especially true at a new node or when significant new technology is introduced, such as copper dual damascene, a new wavelength-resist system, or advanced optical-enhancement techniques. Systematic defects are characterized as baseline defects; random defect types as excursions. Systematic defects are those types that are caused by un-optimized processes and/or incompatibility of materials. Examples of systematic defects are residues originating from resist/developer interactions, or process-window failures. Random defects types tend to re-occur from time to time and are typically caused by machine failures, 40

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batch-to-batch chemical variations, particles, and other environmental problems. For this reason, the recommended defect-management approach is to utilize the inspection strategy that provides the highest capture rate for the full range of defect type. This strategy requires inspections to be performed at high sensitivity, even at the expense of throughput. The goals during the process optimization phase are to: • Capture and characterize all defect types • Analyze the effect of each defect type on yield • Optimize the process for minimum defectivity During this phase the team learns the sources of the critical defect types, tunes the inspection systems to capture them efficiently, programs the automatic defect classification (ADC) systems to recognize them, and sets control limits based on the expected frequency and kill ratio of each defect type.

In the lithography area, a high-NA, high-resolution imaging inspection system is recommended to provide the highest level of defect capture of the broadest range of defect types. A high-frequency sampling strategy is needed: typically, full-wafer inspections on enough wafers to capture wafer-to-wafer and lot-to-lot variations coming from different spin and develop cups. Since high defect-capture rate is desired in this phase, the full-wafer inspection mode, typically performed using a “random” mode inspection, should be supplemented with “array” mode inspection which typically provides higher sensitivity in dense design areas. On-board ADC will be supplemented heavily with offline review using optical and SEM-based review stations. Towards the end of this phase, a PCM process will also be established, providing the maximum sensitivity to patterning defects to establish and maintain a baseline.

Slurry residue, particles, and other contamination on the backside of the wafer have been correlated to the gener-ation of hot spots on the front side of the wafer (Figure 3). This is particularly important for devices relying on 180 nm design rules and below, where the depth of focus is very narrow. During backside inspection, blank wafers are run through the cell and an unpatternedwafer inspection system is used to examine the backside of the wafer for contamination, scratches, and other defects. Backside inspection also may be employed before and after cleaning steps to detect contamination and residual slurry, monitoring process equipment chucks and end effectors. In some fabs, unpatterned test wafers are also used to enable detection of micro defects on the front side, such as pinholes and microbubbles from the coating process. Detection of developer-dispense errors and residue via their spatial signatures represent another application for front side inspection of unpatterned test wafers.

Tool and process monitoring

Backside inspection After the process has been optimized and transferred to production, the health of the litho cell must be monitored through periodic checks. A systematic check of the photo process equipment is typically performed once per shift. Part of this monitoring process includes backside inspection.

The characteristics that make an unpatterned inspection system suitable for this application include high sensitivity and uniform detection capability, and the power to detect the range of defect types of interest—which in turn requires a flexible optical system. The high sensitivity and uniform detection are not only possible due to the inspection technologies available, but also due to the lack of interference from previous processing. Because the back side of the wafer is rough on 200 mm wafers and below, detecting defects such as particles and scratches on the back side poses different system requirements from detecting microbubbles in a thin film of resist on the front side. Backside inspection also necessitates edge handling of the wafers during inspection, instead of resting them on a chuck or paddle.

PCM

F i g u re 3. Bac kside c huck marks identified by the KLA- Tencor Surfsca n SP1 D L S

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Another technique for ensuring the health of the litho cell is PCM. The introduction of patterned photo cell monitor wafers to the lithography defectmanagement system arose from a need to increase the capture rate of certain low-contrast defects that were being missed during inspection of product wafers.1 These resist-on-silicon or resiston-oxide-on-silicon wafers may use the Yield Management Solutions

same reticle as product wafers, or they may use their own specially designed reticle. The value of PCM wafers is that they have only a single layer of patterned resist, which facilitates capture of defects that may be masked by noise from underlying layers on a product wafer. Although the cost of these non-product wafers must be taken into account in determining the optimum defect-management strategy, PCM wafers can be recycled. The experience of KLA-Tencorâ&#x20AC;&#x2122;s Yield Management Consulting Group has shown that greater than 90 percent of defect types seen on product wafers can be detected and managed using PCM. Often the detection of the defects is better on PCM and the fab, therefore, is better able to ascertain the defect source through experimentation and analysis of the spatial signatures. Inspectionsystem throughput is also higher on PCM wafers because the inspections can be set at a larger pixel size and still have the same capture rates as compared to smaller pixel sizes used on product wafers. In addition, defect classification and review is also more efficient, since defects on PCM wafers are limited to the photo cell, compared with the many previous layer defects present on product wafers. Typically, the lithography cell is checked using PCM once a shift or once a day. If the inspection frequency is lower, the cost risked by missing excursions increases. Highly sensitive, high-resolution imaging inspection of PCM wafers will capture very low topography and/or very small defects such as stains, microbridging, microbubbles, CD variation, and single, isolated missing or deformed contacts/vias. All of these defect types are difficult to detect on product wafers. Examples are shown in Figure 4. Defects such as amine contamination of deep UV resist can also be detected by high-resolution imaging micro inspection using a PCM wafer. Stains and minor color variations can be translated into blocked contacts, bridging, missing or extra-pattern defects, and CD variations after etch. The high-resolution imaging system also has the sensitivity to detect single missing contacts with a high capture rate, providing good information for quantifying and improving this elusive defect. When defectivity problems are discovered and fixed using PCM, valuable product wafers can be spared.

or cause CD variations. Image qualification is a necessary process for qualifying image transferring for PSM (Phase Shift Mask) reticles. Its importance has increased in the photo defect area due to the wide use of the phase shift technology for sub-130 nm. In order to ensure complete transfer of the PSM image onto the wafer, it is not necessary to inspect the full wafer for this, but only to inspect sufficient fields to allow arbitration and repeater confirmation. Some fabs choose to extend this by printing at a range of focus settings and exposures to amplify the effect at the edges of the process window. These wafers are then inspected on a high-resolution imaging inspection system and analyzed for repeating defects. Another method for reticle management is direct inspection of the reticle itself using a reticle inspection system. This is effective for detecting defects on the reticle or pellicle such as soft defects, effects from electrostatic discharge, crystal growth, or a number of other common problems.

Small pattern bridging Single distorted contact/via

Single distorted

Micro bubbles

Image qualification The process used for PCM is designed to optimize sensitivity while reducing cost. It may also be used to qualify reticles in the fab inventory prior to use. By printing wafers from the product reticle, it is possible to discover any defects that may print as pattern errors 42

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Missing single contact/via F i g u re 4. Photo defects detected using KLA-Te n c o r â&#x20AC;&#x2122;s 2351 High Res olution Ima ging Waf er Inspection.

It is beyond the scope of this article to fully explore reticle defect control; it is a topic that is worthy of its own paper on methods, tools, strategies, and costs.

macro inspection systems came on the market in 1998, and have been rapidly adopted in place of manual inspections (Figure 5).

Monitoring and disposition of product wafers via macro and micro ADI

Many of the defects formed in lithography can be reliably found with automated macro inspection. Defects ranging in size from 50 µm to full-wafer are captured at high throughput, with capture rates and repeatability much higher than that of visual inspection. Archival storage of each inspection is provided—another benefit over using visual techniques. Wafer maps can be used for defect analysis, stacking, and generating Paretos. Instead of relying on subjective judgment, which changes with the operator, the shift, and the product, automated inspection provides objective data to drive effective wafer disposition. Because this information is also recorded like any other automated defect inspection result, it may be examined by a number of methods, including stacking of multiple wafers to identify subtle patterns.

After the health of the litho cell has been assured by backside inspection and PCM, product wafers are allowed to pass through. A small number of product wafers are monitored for macro defects using automated, simultaneous high-resolution imaging and highthroughput laser scanning technology, then for micro defects using broad-band high-resolution imaging technology. When defectivity problems are discovered before etch, the product wafers often can be reworked, instead of being scrapped at a later step or found at final test to have suffered yield loss. The cost savings from this control can be dramatic. This inspection point is known as the after-develop inspection, or ADI. CD SEM and overlay metrology are also performed at this point, either before or after the inspections, depending upon the expected frequency of metrology versus defect problems. A high-resolution imaging after-etch inspection of the product wafers for micro defects completes the set of lithography-related inspections, as shown in Figure 2. Often the first after-develop inspection is macro ADI. In the past, this inspection was done by trained operators using their eyes and a bright light—with results that varied widely among inspectors and over time. Automated

A case study from IBM showed significant increases in capture of several lithography-related defect types after automated macro-defect inspection was implemented (Figure 6a), and another study from NEC6 demonstrated an overall increase in defect capture rate of more than ten percent (Figure 6b). Evaluating eight layers on one product, weighting defects by their kill ratio—and not including savings realized by using fewer operators or through shorter time to decision—NEC’s study found a potential savings of $66,500 per month through using automated macro inspection. Other studies have shown potential annual benefits of $3.6M2 to $6.7M3, depending

F i g u re 5. As des ign rules app roach 130 n m and beyond, these figur es show the r ise in adoption o f KLA-Te n c o r ’s macro-def ect inspect ion syst em by i nst alled base and app lication.

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upon the device value, fab size, and other assumptions and details of the calculation. Completing the scope of after-develop inspections is micro ADI. As with the PCM inspection, high-NA, high-resolution imaging inspection is the best technology to capture any micro defects that may be similar to the PCM defects or may be topography-related, process- integration defects. Micro ADI inspection has shown critical detection of 130 nm-node photo ADI defects such as pattern repeaters, line CD variations, and missing contacts/vias due to reticle and other process issues. These are critical defects that normally are not detected until after etch/strip/clean inspection (ASI or ACI). Capture of these defects allows rework of the resist and avoids scrapping the wafers.

When the after-develop inspection is complete, a decision must be made whether to pass the wafers onto etch, re-work the lot, or scrap it. Lot disposition can be done automatically in many cases by utilizing an integrated ADC and analysis system to monitor defectivity by type. In the lithography cell, defect classification and analysis methodology should be similar to that in other parts of the fab. Newest techniques are aimed at intelligent filtering of data: leveraging any quick, automatic binning of defects that reduces the sample size of defects requiring more thorough review. On-board real-time classification or inline ADC can separate nuisance defects from defects of interest before the wafer leaves the inspection system— and often without impact on the inspection throughput. High-resolution ADC, either on the inspection system itself or on a review station, can then be limited to defects of interest which require further review. The analysis tool is an integral part of this “waterfall sampling” process, as it employs automatic defect-source analysis, and manages the data flow and presentation. The simple methodology described above relies on only three kinds of defect-inspection systems: an unpatterned inspection system for backside inspection, a high-resolution imaging micro-defect inspector for PCM and ADI, and an automated macro-defect inspection system for ADI. Together with automated defect classification and analysis, this inspection tool set and methodology can provide leading-edge defect management for the lithography module. Methodology Model

F i g u re 6a. Normalized comparison of man ual r ewo rk t o automated m a c ro inspection, (with KLA-Te n c o r ’s 2401) excluding wh ole-wafer events, showing signifi cant i ncreases in captur e of al l d efect types.

To supplement the knowledge gained from customer experience and by in-house experiments, a group at KLA-Tencor constructed a model for determining an optimized defect-management methodology for the lithography module. Leveraging the Sample Planner 3 cost model, the group analyzed a full range of defect-inspection technologies and sampling strategy combinations to determine the most cost-effective solution.

F i g u re 6b. Pass/fa il resul ts comparing visual inspection to 2401 aut omated macro inspect ion, for 213 lot s i nspected at ran dom, demon stra ting th at t he auto mated syst em h as a capture rate ten times that of visual in spection.

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For the model inputs, they used 300 mm wafer sizes and throughputs, assumed 5000 wafer starts per week, used a 12wafer lot size, 600 dice per wafer, and $35 average selling price per device. They used actual 200 mm production fab-cycletimes and modeled 31 typical defect types.

KLA-Tencor’s Tool Set for Lithography Defect Control Unpatterned Inspection for Backside Contamination KLA-Tencor’s unpatterned inspection system is the Surfscan SP1DLS. It features axially-symmetric collection optics for sensitive and uniform defect detection, with an oblique incident angle and polarization to optimize sensitivity on rough surfaces—such as the back side of the wafer. Already used heavily throughout most fabs, including in the litho area, the SP1DLS is an important piece of the strategy to monitor and maintain process quality. On-board defect classification is provided without discernible impact on inspector throughput. Automated Macro Inspection for ADI KLA-Tencor’s 2430 features concurrent darkfield and brightfield optics to provide the breadth of technology required to capture all important macro defect types. Defects ranging in size from 50 µm to full-wafer are captured at more that 80 wph throughput. The capture rate is about ten times that of visual inspection, and repeatability is more than 90 percent. The 2430 also features on-board review and storage capability for root-cause analysis, defect map signatures, and a wafer gallery. High-Resolution Imaging Inspection for PCM, ADI, and Image Qualification KLA-Tencor’s latest addition to their line of high NA high-

For inspection equipment, they included macro ADI, high-resolution imaging and high-throughput laser scanning micro ADI, (such as would be provided by KLA-Tencor’s AIT systems), and high-resolution imaging and high-throughput laser scanning PCM. For costs due to inspection operations, they included inspection-and review-tool capital depreciations, testwafer and process-tool time, direct and indirect labor, service contracts and parts, and facility costs. For costs due to defect excursions they included lost revenue opportunity due to increased lots at risk to excursions, and investigation and fixing costs. The plan was to achieve the optimum balance of total fab costs, the sum of operational expenses, and yield-related losses. The results of this simulation are given in Figure 7. In Figure 7a, the benefits of using PCM and macro inspection are clearly shown. Using macro inspection alone reduced the overall yearly cost by nearly a factor of two, while using macro inspection together with PCM three times a day reduced the overall cost by more than a factor of two. In Figure 7b, the results of comparing high-throughput scanning with high-reso-

resolution imaging inspection systems is the 2351. This system combines broadband visible and UV light with different pixel sizes to meet sensitivity and throughput requirements. Special optical modes are available to suppress grain noise and enhance capture of low-contrast defects. Cost of ownership is minimized by employing massively parallel image processing, plus an updated image computer and stage to enable highest possible throughput for wafer sizes up to 300 mm. On-board inline automatic defect classification (iADC) provides the most useful information in the fastest time possible. Defect Classification and Analysis For most of KLA-Tencor’s inspection systems, automatic defect classification (ADC) is provided on the inspector itself. These integrated ADC systems can provide binning of defect types, such as nuisance defects, using the inspection data only and therefore providing information without impact on the throughput of the inspection system. For those defects requiring higher-resolution review, some of the inspection systems also allow review and higher-resolution ADC on the tool itself. After on-board review classifies most of the defects, any remaining unclassified defects can be sent to a dedicated review station, such as KLA-Tencor’s optical CRS or SEM eV300. All of these systems are equipped with compatible ADC systems, so that all defects of interest are automatically located, reviewed-and classified.

lution imaging PCM are given. In all cases high-resolution imaging PCM provided superior overall cost, and performing PCM three times a day provided benefit over a twice-daily regime. In this case, the high-resolution imaging technology claimed a significantly higher capture rate of the defects of interest over the highthroughput scanning system, easily negating the higher cost of operating the high-resolution imaging system. The key component of this result is the higher capture rate of all critical defect types. In Figure 7c, the ADI inspections are added to the mix. The largest difference between revenue saved and cost of inspection operations was given by a combination of high-resolution imaging PCM, three times a day; 100 percent macro ADI; and high-resolution imaging ADI with the relatively low sampling rate of 6.25 percent. This study provided several important conclusions: • Macro ADI provided the highest return on investment, and allowed the micro ADI sampling rate to be reduced. Important to this result is the need to detect all critical litho defect types; any significant gap in sensitivity can have dramatic impact on the cost benefit. Fall 2001

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Stepper Qualification Using Automated Macro Inspection A robust tool-monitoring technique is required for steppers, since they are often the most critical tools in the line. Their high capital costs can result in a throughput bottleneck. The current practice of a visual check for focus errors or “hot spots”, following preventive maintenance or before critical lots, is limited by the qualitative nature of the operator’s inspection, high operator-to-operator variability, complex wafer diffraction patterns, and the lack of physical records of the inspection. This is an area where automated macro inspection can provide significant benefit. Recently ST Microelectronics conducted a study with KLA-Tencor’s 2401 and found that: • Regular stepper monitoring can reduce product exposure to yield killers: hot spots, leveling/focus/exposure errors; • Their largest gap currently is their use of visual inspection techniques; • Using an automated macro inspection method provided significant benefit via high sensitivity (full-field grating, post-reticle at lens resolution); and high consistency— effective sampling with an historical record. Source: Martin, B. (ST Microsystems); Kent, E., DiBiase, T., Tamayo, N., Rutherford, I. (KLA-Tencor) “Stepper Qualification with Automated Macro Inspection,” SPIE Microlithography Conference, Santa Clara, California, February, 2001.

• High-resolution imaging PCM provided the second highest return. Sampling once per shift was critical, even when capacity had to be allocated from the after-develop micro inspection. It was found that it is important to do this with high-resolution imaging inspection to capture all defect types; other types of inspection have inadequate capture at this step. • Test wafer costs were low compared with PCM savings, even using 300 mm wafers. • Lot-rework ability increased the value of the difference in capture rate of high resolution imaging versus high-throughput scanning technology for defect types modeled in this study. Lot-rework ability also reduced the requirement for high lot-sampling frequencies. Thus, overall, high-resolution imaging technology proved more cost-effective for micro ADI and PCM. In short, the recommended lithography defect inspection strategy is provided by a combination of macro ADI, 46

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F i g u re 7. Results of the Sampl e Planner 3 model showed (a) the significant cost benefit to using automated macro inspection and PCM; (b) the benefit of using high-resolution imaging PCM over high-throughput s c a nning; (c) the benefit of high-resolution imaging ADI over high-re s o l u t i o n i m a g i n g, p roviding the op timum solution of ma cro ADI, h i g h - re s o l u t i o n i m a g i n g PCM and h i g h - resolut ion imaging ADI with a sampling interv a l of 6.25%.

high-resolution imaging PCM, and high-resolution imaging ADI.4 Summary

From a defect-management perspective, now is the right time to bring the lithography module up to the standards of the other process modules in the fab. References 1.

Petersen, I., Thompson, G., DiBiase, T., Ashkenaz, S., Pinto, B., “Lithography Defects: Reducing and Managing Yield Killers through Photo Cell Monitoring,” Yield Management Solutions, Summer 2000.

Reticle Qualification Complemented by High-Resolution Imaging Wafer Inspection As design rules approach 130 nm and below, the reticles used to produce these devices typically must rely on phaseshift technology. Guaranteeing 100 percent defect-free reticles is a difficult task, even with the advanced reticle inspection tools available on the market today. The amount of phase error found on a defective reticle can be multiplied by an order of magnitude at the wafer level, depending on the kind of resolution-enhancing technology used.

Defect management in the litho cell is an area where significant improvements can be realized. As lithography has become more complex with thinner resists and sub-wavelength optics, the value of implementing an effective defect-management program has increased. The ability to rework wafers when defects are captured before etch enhances the value of defect control in this area. An effective defect-management system is comprised of three parts: process optimization, tool and process monitoring, and monitoring and disposition of product wafers in production. A mathematical model of the inspection systems, sampling strategies, and fab costs, supported in part by case studies from fabs, demonstrates that the combination of high-resolution imaging PCM, macro ADI and high-resolution imaging micro ADI together with backside inspection provides the most effective litho defect-management system. The replacement of visual inspection with automated macro ADI provides highest value, followed by introducing highresolution imaging PCM.

In addition to naturally occurring defects on reticles, attempts at repairing defective reticles occasionally produce unexpected results on the wafers near the repair area, such as defect printability or CD variations. Considering that advanced reticles cost upwards of $30K, it can be cost-effective to supplement reticle inspection by using a high-resolution imaging wafer inspection system to monitor the wafer. This is one area of the fab where finding most of the defects is not enough—just one repeater occurring in an unfortunate position in the die can affect yield.

Yanof, A., Plachecki, V., Fischer, F. (Motorola); Cusacovich, M., Nelson, C., Merrill, M.(KLA-Tencor), “Implementation of Automated Macro After Develop Inspection in a Production Lithography Process,” Metrology, Inspection, and Process Control for Microlithography XIV, Proc. SPIE Vol. 3998, p 504-514, SPIE, Bellingham, WA, 2000. 3. I n t e rnal KLA-Tencor presentation. Contact Kanae Mukai for additional information.—kanae.mukai@kla-tencor.com 4. These results are expected to hold for 200 mm operations as well. The sampling frequency may be incre a s e d since the inspection costs are lower for 200 mm wafer inspection.

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Got a Litho Question? Ask the Experts Q How does diffusion during post-exposure bake affect resist linewidth?

A Diffusion during post-exposure bake (PEB) can serve many purposes, including smoothing away standing waves and allowing acid in chemically amplified resists to migrate to reaction sites. One detrimental affect of diffusion is the possibility for a change in the critical dimension (CD) of the feature. In this respect, diffusion acts a lot like going out of focus: it degrades the gradient of chemical species between the exposed and unexposed areas. Like defocus, its affect on CD depends both on the feature type and the exposure dose. For example, consider a dense array of lines and spaces. When underexposed, going out of focus tends to make the line larger, while the opposite occurs when overexposed. For most isolated lines, going out of focus will always make the line smaller (unless you are seriously underexposed). Increased diffusion has nearly the same effect on the CD for dense and isolated lines. For chemically amplified resists, the picture is more complicated. Increased diffusion may also lead to increased amplification reactions, which tend always to make the lines smaller for a positive resist. If, however, one thought of diffusion as independent from the reactions that occur during PEB for a chemically amplified resist (a useful mental exercise, if nothing else), then the same ideas described above will apply.

Q Can PROLITH be used to calculate the

overlapping process window of horizontal and vertical lines in the presence of astigmatism?

PROLITH can certainly simulate the effects of astigmatism on the process window. By entering the coefficients of the 36 term Zernike polynomial, just about any aberration can be simulated. By running a focus-exposure matrix as a simulation set, the process window will automatically be calculated. This can, of course, be repeated for both vertical and horizontal lines (the "rotate mask" feature is very convenient for this purpose). However, PROLITH cannot be used to overlap the two simulated process windows. Klarity ProDATA, KLA-Tencorâ&#x20AC;&#x2122;s lithography data analysis software solution, is needed to accomplish this. A simple drag and drop operation can be used to take the simulated focus exposure data and add it to Klarity ProDATA. Repeating this step for both horizontal and vertical lines will put both data sets into ProDATA. Then, a data group with these two data sets can be created in Klarity ProDATA and the overlapping process window feature can be selected.

Do you have a lithography question? Just e-mail lithocolumn@kla-tencor.com and have your questions answered by Chris Mack or another of our experts.

Fall 2001 Yield Management Solutions

Lithography

Spectroscopic Critical Dimension (SCD) Metrology for CD Control and Stepper Characterization Authors: John Allgair, Motorola, APRDL & Pedro Her rera, KLA-Tencor Corporation Co-authors: R. Hershey, L. Litt, D. Benoit; Motorola, APRDL, A. Levy, U. Whitney; KLA-Tencor Corporation

Smaller device dimensions and tighter process-control windows have created a need for CD metrology tools to detect and measure changes in feature profiles that are becoming critical to inline process control and stepper evaluation for sub-0.18 µm technology. Spectroscopic CD is an optical metrology technique that can address these needs. This work describes the use of a spectroscopic CD metrology tool to measure a sub-0.18 µm gate level focus and exposure matrix in order to characterize the lithography process window. The results include comparison to the established inline CD SEM, as well as profiles from a cross-section SEM. Repeatability, long-term stability, and matching data from a gate-level nominal process are also presented.

Introduction

Smaller device dimensions and tighter process control windows have created a need for metrology tools that measure more than just one-dimensional critical dimension (CD) features. The need to easily detect, identify, and measure changes in feature profiles is becoming critical to controlling current and future semiconductor lithography and etch processes. Measuring changes in sidewall angle and resist height, as well as detecting subtle phenomena such as line-rounding, t-topping, and resist footing, is now as important as the traditional CD line-width measurement. This additional profile information can be used to enhance process-control mechanisms and can also be used to evaluate and characterize the performance of a stepper/track module. Traditional CD metrology techniques give no indication of a measured feature’s sidewall angle or height. Spectroscopic CD is an optical metrology technique that can address these needs. SCD is based on spectroscopic ellipsometry (SE), an accepted and 50

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Yield Management Solutions

widely used optical technique for measuring film thickness and film properties. This work describes the SCD measurement technique and its use in measuring a sub-0.18 µm gate-level focus and exposure matrix to characterize the lithography process window. SCD results are compared to results from a CD SEM and a cross-section SEM to determine if SCD is able to measure accurately the feature behavior through changes in focus and exposure. Furthermore, SCD is used to monitor features outside the process window to determine if it can detect and identify out-of-control process conditions. Repeatability, long-term stability, and matching data from a gate-level nominal process are also presented. These repeatability and stability tests were performed to verify SCD meets the roadmap requirements for current and future semiconductor processes. SCD Measurement

The SCD measurement technique is summarized in Figures 1 and 2. Gratings on the production wafers

F i g u r e 1. Schematic of SCD measure m e n t .

have polarized light directed onto them and the spectrum of the reflected light is recorded. The gratings are repeating line/space features of uniform period. The line size and period of the grating are designed to represent the in-die feature that is being controlled. A model of the grating geometry and underlying film stack is created and incorporates such parameters as the grating height, the line width, the sidewall angle, and the film properties (thickness, n, and k). Varying the grating parameters and calculating theoretical spectra construct the library. This library is linked to the recipe on the metrology tool. As the wafer is measured the data are compared to the library. The best match between the measured spectra and the modeled spectra determines the parameter values that best describe the physical grating.

of polysilicon, and 30Å of oxide. One wafer type was printed as a focus-and-exposure matrix with focus varied from -0.35 µm to +0.05 µm (0.05 µm steps) and exposure varied from 18.6 mJ/cm2 to 21.8 mJ/cm2 (0.4 mJ/cm2 steps). The second wafer type was printed with nominal settings for focus and exposure. The gratings on these wafers are 50 µm x 50 µm in size and have a line/space ratio of 150/210 nm (360 nm pitch). Measurements from the focus and exposure matrix wafers were used to generate Bossung curves, determine the correlation between SCD and CD SEM

Procedure

Metrology Tools The metrology tools used in this work were a KLA-Tencor SpectraCD SCD measurement system, a KLA-Tencor 8100XP CD SEM, and a Leopold 982 Cross-Sectional SEM. SpectraCD allowed for full spectrum (240-780 nm wavelength) matching with its broadband light source. Spectra collected on the SpectraCD were matched in real-time to a library generated with KLA-Tencor’s Library Generation Service (LGS) modeling software. The 8100XP is a top-down (electron beam normal to the sample) CD SEM used for inline process control and engineering development. The CD SEM was calibrated to a known pitch standard and production recipes were used in automated mode for all the measurements described herein.

Wafers and Gratings Two types of wafers were used for this work. Both types had 3800Å tall resist lines over 200Å of ARC, 1500Å F i g u re 2. SCD measurement summar y.

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generation also incorporated such features as line rounding, t-topping, resist footing, and asymmetry between the left and right sidewalls. Figure 3 shows the range of profile shapes and illustrates how the line width (CD), height (HT), and sidewall angle (SWA) are defined. The shaded area between the inner and outer profiles represents the range of modeled profiles from the smallest, rounded profile to the largest, t-topped profile. Results

Analysis of a Focus-and-Exposure Matrix for Stepper Characterization

F i g u re 3. Libr ar y profil e ra nge wit h defi nition of CD, HT, and SWA .

measurements, and compare SCD to cross-section. The nominal wafers were measured to characterize the precision, stability, and matching performance of SCD.

SCD Library The library created to measure these wafers was developed to encompass the range of CD, height, and sidewall angle found in the focus and exposure matrix described above. CD was varied from 100-200 nm, sidewall angle from 81-93 degrees, and height from 200-400 nm. These are very large parameter ranges; a library for a normal, production layer would use much smaller ranges. The profile shapes used in library

F i g u re 4. CD-SEM B ossung cur v e s .

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Bossung Curves and Measurement Correlation: When measured on the CD SEM, the Bossung curves are as drawn in Figure 4. As shown, focus is centered near -0.15 Âľm. CD is stable through focus at the center exposures, but shows more variation at the minimum and maximum exposures. Overall, there is symmetry in the curves from left to right and top to bottom. Comparing these to the Bossung curves generated with SCD, see Figure 5, it is clear there is good agreement between the two measurement techniques at negative defocus. Both techniques show an upward trend at small exposure and a downward trend at large exposure as focus becomes more negative. However, the two techniques do not agree at positive defocus. In this region, the SCD measurements show a consistent downward trend. This is very noticeable on the 19.8 and 20.2 mJ/cm2 exposure trend lines where CD values are very low at positive defocus. The SCD Bossung curves do not demonstrate the same left to right and top to bottom symmetry found in the CD SEM Bossung curves.

F i g u re 5. SCD Bossung curv e s .

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F i g u re 8. Cross-sect ions at center and po sitive focus.

(positive defocus). The SEM measurements will key on the bright line edges and report similar measurements for both lines. The SCD measurements will detect the change in sidewall angle and give measurements to reflect the different midpoint CDs.

F i g u re 6. Sidewall a ngle a nd heigh t through focus and exposure .

Sidewall Angle and Height Measurements: The SCD measurements for sidewall angle and height explain why the Bossung curves do not agree. In Figure 6 the line height decreases with positive defocus; this is also the case for the sidewall angle. The line profile is shorter and getting wider at the bottom than at the top. Figure 7 shows the difference between a well-defined vertical line (center of focus) and a shorter rounded line

SCD Comparison to Cross-Section: Cross-sections taken on wafers with a larger focus range agree with the SCD height and sidewall angle measurements. As shown in Figure 8, the cross-section at center focus shows vertical edges and good uniformity from line to line. The cross-section at positive defocus shows the resist height loss and less vertical edges described in the SCD measurements. Furthermore, a comparison between SCD and cross-section reveals SCD gives accurate (referenced to cross-section) measurements of CD, height, and sidewall angle. Table 1 shows the SCD and cross-section results from the same grating. Given the amount of error in the cross-section (~2%), the two methods give identical CD measurements. SCD can, therefore, be used to accurately and non-destructively measure linewidth CD and characterize a featureâ&#x20AC;&#x2122;s profile real-time on product wafers. Fault Detection: At process extremes, the need to measure changes in CD or sidewall angle is replaced by the need to detect if the features are completely outside of the process window. The edge of the focus-and-exposure matrix yielded the opportunity to test SCD against out-of-control, beyond-process-window conditions. One such condition is when lines are over-exposed to the point where they are either faint smears or missing

CD (nm) Height (nm) Sidewall Angle (deg)

Cross Section (nm) SCD (nm) 117 113.7 344* 364 N/A 89.0

* Cros s-section height measurement taken at cent er, s horter l ine F i g u re 7. Grating line at cen ter an d positive focus (150kX images ).

Table 1. Cross-section a nd SCD measure m e n t s .

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Min Max Mean 3

Sidewall Angle (deg) Height (nm) 85.92 549.26 85.94 549.37 85.93 549.32 0.01 0.08

CD (nm) 217.92 218.00 217.96 0.06

Tabl e 2. Single site stat ic measurement pre c i s i o n . F i g u re 9. Cross-sect ion and SEM image (75kX) of over-exp osed, outof -focus lin es.

from the wafer altogether, (see Figure 9). The SCD model can be modified and expanded to account for this and other out-of-control conditions. Figure 10 shows modeled and measured spectra for two such cases—one where the lines are missing from the wafer, another where the lines were not developed or exposed and the grating is actually a pad of resist with no pattern.

Min Max Mean 3

Sidewall Angle (deg) Height (nm) 85.89 549.19 85.96 549.53 85.93 549.37 0.05 0.24

CD (nm) 217.69 218.11 217.80 0.27

Table 3. Single site dynamic measurement pre c i s i o n .

Measurement of a Nominal Gate Wafer Process for Precision, Stability, and Matching Estimates

recipe measuring five fields (top, center, bottom, left, and right) on the nominal wafer. Figure 11 shows the measurements at each site for 31 days.

SCD Measurement Precision: The SCD static precision and dynamic measurement precision (1 site) are shown in the Tables 2 and 3. The results are from 20 measurements taken on the same field, where static indicates the wafer was not unloaded and reloaded between each measurement. The sidewall angle, height, and CD show good repeatability for both tests. Measurements from 24 sites across the wafer support these single-site tests by giving an average CD dynamic repeatability of 0.28 nm (3σ).

Tool-to-Tool Matching: The nominal wafer was measured on four different SpectraCD systems to gauge the techniques-matching capability. Each tool took 15 measurements on the wafer. Results from those measurements are shown in Table 4. Each tool was within 0.5 nm of the total average.

SCD Measurement Stability: The SCD measurement stability over a month-long time period was 0.31 nm (3σ). This was measured by running a daily qualification

As shown, SCD technique based on spectroscopic ellipsometry is able to characterize a focus-and-exposure matrix and demonstrate excellent measurement precision.

Conclusion

F i g u r e 10. Modeled an d measured spectra for no exp osure/ devel op and over- e x p o s u re .

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System 1 2 3 4 Average Range

CD (nm) 195.14 194.55 195.18 195.00 194.97 0.63

Delta to Average (nm) -0.17 0.42 -0.22 -0.03

Table 4. SCD matchin g re s u l t s .

F i g u re 11. SCD l ine widt h m easurements over 31 d ays.

SCD shows good correlation to a top-down CD SEM and demonstrates good accuracy when compared to crosssection SEM. The SCD measurements of resist height and sidewall angle give a clear picture of how the grating target lines are affected by changes in focus and exposure. Furthermore, SCD is capable of detecting when a process is out of its control window and identifying the out-ofcontrol failure condition. The SCD technique, performed on the SpectraCD system, is therefore a metrology technique that can be used for real-time, inline control of an advanced semiconductor pattern transfer process.

References 1. J. Allgair, D. Benoit, R. Hershey, L. Litt, I. Abdulhalim, M. Faeyrman, J. Robinson, U. Whitney, Y. Xu, “Manufacturing Considerations for Implementation of Scattero m e t ry for Process Monitoring,” Proceedings of the SPIE, Vol. 3998, pp. 125-134, March 2000. 2. H. Tompkins, W. McGahan, Spectroscopic Ellipsometry and Reflectometry, John Wiley & Sons, 1999. A version of this article was originally published in SPIE Proceedings vol. 4344, paper 57, entitled “Implementation of spectroscopic critical dimension (SCD) for gate CD control and stepper characterization” by J.A. Allgair, D.C Benoit, R.R Hershey, L.C Litt (Motorola); B.Braymer, P.P Herrera, C.A Mack, J.C Robinson, U.K. Whitney, P. Zalicki (KLA-Tencor Corp.)

Lithography S

Using Pattern-Quality Confirmation to Control a Metal-level DUV Process with a Top-down CD SEM Chien-Sung Liang, Haiqing Zhou, Mark Boehm, Ricky Jackson, KFAB Photolithography Module, Texas Instruments Chih-Yu Wang, Mike Slessor, KLA-Tencor

As critical-feature patterning processes increase in complexity and sensitivity, conventional critical-dimension (CD) mea surements may not afford the level of process control required for effective device production. By comparing recorded top-down scanning-electron-microscope (SEM) images to a predefined reference image, Pattern Quality Confirmation (pQC) enables a more detailed analysis of measurements captured by KLA-Tencor 8xxx CD-SEMs. An example of the utility of this additional information is discussed for a metal interconnect level patterned with a deep-ultraviolet (DUV) photolithography process. In particular, we demonstrate that, for certain ranges of focus-exposure conditions, conventional post-develop CD measurements remain well within specification; however, when etched, the resulting metal-line CDs are significantly below the lower specification limit. The pQC image analysis results predict the observed post-etch CD variations and, consequently, offer sensitivity to yield-limiting focus drifts and excursions, enabling effective product-dispositioning (rework) decisions.

Introduction

At virtually every processing step, modern semiconductor manufacturing relies on highly automated metrology for process control. For lithography and etch processes, automated critical-dimension scanningelectron microscopes (CD SEMs) fill this role; however, there exists a set of yieldrelevant excursions, e.g., profile changes, scumming, etc., which can elude detection by standard CD measurements. The contraction of multi-dimensional image information into a single CD value can obscure such subtle effects, which are evident in the images themselves. Pattern Quality Confirmation (pQC) is a method that utilizes some of this image information to enable detection of subtle changes as part of a fully-automated CD SEM metrology step. In effect, a comparison is 56

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made between a known â&#x20AC;&#x153;goodâ&#x20AC;? template, and the image obtained during measurement of the feature of interest. A correlation score provides the metric of comparison; a perfect match returns a score of 100, no match returns a score of zero. On KLA-Tencor 8xxx CD SEMs, this measurement option is available in two flavors: a onedimensional or linescan pQC correlation score, and a two-dimensional or image-based pQC correlation score. Both one- and two-dimensional pQC measurements have been demonstrated to provide additional value to top-down CD SEM measurements; 1,2,3 in this work, we explore the use of two-dimensional pQC in monitoring an aluminum-interconnect patterning process. The process of interest employs deep-ultraviolet (DUV) photoresist application and exposure techniques along with a conventional metal-etch process. For this process and layer, a thick layer of photoresist is required to pattern the desired interconnect structure, and the lithography process is found to be relatively sensitive to variations in exposure-tool focus and energy. In turn,

etch processes in general are sensitive to photoresist sidewall profile, providing a challenge to overall etched-linewidth control and associated interconnect performance and reliability. Method

For this work, a conventional patterning process currently in production use was employed, allowing us to directly assess the effectiveness of pQC in a productmonitoring scenario. Metallized wafers (AlCu+Ti/TiN) were coated with an 890 nm thick film of commerciallyavailable deep-ultraviolet (DUV) photoresist, exposed using a binary reticle in a Nikon NSR2205EX14D step-and-repeat KrF exposure tool, and developed using a 60-second puddle process with a 0.26N (2.38 percent TMAH) developer. This process has a (known) nominal best focus of 0.1 µm and a nominal best exposure of 48 mJ/cm2. For the purposes of this study, photoresist linewidth and profile were intentionally modulated using a standard focus-exposure matrix centered at the nominal best values. Focus values were varied from -0.9 µm to 0.9 µm in increments of 0.2 µm, with exposures from 40 mJ/cm2 to 56 mJ/cm 2 in increments of 2 mJ/cm2. Both conventional CDs (linewidths) and pQC correlation scores were recorded for both isolated and dense features; in addition, sidewall angles were inferred using an edge-width algorithm. Wafers were then etched using a standard metal-etch process, and postetch CDs were then measured. All measurements were recorded using standard algorithms available on the KLA-Tencor 8100XP CD SEM. Linewidth and pitch algorithms are standard practice and are not described here; a brief discussion of pQC and edge-peak width algorithms is presented here for completeness. Detailed discussions are available elsewhere.4,5 The pQC algorithms are available in both one- and two-dimensional varieties; the two-dimensional version was employed for this work, applied to quasi-onedimensional structures (lines). This measurement reports a pixel-by-pixel correlation with a reference, or “golden” image recorded from a successfully patterned feature. Here, we recorded reference images at a magnification of 25kX, in fields printed at the known best exposure of 48 mJ/cm 2 and a focus value of -0.1 µm. The selection of these values will be discussed in the Results section. The images are shown in Figure 1, for both isolated and dense features.

F i g u re 1. Reference, or “golden ”, images re c o rded fo r i sola ted (l eft) an d dense (right) features. These image d ata are used by the p QC al gorithm for compari son wi th images re c o rded for the measure m e n t si te of interest.

Edge-peak width measurements employ CD SEM linescans to infer the effective width of the transition (sidewall) region evident in image data by computing the distance between a predefined rising-edge threshold value and an accompanying falling-edge threshold value. To further understand the correlation between sidewall profile changes and image-based pQC scores, we also employed atomic force microscopy (AFM) to directly probe the sidewall angle. Of course, this technique is impractical for production line monitoring, however, it provides a direct, high-resolution measurement of the sidewall profile. Klarity ProDATA, a commercially available software package, was used for data analysis and presentation throughout this work. This package enables rapid, automated analysis of conventional critical-dimension and pQC data to produce results such as Bossung curves, process windows, and overlap process windows. Examples of each are found in the Results section, below. Results

The post-develop response of isolated and dense line critical dimensions, with respect to changes in focus and exposure, is shown in Bossung curves in Figure 2. These particular scribe-line structures have CD targets of 0.33 µm and 0.22 µm for isolated and dense linewidths, respectively; specification limits of ±10 percent are imposed on the process. As seen in Figure 2, each feature exhibits a reasonable range of focus and exposure values for which CDs are printed within specifications. Individual process windows computed for these two features, along with the overlap process window, are shown in Figure 3. Individually, each feature exhibits an acceptably large depth of focus and exposure latitude, Fall 2001

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F i g u re 2. Boss ung cur ves for isolated (left ) a nd dense ( righ t) lines, with CD specificat ion (target (10%) lines superimposed. Bo th axes re p o r ted i n un its of micro n s .

in addition, both windows are centered at approximately the same focus and exposure values. The overlap process window is determined primarily by the behavior of the isolated line; Klarity ProDATA process-window overlap analysis indicates a best focus of 0.08 µm with a depth of focus of 0.77 µm, and a best exposure of 45.4 mJ/cm2 with an exposure latitude of 4.5 mJ/cm2. These values compare favorably with the known best values, indicating that the lithographic process is behaving normally. The next step in this process is pattern transfer from the photoresist to the metal film, producing the metal lines for back-end interconnect. Representative results for isolated-line CDs, measured after completion of the etch process, are shown in Figure 4. These post-etch

linewidths are measured for metal lines printed on the same wafer at best exposure (48 mJ/cm2) with various values of focus. For relatively small values of positive defocus, we observe a precipitous decrease in etched width of the isolated line, well below the imposed lower specification limit of 0.55 µm. Of course, an unintended linewidth (cross-sectional area) change can result in associated effects on device performance and reliability, such as changes in interconnect resistance, power dissipation, and probability of electromigration failure.6 There is no such decrease observed for negative focus values, and the near-symmetry of the isolated-line Bossung curve for post-develop data (Figure 2, left) has

F i g u re 3. Individual process windows computed for each feature, along

F i g u re 4. Criti cal dimensio n ( wi dth) of isol ated metal line f ollowing

with overlap process window. Overlap window describes focus-exposure

et ch. Note t he decrease i n l inewi dth for moderat ely positi ve focus

region for wi thin-s pecification pri nting of both fea tures simultaneous ly.

deviations. Imposed lower specification limit of 0.55 µm is also shown.

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F i g u re 5. CD-SEM images an d s uperimposed electr on-i ntensity profiles of isolated li ne print ed at vari ous focus values and best d ose (48mJ/c m2). F rom left to right, the nomina l f ocus varies fr om –0.5 µm to +0.5 µm in 0. 2 µm i ncre m e n t s .

been lost in the etch process. Interestingly, this postdevelop CD data exhibited a rather moderate decrease with increasing positive focus and gave no indication of this post-etch behavior. This is problematic in the context of product dispositioning. In this positive-focus regime, post-develop CD measurements do not allow accurate prediction of post-etch metal linewidths, substantially decreasing the effectiveness of productrework decisions. Examination of post-develop SEM image data (Figure 4) provides an indication of the root cause of the observed reduction in post-etch linewidth. In particular, a continuous qualitative change in the image of the sidewall regions can be observed with increasing focus; we infer from these images that the photoresist profile is becoming more rounded or sloped for positive focus values. Such a resist profile would be less resistant to etch at the edges of the line, and would be expected to

produce narrower lines than a profile with a closer-tovertical sidewall. Given the image-to-image comparison performed by the pQC algorithm, the qualitative changes in image data such as those observed in Figure 5, it is reasonable to expect these changes to be reflected in pQC correlation scores. “Bossung-style” plots of post-develop pQC scores, with the corresponding conventional CD-based Bossung curves are show in Figures 6 below for the isolated line. Qualitatively, the isolated-line pQC correlation score data exhibits a more rapid decrease for increasing positive focus than does the CD data, reflecting the change in sidewall behavior inferred from the SEM images of Figure 5. This positive-focus decrease is reminiscent of post-etch CD data of Figure 4. As described in the Method section, pQC template images were recorded at best exposure, but with a focus of

F i g u re 6. Isolat ed-l ine Bossung cur ves fo r p QC correlation scores (left), an d CD measurements (right). Corre lation scor es exhib it a rapid decre a s e with i ncreasi ng fo cus, tr acking the (quali tative) pos t-d evelop imag es.

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(48 mJ/cm2) and focus values ranging from -0.5 µm to +0.5 µm. To enable this comparison, each value was normalized by the maximum value attained by that data type (e.g., post-develop CD) over the focus range. In addition, SEM images are included for reference. Here, it is clear that post-develop CD has failed to capture the sidewall variations qualitatively observed in the images. As discussed above, these sidewall variations are the root cause of etched-linewidth reduction associated with positive focus values; pQC scores are in agreement with both the qualitative changes in the sidewall images and the reduction in etched linewidth. Post-develop pQC correlation scores are seen to provide a F i g u r e 7. Comparison of isol ated-li ne post -develop and post -etch C D mea suremen ts with pQC quantitative, predictive metric of post2 c o rrelation scores, as a function of focus. All features printed at a constant exposure of 48 mJ/cm . etch CD variation—a variation that Post -develo p SEM i mages are a lso shown for each f ocus va lue. Values for ea ch quantity are p o s t -develop CD measurements were n o rma lized by the maxi mum value for that quantity t o allow di rect compar ison of all three unable to predict. The additional m e a s u rements. Note the devia tion between post-d evelop and post-etch CD measurement s f or information provided by pQC analysis, positive val ues of focus. using automated top-down CD SEM image data alone, is seen to enable -0.1 µm, an offset of (negative) 0.2 µm from the known quantitative and reliable product-dispositioning best focus value. This value was chosen to enhance sen(rework) decisions. As discussed above, such decisions sitivity of the reported correlation score to changes in were not possible on the basis of conventional linewidth the sidewall region, while minimizing its sensitivity to measurements. changes in absolute feature size in the region of interest. The SEM images presented in Figure 5 are indicative A direct comparison of post-develop CD and postof a change in sidewall profile with changing focus; a develop pQC data with post-etch CD data is found result mirrored in the image-based pQC results. To in Figure 7 for features patterned at best exposure confirm these SEM image results, booted-tip atomic-

F i g u r e 8. Inferred post-develop photoresis t s idewa ll ang les from AFM and top-down CD SEM measur ements. Sidewall angles measured by both techniques as a function of focus (left) corrobora te concl usions made on the b asi s of SEM image data. R easonab le a greement between the di rect AFM techn ique and t he indirect SEM i mage measuremen t i s a lso ind icated (right).

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result not surprising in light of the etch behavior in this regime. Conclusions

F i g u re 9. Isolated-lin e process wind ows for both critical di mension and pQC correl ation score, a s well as t he overlap process wind ow for both. Note th at the positive f ocus limit of the win dow is d etermined by the pQC score, reflecting the i ncreased detection sensitivity of sid ewall angle excursions aff o rded by pQC.

force microscope (AFM) measurements were used to directly measure post-develop photoresist sidewall angle as a function of focus. As can be seen in Figure 8, the AFM results corroborate the inference of a changing sidewall angle. In addition, there is reasonable agreement between directly-measured angles (AFM) and angles inferred from a calculation using edge-peak width measurements and the known photoresist thickness. Interestingly, the dense line data showed much less modulation of sidewall angle with focus, and all metrics discussed for the isolated line were seen to be much more stable with changing focus. Consequently, there is little to be gained by monitoring the dense line alone; in fact, significant risks would be incurred by implementing a control scheme that ignored isolatedline behavior. Finally, we can exploit the increased sensitivity to the observed focus offered by the pQC measurement to revise the usable lithographic process window that results in successfully (within-specification) etched lines. In particular, we define a pQC correlation-score specification of 55 percent, a value chosen to correspond to the level at which etched lines were observed to fall below their lower specification limit (Figure 5). This specification is analogous to the more-familiar 10 percent CD specification, and allows definition of a pQCbased process window in focus-exposure space. As seen in Figure 9, the pQC-based process window allows a significantly smaller range of positive focus values, a

In this work, we investigated the patterning of metal lines using both conventional critical-dimension measurements and pQC image analysis. We find regimes where measured post-develop CDs are still well within specification, but image-based post-develop pQC correlation scores have dropped to less than 55 percent of the nominal value. Examination of SEM images through the focus-exposure range indicates modulation of sidewall angle that has been captured by the (image-based) pQC correlation score, but has eluded detection by conventional CD measurements. This sidewall modulation is also corroborated by atomic-force microscope (AFM) measurements, which show good agreement with image-based measurements. This sidewall angle modulation has a significant effect on post-etch linewidths; for positive focus values, a reduction in post-etch CDs to values well below the specification limits is observed. Conventional postdevelop CD measurements were unable to predict this behavior, however, post-develop pQC correlation scores were an effective predictor of the post-etch linewidth variation. The capability to quickly and accurately measure these additional profile characteristics lends a powerful tool in detecting a variety of excursion types that further reduce already challenging depths-of-focus. The results presented here illustrate some of the shortcomings of conventional CD measurements in monitoring this process, however, they also illustrate the richness of top-down SEM image data beyond these conventional measurements. Acknowledgements

We wish to thank Vladimir Ukraintsev, Raymond Yip, and Sunil Desai for their expert assistance with the measurements. References 1 . B. Choo, T. Riley, B. Schulz, and B. Singh; â&#x20AC;&#x153;Automated P rocess Control Monitor for 0.18 Âľm Technology and Beyond,â&#x20AC;? M e t ro l o g y, Inspection, and Process Control for Microlithography XIV, Neal T. Sullivan, Editor, Proceedings of SPIE Vol. 3998, pg. 218-226, SPIE, Bellingham, WA, 2000.

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2 . J. Allgair, G. Chen, S. Marples, D. Goodstein, J. Miller, and F. Santos; “Feature Integrity Monitoring for Pro c e s s C o n t rol Using a CD SEM,” Metro l o g y, Inspection, and Process Control for Microlithography XIV, Neal T. Sullivan, E d i t o r, Proceedings of SPIE Vol. 3998, pg. 227-231, SPIE, Bellingham, WA, 2000. 3. D. M. Goodstein, B. Choo, B. Singh, “Correlation Flagging of i-Line Lithographic Process Drift,” KLA-Tencor CD SEM Users Group Meeting, Santa Clara, CA, 1999. 4. 8xxx Series CD SEM Operation Manual (v3.1.X), KLA-Tencor Corporation, 2000.

5. 8xxx Series CD-SEM Application Note, “Measuring Edge Peak Widths for Process Characterization,” KLA-Tencor Corporation, 1999. 6. S.M. Sze, Editor, VLSI Te c h n o l o g y, Second Edition, McGraw Hill, 1988.

A version of this article was originally published in SPIE Proceedings Vol. 4344, paper 108, entitled “Using Pattern Quality Confirmation to Control a Metal-level DUV Process with a Top-down CD-SEM” by Chien-Sung Liang; Haiqing Zhou. Mark Boehm, Ricky Jackson (KFAB Photolithography Module, Texas Instruments); Chih-Yu Wang, Mike Slessor (KLA-Tencor Corporation).

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Summer 2001 Yield Management Solutions

When it comes to copper yield, we have all the right elements. Especially if you’re interested in getting to high-volume copper production faster than anyone else. In fact, we recently helped a major fab do just that. By getting fast and

For more about how we helped a leading copper fab dramatically shorten its time to yield, visit

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were able to decrease defectivity by 10X in a single month. Which let them ramp to production faster. And hit ROI sooner. But helping accelerate yield is our specialty. So it’s no wonder that more successful fabs are turning to us. Must have something to do with our chemistry. For more information, please visit www.kla-tencor.com, or call 1-800-450-5308. ©2001 KLA-Tencor Corporation

Accelerating Yield

Product News AIT XP

The AIT XP is the first commercially available wafer inspection system to combine both high speed and high sensitivity in all die regions. Dubbed NexTekTM, this single-pass capability leverages multiple optics and intelligent control to dynamically adjust and optimize both inspection speed and sensitivity for each region of the device. Combining the extreme sensitivity needed to find killer defects in today’s most advanced devices together with high-speed, single-pass intelligent inspection, the AIT XP is ideally suited for global chipmakers that produce multiple types of advanced devices incorporating 100 nm and smaller design rules. Its enhanced nuisance-defect filtering and noise suppression make it ideal for inspection in copper CMP production. With the ability to set different contrast and threshold values for varying backgrounds, the AIT XP can inspect an entire patterned wafer in as little as 80 seconds with a high rate of defect capture, providing an effective increase in throughput of up to 75 percent compared to current systems. The AIT XP also features ease of use combined with power and flexibility, thanks to significant improvements such as reduced recipe setup time (as low as eight minutes), a streamlined user interface, and 5.1 Software additions such as the Template Feature. This feature enables consistent recipe setup across like products through the use of templates with a minimum of operator interaction and time.

Surfscan SP1DLS

The first 300 mm inspection tool that provides brightfield, darkfield, and nanotopography defect information in a single scan. Featuring a dual-laser, simultaneous brightfield-darkfield system, the Surfscan SP1DLS is designed to capture the wide variety of yield-limiting defects (down to 50 nm) at high throughput (up to 125 wafers per hour) to accelerate yield learning at 130 nm, 100 nm and smaller design rules. The combination of high sensitivity at high throughput with real-time defect classification makes the Surfscan SP1DLS one of the industry’s lowest cost-of-ownership tools. The system enables rapid capture and characterization of critical defect types on blanket film wafers during lithography, deposition, etch and chemical mechanical planarization (CMP) processing, thereby reducing the risk to product wafers. The SP1DLS is also available with wafer-edge handling, which allows the tool to non-destructively inspect the backside of wafers for contamination – a critical requirement for 300 mm double-sided polished wafers. It also features RTDC (Real-Time Defect Classification), which enables fabs to achieve faster development and ramps or maintain yield during manufacturing through rapid failure analysis and root-cause analysis.

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iADC

iADC (Inline Automatic Defect Classification) is the newest component of IMPACT XP, KLA-Tencorâ&#x20AC;&#x2122;s comprehensive, advanced, and easy-to-use ADC solution for line and tool monitoring, baseline yield improvement, and excursion problem-resolution use cases. iADC provides more accurate binning for faster analysis and real-time classification of defects during inspection with minimal impact on throughput, thus speeding time-toresults. Available on the 2350/2351 high-resolution imaging and eS20XP advanced e-beam inspection systems, iADC is a revolutionary technology that delivers trending by killer-defect type for excursion monitoring while filtering out nuisance defects. The use of iADC during e-beam inspection enables users to separate and identify critical yield-limiting defects into meaningful categories such as electrical versus physical. It is also enables users to create intelligent, effective SEM sampling for defect review, thus reducing the load on the SEM and ultimately lowering SEM cost of ownership.

SpectraCD

The SpectraCD is an advanced metrology tool designed for in-line CD measurement and process monitoring. The SpectraCD combines Spectroscopic CD technology with Thin Film Spectroscopic Ellipsometry to provide semiconductor manufacturers with the most comprehensive Litho and Etch process control feedback available. The product offering includes an offline SpectraCD Library Generation System providing complete ownership of the SpectraCD library generation process. The system accurately determines CD (at any percent on the profile), line height or trench depth, sidewall angle from spectroscopic CD measurements on special grating targets. The cross section profile is also determined. The SpectraCD measurement technology is complemented by the full range of thin film measurements presently available on KLA-Tencorâ&#x20AC;&#x2122;s industry leading ASET-F5x. The SpectraCD addresses both CD and thin film process control needs in a single production-worthy tool.

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Yield Management Solutions

Product News PRECICE

PRECICE is the industry’s first production-worthy in-situ film thickness and end-point control system for copper CMP. PRECICE uses a combination of optical and eddy-current technologies that allow chipmakers to run multiple steps within the CMP process with a high degree of repeatability. PRECICE’s eddy-current probe provides accurate thickness measurements in real time, and enables the CMP tool to dynamically adjust for film variations to ensure proper CMP process control at all times. It also automatically compensates for temperature and pad-wear effects that occur during CMP that might otherwise create false measurement. PRECICE’s optical probe uses a single-wavelength, multi-angle reflectometer, which provides more comprehensive data than competing single-angle laser reflectance systems. It also eliminates false end-point reporting—a fatal error in volume production

ASET-F5x Wafer Bow Wafer Stress Capability (WBWS)

This optional feature for 300 mm monitor wafers allows for measurement flexibility and improved cost of ownership by adding wafer bow wafer stress capability to the ASET-F5x thin film metrology platform. WBWS can be determined using the measured film thickness or a thickness entered at run time for opaque films. The combination of film and stress metrology on the same tool improves CoO by reducing footprint and eliminating the cost of two separate systems. The ASET-F5x stress option along with the ASET-F5x CoO and automation features meets the requirements of a fully automated 300 mm fab.

Klarity ACE 5.5 Advanced Correlation Engine

Klarity ACE is an enterprise business application designed to meet the analysis needs of semiconductor professionals, including the defect, yield, product, process, integration and R/D engineering communities. It integrates nearly all available fab and test data, and provides the capability to correlate them to identify key parameters pertaining to yield. Klarity ACE 5.5 – the latest version of KLA-Tencor’s yield analysis software –incorporates several new features that dramatically improve ease of use and reduce analysis time by more than 30 percent. It can differentiate between random and systematic yield problems, providing users with the data they need in order to take appropriate corrective measures.

Fall 2001

Yield Management Solutions

Printability Analysis Stepper Simulator

The Printability Analysis Stepper Simulator™ (PASS) is a new software tool that can provide photomask manufacturers with significant time and cost savings by automating the reticle defect analysis process and reducing the amount of repair work needed for sub-wavelength photomasks. With this new tool, KLA-Tencor’s suite of advanced reticle inspection systems now has the ability to characterize and simulate the printability of defects on these advanced photomasks – providing better process control and reducing reticle manufacturing cycle time. PASS enables mask manufacturers to characterize any small defect or critical dimension (CD) error on the reticle without having to move the photomask from the inspector to an offline aerial defect-imaging tool. In addition, PASS automatically simulates how the defects will print onto the wafer before the photomask is shipped to a customer or used in production.

PROLITH 7.1 Advanced Optical Lithography Simulation

PROLITH is the leading lithography simulation tool for the semiconductor industry. PROLITH provides advanced optical lithography modeling capabilities that increase lithography equipment utilization, enable more rapid process development and maximize yield. It simulates the complete optical lithography process and provides accurate three-dimensional representation of the photoresist pattern. PROLITH 7.1 is the latest version of KLA-Tencor’s advanced optical lithography simulation software. PROLITH 7.1 simulates three-dimensional resist patterns for 193 nm lithography, and calibrates model parameters to experimental CD and thickness results. This new version also enables quick screening of lithography illumination and mask design options.

Fall 2001

Yield Management Solutions

AIT XP has arrived. And wafer inspection will never be the same.

AIT XP with NexTek

Now that AIT XP with NexTek™ has been unveiled, the world of wafer inspection

• Adaptive mode technology

is about to evolve. For one thing, choosing between speed and sensitivity will be a

• Higher speed with maximum sensitivity

thing of the past. That’s because NexTek’s dynamic technology adjusts sensitivity in

• Single pass for all regions

real time – without masking or multiple scans. So you get the whole picture in a

• Faster recipe setups

single pass. Higher defect capture. Much faster effective throughput. And an end to compromises. Plus, our automated recipe setup cuts engineering time by up to 30 percent. All of which is sure to make other laser scanning methods extinct. For more information, please visit www.kla-tencor.com/nextek, or call 1-800-450-5308. ©2001 KLA-Tencor Corporation. NexTek is a trademark of KLA-Tencor Corporation.

Accelerating Yield