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S O L UYield Acceleration T Strategies I O N S for the Semiconductor Industry

SPECIAL FOCUS: Pattern-Limited Yield 15

COVER STORY — WHERE HERE IN N THE THE WORLD ORLD IS S THE THE PROCESS ROCESS YIELD IELD WINDOW INDOW?

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GETTING WHAT YOU’RE ENTITLED TO

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CONSIDERING OVERLAY METROLOGY IN THE DFM DISCUSSION

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Shining Spotlight on SOI Wafers

E-beam inspection can be a powerful ally in uncovering subtle etch variances in SOI wafers.

24 From One Side to Another When it comes to wafer quality, you can’t afford not to watch your back.

36 Getting What You’re Entitled To A new paradigm in design verification enables earlier corrections and reduction of pattern-dependent yield loss.

49 Considering Overlay Metrology in the DFM Discussion A look at the advantages of casting a wider net when defining overlay metrology.

Cover image by Jovita Rinkunaite, KLA-Tencor

Cover

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15 Where in the World is the Process Yield Window?

Explore process control methodologies that can reduce harmful hidden systematic errors.

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Product

WEB Exclusive Pinpointing Causes of Overlay Metrology Uncertainty Learn more about a new method to identify and quantify individual contributors of overlay metrology uncertainty.

News

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Archer AIM+ Advanced optical overlay metrology

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Archer XT+ Advanced overlay metrology

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Phoenix Handler Standardized platform for better performance and cost control

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Online Recipe Services Faster tool recipe qualification and troubleshooting

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SP2 Wins 2005 Best Product Award Surfscan SP2 unpatterned wafer inspection system

www.kla-tencor.com/magazine Yield Management Solutions is published by KLA-Tencor Corporation.

To receive Yield Management Solutions, subscribe online at: www.kla-tencor.com/magazine

Sections 4

Editorial: The Future’s All About Cost

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Awards: Levy Honored by Silicon Valley Engineering Community

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Spotlight on Lithography

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Yield Management Seminar Series

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New Product: 2800 Ultra-broadband Brightfield Inspector

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Awards: Vaez-Iravani Named First KT Fellow

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KLA-Tencor Trade Show Calendar

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New Product: Puma 9000 Next-generation Darkfield Inspector

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Awards: Tribute to Women and Industry Honor

For literature requests, visit: www.kla-tencor.com/company/inquiry MG-YMSFAL-08/05 For information, visit: www.kla-tencor.com

©2005 KLA-Tencor Corporation.

All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation.

Products in this document are identified by trademarks of their respective companies or organizations.

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The Future’s All About Cost…

Many of us have pondered about the end of the classical Moore’s Law, the prediction that integrated circuit functions would double in density every 18 months. For more than 20 years, Moore’s prediction has relied primarily on device scaling. That era is coming to an end, partly due to the failure of the 157 nm and EUV lithography roadmaps and partly due to more fundamental limitations such as power dissipation in small devices. Ultimately, it all boils down to cost. If new materials, device architectures, and means of production are significantly more costly or less efficient, they will not be used; and older technologies will be extended. Currently, the semiconductor industry is at such a crossroad.

Most semiconductor manufacturers expect 193 nm immersion lithography to remain the dominant patterning technology through the 32 nm technology node. Even now, the interaction of more complex designs with shrinking process windows is having an impact on parametric yield in early production. The semiconductor industry is addressing this problem using design for manufacturability (DFM) and advanced process control (APC) strategies. The exact definition of DFM and APC can vary significantly with context, particularly when comparing foundry, logic, and memory products. In each case, however, the primary goal of DFM is to enlarge the process yield window, and the primary goal of APC is to keep the process in that yield window.

Enabling DFM and APC strategies with metrology will require significant innovation. As a minimum, DFM will require feeding forward design intent, simulator output, layout clips, and DRC hot spots to expedite

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setup of measurement tools. Current design-rule-check (DRC) and aerial image modeling at best focus and exposure conditions is increasingly unreliable. In the future, process window-aware approaches will require powerful full-chip simulators that can accurately predict and measure developed patterns in resist, along with a super-computing environment that can produce results in an acceptable timeframe. To control development costs, the conversion of data to information, knowledge, and decisions will be taken as far upstream as possible.

On the process control side, implementing an APC strategy requires feeding forward both process context and measurement data. In the future, we know that process context and measurement data must increase dramatically to support multi-variate control at the lot, wafer, field, die, and intra-die levels. In addition, yield and performance losses are often caused by integration issues or combinations of profile, shape, roughness, thickness, and pattern placement errors. For these applications, additional measurement types are required, creating a need to decrease the cost and increase the yield-relevance of each measurement.

Despite the cost, DFM and APC are growth areas for the semiconductor industry. The economic trade-off between yield loss and process control is driving an increase in capital and service expenditure to support more sophisticated DFM and APC strategies. The case for linking design, layout, mask, and wafer processes with metrology is compelling. Greater complexity is offset by the advantage of greater access to adjustment; an array of strategies generates higher return than just one.

Yield Management

SOLUTIONS E D I T O R - I N -C H I E F Uma Subramaniam

SENIOR EDITOR Christine Young

CONTRIBUTING EDITORS David Moreno Lisa Garcia

That brings us back to Moore’s Law. The extension of Moore’s Law can no longer rely on scaling alone. Progress may depend more on innovation in materials, nanotechnology, architecture, and packaging. For example, a number of microprocessor manufacturers are introducing multi-core processors that promise increased speed and functionality with lower power dissipation. Clearly, whether the market is my teenage son, who owns every imaginable video game, or a global economy that hungers for productivity gains, there will always be customers for the capability that Moore’s Law can deliver. In fact, a less than prophetic engineer once told me that a 20-MHz processor was more than adequate for desktop computing and that no one would ever need an upgrade. I replied that human eye-motor response is roughly 250 milliseconds and, ideally, results should be provided within this timeframe. I’m still waiting...

PRODUCTION EDITOR Siiri Hage

ART DIRECTOR AND PRODUCTION MANAGER Carlos Hueso

DESIGN CONSULTANTS Harry Wichmann, Terry Rieckhoff, Jovita Rinkunaite, Inga Talmantiene

CIRCULATION EDITOR Nancy Williams

KLA-Tencor Worldwide CORPORATE HEADQUARTERS KLA-Tencor Corporation 160 Rio Robles San Jose, California 95134 408.875.3000

INTERNATIONAL OFFICES KLA-Tencor France SARL Evry Cedex, France 33 16 936 6969 KLA-Tencor GmbH Munich, Germany 49 89 8902 170 KLA-Tencor (Israel) Corporation Migdal Ha’Emek, Israel 972 6 6449449

Dr. Kevin M. Monahan Parametric Solutions Group KLA-Tencor Corporation

KLA-Tencor Japan Ltd. Yokohama, Japan 81 45 335 8200 KLA-Tencor Korea Inc. Seoul, Korea 822 41 50552 KLA-Tencor (Malaysia) Sdn. Bhd. Johor Bahru, Malaysia 607 557 1946 KLA-Tencor (Singapore) Pte. Ltd. Singapore 65 6367 6788 KLA-Tencor Taiwan Branch Hsinchu, Taiwan 886 3 552 6128 KLA-Tencor Limited Wokingham, United Kingdom 44 118 936 5700

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Shining Spotlight on SOI Wafers A New Approach to Detecting Subtle Etch Variations Alexander Ache and Nicole Rowland, IBM Corporation Kevin Wu, KLA-Tencor Corporation

In advanced fabs, silicon-on-insulator (SOI) wafers are becoming increasingly popular for their low power consumption and high processing speed, as compared with conventional wafers. This growth has generated a need to implement electronbeam inspection (EBI) of SOI wafers with a new approach. While EBI has proven its effectiveness on bulk material, the same needed to be demonstrated with SOI wafers. IBM’s 300 mm production fab applied EBI to inspect its SOI wafers for Reactive Ion Etch (RIE) process variation on tungsten local interconnect levels. Through this process, IBM was able to demonstrate that its eS31 system was able to find subtle etch variances.

Introduction

Electron-beam inspection (EBI), through the use of voltage contrast, is used extensively throughout the industry to identify inline electrical failures. In fact, EBI has become a widely accepted addition to semiconductor fabrication yield strategies. Like other inspection strategies, EBI needs to be sensitive to critical defects of interest (DOI) and also be stable. It also should provide minimum charging and contain low amounts of nuisance. However, it is becoming apparent that in order to meet these objectives for silicon-on-insulator (SOI) technology, a new approach to EBI is required.

Unlike conventional wafers, the SOI wafer contains three layers. The first is a singlecrystal layer of silicon with a thickness of 1 mm or less. The other two consist of a base silicon substrate and a thin insulator that electrically insulates the single-crystal layer from the substrate. The thin insulator prevents the parasitic or incidental capacity usually induced between a device and the substrate for conventional wafers. The result is lower power consumption and higher

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processing speeds. SOI is becoming more popular in advanced semiconductor fabs for this reason.

EBI methodologies and different materials

Conventional substrate

EBI has been proven effective on bulk material, especially for the inspection of tungsten (W) plug integrity.The voltage contrast signal is also easily reproducible with an ion beam, making the affected contact easy to redetect in cross section. Figure 1 shows a typical open W contact after fill and planarization that was detected through voltage contrast inspection.

Figure 1. Voltage contrast (left) of W contact indicating underetch (right) on conventional wafer.

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SOI substrate

The concept of SOI intuitively suggests that the insulator box would prevent a direct path to a grounded state and, therefore, prevent the generation of strong voltage contrast for EBI. Empirically, however, voltage contrast can be obtained on SOI wafers as seen in Figure 2, and is most likely the result of capacitance variations. Additionally, the top thin silicon layer may serve as an electron sink. Here we see voltage contrast W contact connected to PFET indicating an open.

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Figure 3. Material contrast seen through an etched local interconnect level prior to W fill.

Figure 2. Voltage contrast of W contact indicating underetch on SOI wafer.

SOI substrate and W local interconnect �������� Some difficulty arises when inspecting for voltage contrast

on a W contact layer where the W structures act as local ��� lines may bridge interconnects. These short metal several devices as well as the shallow trench isolation (STI). In this situation, the capacitance variation that causes voltage contrast on a filled W structure may become redundant and no signal is observed. However, if the inspection occurs prior to metallization fill, an underetch signal can be seen. Figure 3 illustrates the EBI image of unfilled W local interconnects just after RIE etch.

It is important to note that EBI at this layer requires charging effects to be minimized. A capability on the KLA-Tencor eS3X was used to predose the wafer with electrons, which reduced localized charge non-uniformity.

Within one line structure, the gray scale can alternate between being completely black and being bright white. This is the result of differing secondary yield coefficients for the two materials located at the prior level. The black regions represent regions of STI. The bright regions represent diffusion or polysilicon regions that are covered with silicide. Figure 4 shows a normally dark region now appearing bright.

Figure 4. Material contrast seen through an etched local interconnect level prior to W fill.

The defect from Figure 4 and others in the vicinity are believed to be the results of subtle barrier nitride underetch. The TEM cross section image of this area can be seen in Figure 5.

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Figure 5. Material contrast seen through an etched local interconnect level prior to W fill.

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SOI vs. conventional substrates

The conditions needed to generate an optimum EBI signal for detection of open W contacts is presented in Table I. The table shows the conditions for both conventional and SOI wafers for pre- and post-W metallization. e-Beam Landing Energy (eV)

e-Beam Current (nA)

Conventional Wafer Pre-W Fill

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Case study: Seeking subtle underetch on W local interconnect

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The overlay defect wafer maps can be seen in Figure 6.

There does seem to be some degree of regionality to the defects, even across the various process conditions.

Figure 7 shows the results, and indicates that process split A is the best choice for the RIE process condition.

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A high extraction field was used on the wafer in order to maximize the signal. In addition, the wafer was preconditioned with a negative charge prior to the inspection. The inspection pixel size was done at .10 µm in a die-to-die comparison.

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A case study was conducted at IBM’s 300-mm production facility in search of subtle underetch on W local interconnect structures. The goal of the experiment was to determine the optimum process conditions for achieving proper selective-etch conditions. A group of 10 wafers was split into five distinct processing conditions for inspection on the KLA-Tencor eS31.

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Inspection for voltage contrast events on SOI wafers requires additional attention compared to the conventional wafer counterpart. However, this study has proven that electrical defectivity can be identified through e-beam inspection and voltage contrast is still a viable method.

Care must be taken to establish proper beam conditions that do not induce high levels of charging across SOI wafers.

This article is based on a paper that was originally presented at ASMC 2005.

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Photo courtesy of Dr. Jay Pinson.

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When asked about his proudest engineering accomplishments, Kenneth Levy, Chairman of the Board at KLA-Tencor, discusses the efforts that went into the development of KLA Instruments’s first product, the KLA 100 Automated Photomask Inspector. He also doesn’t hesitate to applaud the technical team behind this and subsequent innovations, noting,

“I am as proud of the technical excellence of the KLA-Tencor team as I am of the products we design and build.”

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Over the past 30 years, Levy has been at the forefront of the semiconductor capital equipment industry. In 1976, he founded KLA Instruments Corporation, which later merged with Tencor Instruments to become KLA-Tencor. Through the years, he has worked with some of the brightest minds in the industry.

For his contributions and efforts, Levy was named earlier this year to the Silicon Valley Engineering Hall of Fame. This year’s class includes Dr. Douglas Engelbart, inventor of the computer mouse; Dr. Dan Maydan, President Emeritus of Applied Materials; Dr. David Patterson, Chair of EE and Computer Science at UC Berkeley; and Dr. T.J. Rodgers, founder, President and CEO of Cypress Semiconductor. The honor, in its 16th year, celebrates the professional achievements of Silicon Valley engineers as well as their service to the profession and their contributions to the community.

World-class talents drive innovation The road to developing the KLA 100 automated photomask inspector was marked by two major marketing/engineering realizations that proved to be fundamental in the development of the company, according to Levy. First, there was the recognition that defect density on photomasks was beginning to limit semiconductor manufacturing yields and that the imagery on the photomask was becoming too complex for people to inspect. Knowing that newly developed sensors and semiconductor devices would enable a solution to this challenge to be engineered, Levy’s team seized the market opportunity to create the photomask inspection tool.

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...with Induction into

Engineering Hall of Fame The second major realization came with the awareness that the skills amassed in designing and manufacturing photomask inspection systems could be applied to automating wafer inspection. Explains Levy, “To accomplish both of these innovations, I realized that it would take a world-class team of technical people to succeed. We were fortunate to assemble a great team in 1977. We have an even better team today.”

Smaller devices will mean greater challenges ahead Levy’s passion for semiconductor-related technologies continues to be fueled by shrinking device geometries.

“When I entered the semiconductor capital equipment field in 1969, advanced geometries were well over 10 µm,” he notes. “At that time, it was almost universally accepted that the physics of optical litho-graphy would carry us to 1 µm and then run out of gas. Today, we know that optical lithography will take us below 0.06 µm.”

Levy continues: “As lithography allows smaller and smaller devices, controlling the semiconductor manufacturing process becomes increasingly more difficult. That puts pressure on us to push the capabilities of our systems to detect and measure ever smaller artifacts and dimensions. It’s a great challenge for us, in all of our business segments.”

Pearls of wisdom One of the objectives of the Silicon Valley Engineering Council, which presents the Hall of Fame award, is to promote career development of engineers and other technologists. In his leadership role, Levy offers to new engineers some simple yet compelling advice:

“Love your work. Engineering is as much a passion as it is a profession.”

“Continue to increase your skill level. The skills that you have today will not be sufficient to sustain you in the future.”

“Work on teams where you can learn from other members.

We get more satisfaction and become more valuable when we work on teams where the other members are exceptional.”

“Volunteer to work on the tough projects. You will learn more and find greater satisfaction from succeeding on projects where ‘the more cautious’ fear to go.”

When he considers the legacy that he’ll leave behind as one of the industry’s renowned technologists, Levy turns the spotlight on the company that he has helped build. Says Levy, “In 2050, I would like people to look at KLA-Tencor and say, ‘That’s a great company. It has made a major contribution to society by continually producing technically advanced products, and, because of that, it has become one of the most successful companies in the world.”

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More Problems with PSM In the last edition of this column, we talked about one of the most vexing problems with alternating phase shift masks – phase conflicts. Arbitrary layouts of brightfield patterns will almost always result in numerous regions where 0 to 180º phase transitions occur (resulting in the printing of a dark line), but where printed features are not wanted. While design and layout methodologies might be found to resolve these conflicts for most, if not all, cases, and double exposures can be used where single exposure solutions are not possible, there are other problems that must also be fixed if alternating PSMs are to become practical. In particular, when phase shifting a small space by etching the quartz, the phase and amplitude transmittance of the space is a function of the space width.

The most common way of shifting the phase of light on a photomask is to change the thickness of quartz that one ray of light must pass through compared to another ray. This is most commonly done by etching the quartz under one space by a set depth d while leaving the quartz of an adjacent space unetched (Figure 1). Since the phase change of light as it travels some distance d through a material of index n is given by 2πνδ/λ, a phase shift between two different paths of the light is controlled by the distance traveled through materials of different refractive indices. For the PSM shown in Figure 1, the nominal phase difference between the two adjacent spaces would be 2π(ν−1)δ/λ where n is the refractive index of the quartz and the air is assumed to have an index of one. From this equation it is easy to see that the ideal etch depth to give a p phase shift would be λ/2(ν−1). These equations can also tell us how an error in etch depth turns into an error is phase. For 193 nm lithography, that translates into about 0.9º phase error per nanometer etch depth error.

The above equations relating phase change to etch depth make an important assumption – that the light is traveling vertically. However, as light goes through the etched quartz hole, it begins to diffract at the bottom of the hole and its directions deviate from a straight line. The smaller the hole, the

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greater this diffraction effect. This causes a difference in the actual phase of the light comChris A. Mack pared to the geometric KLA-Tencor “straight line” approximation, and this difference is a function of the size of the etched space. If these phase errors were not bad enough, diffraction through the etched space causes a second problem: some of the diffracted light doesn’t even make it out of the hole. As a result, the etched quartz space appears dimmer than the unetched space, creating an intensity imbalance in addition to the phase error (Figure 2).

As with the phase error, the degree of intensity imbalance is spacewidth dependent.

Obviously, the real, physical effects of trying to create a 180º phase shift by etching the quartz as described above are very bad for lithography.

The intensity imbalance causes the two adjacent spaces to print as different linewidths, and the phase imbalances cause these spaces to have different best focus settings. How can these problems be fixed? There are a number of possibilities.

In the dual trench method (Figure 3a), both the unshifted and shifted spaces are first etched to some depth, then the shifted space is further etched to create the desired phase shift. This approach can reduce both the phase errors and the intensity imbalance, though not perfectly for all space widths, and it complicates the maskmaking process. In the undercut etch method (Figure 3b), the shifted space is etched somewhat isotropically, causing some undercut of the chrome.

This widening of the etched space reduces the intensity imbalance appreciably. However, to get the intensity imbalance to approach zero, the amount of undercut can become excessive, causing possible reliability problems with the overhanging chrome. Finally, the biased space approach (Figure 3c) uses an OPC tool to bias the etched space larger in order to eliminate the intensity imbalance.

This bias can be adjusted as a function of the space size and pitch in order to eliminate intensity

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imbalance across the full range of features. In general, none of these approaches is perfect at eliminating the phase error as a function of size and pitch. � The most common approach to alternating PSM manufacturing today is to combine the biased space approach with a small amount of undercut. While not perfect, it can provide very good intensity balance and minimum phase error. To determine the best

undercut amount and the optimum bias for each etched space, rigorous simulation of the electromagnetic effects of light � transmission through the mask topography is required. KLA-Tencor’s PROLITH with the Mask Topography Option is �� the ideal tool for these types of simulations. ��

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Figure 2. Intensity imbalance shown for an alternating phase shift mask of equal lines and spaces.

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Where in the World is the Process Yield Window?

Conjoint DFM and APC Strategies for Reducing Hidden Systematic Errors at 65 nm and Below Kevin Monahan and Brian Trafas, KLA-Tencor Corporation

Immersion lithography at 193 nm has emerged as the leading contender for critical patterning through the 32 nm technology node. Super-high numerical aperture (NA), along with attendant polarization effects, will require re-optimization of virtually every resolution enhancement technology and the implementation of advanced process control (APC) at intra-wafer and intra-ďŹ eld levels. Furthermore, interactions of critical dimensions (CDs), proďŹ les, roughness, and overlay between layers will impact design margins and become severe yield limiters. In this work, we show how design margins are reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmodeled, and uncorrectable components. We apply four new process control technologies that use spectroscopic ellipsometry, grating-based overlay metrology, e-beam array imaging, and simulation to reduce hidden systematic error. Feedback of super-accurate process metrics will be critical to the application of conjoint design for manufacturability (DFM) and APC strategies at the 65 nm node and beyond. Manufacturing economics will force a trade-off between measurement cost and yield loss that favors greater investment in process control.

Addressing pattern limited yield

In this work, we assess the impact of hidden error on pattern limited yield and generate unique CD and overlay-limited yield models for the 65, 45, and 32 nm nodes. We expect 193 nm immersion lithography to remain the dominant patterning technology at the 32 nm node (Figure 1). Even at the 130 nm node, the interaction of more complex designs with shrinking process windows was already evident. In memory manufacturing, for example, ramp delays of several months were common, leading to revenue losses in the tens of millions of dollars per product and reduction of ROI for 300 mm factories. Ramp delays occur primarily for two reasons: lengthy process optimization for smaller yield windows and increased time allocated for more complex intra-ďŹ eld corrections (e.g., re-design and re-layout). We and the semiconductor industry are Fall 2005

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attacking this problem using DFM and APC strategies. Although the exact definitions of DFM and APC vary significantly with manufacturing context, the goals are clear. The primary goal of DFM is to enlarge the process yield window, and the primary goal of APC is to keep the process in that yield window.

A simplified scheme for conjoint DFM and APC strategies is shown in Figure 2. Implementing the DFM strategy requires feeding forward design intent, simulator output, layout clips, and design-rulecheck (DRC) hot spots. Current DRC and aerial image modeling at best focus and exposure conditions is increasingly unreliable. Process-window-aware approaches will require powerful full-chip simulators that can accurately predict and measure developed patterns in resist, along with a super-computing environment that can produce results in an acceptable timeframe. On the process control side, implementing an APC strategy requires feeding forward process context data and prior-step measurement data. In the future, both context and measurement data must increase. In particular, measurement sample plans will increase dramatically to support multi-variate control at the lot, wafer, field, die, and intra-die levels.

Note that process metrology is at the center of a conjoint DFM and APC strategy. For example, yield window improvements depend on accurate feedback of CD and overlay variation to set design margins.

Full-chip simulators require resist model calibration, and yield prediction depends on correlation with metrology, inspection, and electrical test data. Likewise, control improvements also depend on accurate feedback of measurement 16

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data to update control models, to correctly analyze CD and overlay variation, to adjust process tool settings, and to establish correlations to device performance and yield with high levels of confidence.

Systematic design-to-process yield loss is mostly pattern limited and is a grand challenge for semiconductor manufacturing at the 65 nm node and beyond. The root-cause is the yield gap originating from

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using numerical apertures ranging from 1.3 to 1.5. A daunting array of CD, overlay, and systematic defect challenges will require conjoint DFM and APC strategies to enable yield.

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Figure 2. Process metrology is at the center of a conjoint DFM and APC strategy. Both DFM and APC depend on feedback of accurate measurement data and on removing hidden process error.

Yield Management Solutions

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Figure 3. Rapidly shrinking process windows have created a pattern-limited yield

Figure 4. Going forward, systematic error will be the primary cause of yield

crisis in early production since the 130 nm technology node. Ramp delays can

loss in early production. Innovative conjoint DFM and APC strategies must be

last several months and cost tens of millions of dollars.

employed to close the design-to-process yield gap at 65 nm and beyond.

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Figure 5. Overlay limited yield is a key contributor to yield loss for memory in

Figure 6. CD limited yield is a key contributor to yield loss for logic in early

early production. Windows are shrinking and hidden, unobservable, unsampled,

production. Windows are shrinking and hidden, unobservable, unsampled,

and unmodeled process errors are limiting yield entitlement at “zero error”.

and unmodeled process errors are limiting yield entitlement at “zero error”.

the interaction of more complex designs with shrinking lithographic process windows1. Using past trends and pinning to recent yield data, we can generate models for pattern-limited yield2, as shown in Figures 1-6. Projections of pattern limited yield to the 32 nm technology node indicate a strong need for innovation to

improve yield in early production.

The projections for mature defectlimited yield are still relatively high. An 85 percent yield entitlement for mature 140 nm DRAM production would lie directly on the curve, but the yield-dollar impact of a 3-6 month delay in early production can be tens of millions of dollars per product.

Fall 2005

Memory speed deficits and timeto-market delays impact initial average selling price and die cost, drastically reducing ROI for 300 mm factories. Specific cost and performance issues can vary significantly by product type, as shown in Figures 5 and 6 for memory and logic, respectively.

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Accurate feedback for DFM and APC

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Four types of “hidden error” are expected to limit yield in the era of immersion lithography:

The prospect of massive systematic yield losses at the 65 nm node and beyond will drive conjoint DFM and APC strategies. The success of these strategies is critically dependent on feedback of accurate metrology data and on removing the types of hidden process errors shown in Figure 7. As super-high NA immersion lithography drives CDs smaller, process windows are expected to shrink commensurately. A necessary condition for smaller design rules is the control of edge placement error (EPE). In the factory, we measure EPE as two separate components: pattern placement error (PPE) and critical dimension error (CDE). Both are affected by hidden process errors, such as lithographic dose and defocus that may or may not be measured directly4. As demonstrated in Figure 7, CD and overlay ultimately share a common error budget and constrain the designer’s intent to shrink design rules, improve performance, or increase yield entitlements.

• Unobservable error. Some systematic variations are profile-related and may not be measurable with the current generation of metrology tools. For example, traditional top-down SEM and electrical CDs miss yield-relevant footing and notching at the bottom of gate structures; these excursions are measurable using spectroscopic ellipsometry-based CD systems (SCD). CD SEMs also suffer from poor material contrast on shallow trench isolation (STI) stacks where the critical silicon top CD is obscured by a nitride structure; again, these excursions are measurable using SCD. On the other hand, SCD measurements are limited to grating targets and can miss yield-relevant shape excursions inside the device (e.g., an SRAM cell). In the case of overlay, large box-in-box targets may be subject to processinduced distortion or, because of their size, may not be sensitive to coma-induced, design rule PPE across the lithographic field.

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Figure 7. In-chip 65 nm failure analysis showing gate-to-contact shorting. Deprocessing revealed a total of seven different error types contributing to yield loss, including overlay error interacting with CD dilation, profile excursion, and roughness error on the gate layer and CD dilation, profile excursion, and roughness error on the contact layer. Most types were classified as hidden error.

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Yield Management Solutions

• Unsampled error. Assuming the CDE is measurable, sparse sample plans may still fail to capture actual statistical distributions. If the mean of the sample distribution is shifted, aliased inputs will defeat APC systems and result in costly yield loss, leaving insufficient historical data for robust rootcause analysis. As an example, traditional atomic force microscopes (AFMs) often miss STI profile excursions because sample plans are throughput limited; this is typically not the case for SCD. Insufficient sampling increases alpha and beta risk during ADI and ACI dispositioning, resulting in unnecessary rework, scrap, or yield loss. In the case of overlay, die-level PPE sampling using small targets may be required to support higherorder intra-field models. For nascent super-high NA immersion technologies that use directional liquid injection, it may be appropriate to revisit boustrophedonic sampling plans that separate the effects of stage and scan direction.

• Unmodeled error. Simple run-torun control models are no longer adequate for the 65 nm node and beyond. Model-based APC must take into account CD variation at the lot, wafer, field, and die levels.

As much as 80 percent of measured CDE in lithography results from changes in effective focus or exposure, and most of this is now intra-wafer variation. Underlying root causes are a combination of reticle, lens, scan, stage, track, and etch variation. For immersion lithography, formerly small interaction effects will become more important. Focus and exposure, profile and overlay, wafer and field, and litho and etch interaction effects should be modeled simultaneously.

For nascent super-high NA immersion tech-

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nologies, control of edge-die focus and exposure may be critical, and models should anticipate and enable shot-level correction.

• Uncorrectable error. Even if CDE is accurately modeled with low systematic residuals, it may not be correctable in the factory and must be treated as a DFM issue.

For example, CDE on the reticle could require a new mask or costly redesign. In other cases, process adjustments that could compensate for CDE are simply not accessible. Most stepper suppliers allow shot-to-shot dose and focus correction across the wafer, but few support field-dependent pistonand-tilt corrections that could minimize total intra-wafer variation. In the case of overlay, higherorder scanner errors may be observed, sampled, and modeled; but, again, no means of correction may exist inside the factory. In such cases, the burden of correction shifts to DFM. In the following sections, we discuss four technologies that were created to minimize hidden systematic error and to provide more accurate and comprehensive feedback for conjoint DFM and APC strategies.

Accurate grating-based overlay metrology

Accuracy of overlay measurement may be compromised by process-induced distortion of traditional box-in-box overlay targets. Errors fed back into APC systems drive incorrect scanner adjustments that can take a process out of its yield window. Likewise, erroneous data fed back into DFM strategies drives incorrect margin setting that can result in smaller yield windows. Replacing box-in-box targets with grating-based (AIM) targets greatly increases robustness to process variation5, as shown in Figure 8.

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Figure 8. Overlay measurement accuracy may be compromised by process-induced distortion of traditional boxin-box overlay targets. Replacing box-in-box targets with grating-based (AIM) targets, shown above, can increase target robustness, APC performance, and device yield.

The most critical layer pairs are usually active-to-gate, gate-to-contact, and contact-to-metal. Active-to-gate misregistration, specifically with respect to the line-end, can result in gate leakage or reduced static noise margin. Gate-to-contact misregistration, particularly in conjunction with CD, profile, or roughness error, can result in shorts and functional failure.

Contact-to-metal misregistration quite often results in resistive or open interconnects. As the number of metal layers increases, the probability of a metal-to-via overlay failure also increases, particularly for layers patterned with aggressive pitch.

In addition to process-induced error such as that created by CMP or asymmetric metal deposition, there may be higher-order intra-field error from the reticle and scanner than can account for as much as 50 percent of the overlay model residuals. The effectiveness of APC is reduced in such cases, and DFM strategies must be used to increase the yield window. At least two strategies for target design Fall 2005

are being tested. First, with a small sacrifice in performance, Archer AIM targets may be shrunk to about 10 µm on a side to enable in-chip overlay metrology. Second, if lithographic lens aberrations such as coma are significant, design-rule structures may be incorporated in the bars of the grating target so that featuresize effects are faithfully replicated.

Back-end designers should note that, to support conjoint APC and DFM strategies, these targets must be subject to the same resolution enhancement technique (RET) treatments used to enhance printability in the chip. The PROLITH™ simulator can be a useful tool in such applications.

Accurate ellipsometrybased profile metrology

Pattern noise in CD-SEM measurements can compromise performance of front-end-of-line (FEOL) APC loops, resulting in lower yield and performance entitlements. Replacing SEMs with spectroscopic ellipsometry-based CD systems, as shown

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Accurate SEM-based roughness/array metrology

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CD-SEMs can uniquely characterize and monitor line-width roughness (LWR) and line edge roughness (LER) for DFM applications that address the insertion of immersion lithography into volume production7.

For immersion lithography, LWR varies significantly with resist and top coat characteristics. In fact, if current levels of LWR are not reduced, device yield will trend to zero at the 32 nm technology node. The use of top coats in immersion lithography adds another opportunity for systematic process error. In particular, we have found that LWR is a strong function of cross-wafer, top coat uniformity. The CD-SEM (eCD-1) used for the study is capable of generating online LWR analysis, as shown in Figure 10. A controlled overdose experiment revealed no significant change in the LWR measurement after 100 images had been acquired.

The LER, however, was visibly reduced.

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Yield Management Solutions

DFM strategies. Because of its high precision and accuracy, SCD can also be used as a calibration tool for the PROLITH simulator.

Due to the challenges of creating robust SCD models for back-endof-line (BEOL) metrology, CDSEMs are likely to be the main APC enablers for some time. Two key problems compromising accurate and robust APC performance have been solved uniquely on eCD-2 Class SEMs. First, line/space identification error in older-generation CD-SEM measurements has been decreasing yield and increasing rework in the BEOL applications. Recently, we have verified that electrostatic beam tilt can provide robust identification8 in less than 900 ms without the hysteresis effects

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Figure 10. CD-SEMs can characterize and monitor LWR and LER for DFM applications. Line-width roughness varies by resist type and top coat uniformity, but not by electron dose. If current levels of LWR are not reduced, device yield will trend to zero at the 32 nm technology node.

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and long delays associated with electromagnetic deflection (Figure 11).

Second, the development of arraymode metrology for BEOL applications can greatly reduce the contribution of pattern noise to error in APC adjustments. The CD-SEM measures several lines within its image field and reports mean and standard deviation statistics. These same statistics are now a reliable means for setting design margins in DFM strategies. Combined with beam tilt, array-mode measurements can be virtually flier-free, even when the SEM image field is located deep inside an array of lines and spaces.

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Figure 11. Incorrect line/space identification in CD-SEM measurements can affect APC performance, yield, and

Accurate simulation-based DFM optimization

Accurate printability simulation is essential for DFM. The PROLITH simulator can have up to a ten-fold accuracy advantage relative to other simulators and can be calibrated for DFM using either array-mode CD-SEM or SCD metrology.

Two unbiased metrics for accuracy are the Kintner Image Intensity Test and the Steele Image Placement Test, some results of which are shown in Figure 12.

High levels of accuracy are critical to the generation of multiple simulated measurements used to create overlapping focus-exposure windows.

Such process windows enable backend designers to modify layouts for maximum process robustness, device performance, and functional yield. For DFM applications, the natural extension of this technology is the application of reticle and wafer simulation to the inspection of integrated circuit databases in a supercomputing environment9.

rework in the BEOL. Electrostatic beam tilt provides robust identification, enabling array metrology and the strong spatial averaging required for BEOL APC applications.

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Figure 12. Accurate printability simulation is essential for DFM. As shown above, the PROLITH simulator has up to a ten-fold accuracy advantage and can be calibrated using CD-SEM or SCD metrology. Multiple simulated measurements are used to create overlapping process windows that enable designers to modify layouts for maximum process robustness, device performance, and functional yield.

Conclusions and recommendations

In this work, we have shown how design margins and process control performance can be reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmodeled, and uncorrectable components.

We have applied four new process control technologies to reduce hidden systematic process error. These technologies can provide accurate feedback of process metrics to enable conjoint DFM and APC strategies at

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the 65 nm node and beyond. We contend that manufacturing economic considerations will force a trade-off between measurement cost and yield loss that favors greater expenditure on process control, particularly on those technologies that enable APC and DFM. In summary, we have introduced the following concepts: • A concept of 193 nm immersion lithography extending through the 32 nm technology node,

Yield Management Solutions

• A concept of conjoint DFM and APC strategies that would rely on accurate feedback of process metrics to enable larger process yield windows and better centering of the process within those yield windows, • A concept of predictive yield models for CD and overlay control that can be pinned to actual factory data and can include the yield limiting effects of hidden systematic error, • A concept for parsing hidden systematic error into unobservable,

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unsampled, unmodeled, and uncorrectable components, • And, finally, a concept for development of technologies such as grating-based overlay, ellipsometry-based profile metrology, array-based CD SEM metrology, and calibrated simulators to provide accurate process metrics for 65 nm technology and beyond.

Acknowledgements

The authors would like to thank Chris Mack, David Tien, Amir Azordegan, Chris Sallee, and Matt Hankinson, all of KLA-Tencor Corporation, for valuable discussion.

References 1. K. Monahan, “Microeconomics of Process Control in Semiconductor Manufacturing”, Proc. of SPIE, Vol. 5043, pp. 57-71, February 2003.

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2. K. Monahan, “Microeconomics of Yield Learning in Semiconductor Manufacturing”, Proc. of SPIE, Vol. 5043, pp. 41-56, February 2003.

3. K. Monahan, “Chairman’s Introduction to the ISSM 2003 Cost and Performance Workshop”, ISSM 2003, September 29, San Jose, California.

4. K. Monahan, “Microeconomics of Process Control in Semiconductor Manufacturing,” Proc. of SPIE, Vol. 5043, pp. 57-71, February 2003.

5. L. Lecarpentier, V. Vachellerie, A. Feneyrou, P. Thony, S. Guillot, E. Kassel, Y. Avrahamov, C. Huang, F. Felten, M. Polli, “Overlay Measurement Accuracy Verification using CDSEM and Application to the Quantification of WIS Cause by BARC”, Proc. of SPIE, Vol. 5257-172, March, 2005.

6. W. Lin, S. Liao, R. Tsai, M. Yeh, C. Hsieh, C. Yu, B. S. Lin, T. Dziura,

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“Feasibility of Improving CDSEMbased APC System for Exposure Tools

by Spectroscopic Ellipsometry-based APC System”, Proc. of SPIE, Vol. 5755-17, March 2005.

7. P. Leunissen, G. Lorusso, T. Dibiase, “Full Spectral Analysis of Line-edge Roughness“, Proc. of SPIE, Vol. 575249, March, 2005.

8. E. Solecky, C. Chin, G. Qu, H. Yang, A. Azordegan, “Automated CD SEM Tilt: Ready for Prime Time, a Fast In-line Methodology for Differentiating Lines and Spaces Using Tilted Images for Process Control”, Proc. of SPIE, Vol. 5752-73, March, 2005.

9. J. Tirapu-Azpiroz, J. Culp, S. Mansfield, W. Howard, Y. Xiong, C. Mack, R. Shi, G. Verma, W. Volk, H. Lehon, Y. Deng, “Inspection of Integrated Circuit Databases through Reticle and Wafer Simulation: an Integrated Approach to Design for Manufacturability”, Proc. of SPIE, Vol. 5756-07, March, 2005.

This article is based on a paper that was previously published in the SPIE Proceedings 5756-7.

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From One Side to Another How Backside Defects Can Wreak Havoc on IC Features Laura Pressley, Ph.D., Shirley Hardin, Jeremy Bolf, Travis Kirsch, John Darilek, Mike Allen, Brian Dunham, Buster Klingemann, Teresa Mathews, Carolyn Cariss, Eric Apelgren, Dan Sutton, Kevin Harper, Laurence Kohler, Ph.D., Chris Lansford, Terri Couteau, Bryon Hance, Fab 25, Spansion LLC Rhonda Stanley, Joyce Witowski, Lisa Cheung, KLA-Tencor Corporation

This article examines the impact that backside defects can have on the frontside of wafers and, ultimately, on device performance. For example, in this study, a detailed front-end-of-line (FEOL) frontside and backside defect partition showed that several defect mechanisms were operating in the FEOL, and identified a previously unknown backside defect mechanism that was affecting every incoming silicon wafer from several silicon substrate suppliers. An evaluation of backside defect data enabled the silicon suppliers to identify the root cause.

Introduction

A key challenge for semiconductor devices patterned at 110, 90, 65 nm and below are backside defect transfer mechanisms that occur in batch processing equipment in which the frontside, device performance portion of the wafer is directly exposed to the backside of wafers during processing.

Several studies of backside defectivity have been previously reported in the literature.1-10 The majority of processing equipment for IC devices utilizes single wafer processing for etch, photolithography, CVD, PECVD, and polish operations. Yet, diffusion and wet clean processes are typically performed in batches and are susceptible to defect transfer between wafers during processing. Several IC equipment suppliers have anticipated these defect transfer-related issues and have developed new methods to minimize these transfer mechanisms. For example, several IC wet clean equipment suppliers have developed immersion tools that orient wafers with the frontsides facing each other (face-to-face processing), which allows the

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wafer backsides to not be directly exposed to the IC features. Going one step further, single wafer wet clean sinks have also been developed in recent years, and single wafer cleans are progressively being introduced in the FEOL cleans by various IC manufacturers.

In FEOL diffusion furnace processes, wafers are typically positioned in parallel above each other with the frontsides of wafers underneath the less characterized and typically more defective backsides of wafers. This type of diffusion furnace batch processing is susceptible to backside defects and the incidence of film flaking onto the frontside of the wafers positioned below. These mechanisms may be the result of film stress, thermal expansion/contraction, and/or lattice mismatch issues that occur during diffusion processing. Therefore, it is important to understand and characterize the backside defectivity in the FEOL batch processes to determine if these processes contribute to die yield losses. In this paper, FEOL diffusion backside defectivity characterization methods are discussed, including the chemical identification of these defects, the correlation of various backside defect signatures to a root cause, the transfer to the frontside of wafers during FEOL diffusion processes, and the possible impact to device sort yields.

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Experimental methods

Several sets of Flash memory production lots and bare Si test wafers were utilized in this study. To minimize background noise levels for defect detection, we used Si substrate material with low levels of crystal oriented pits (COPs) and double sided polished (DSP) Si for increased defect sensitivity for backside defects. Frontside and backside defects were characterized with various surface analytical techniques such as scanning electron microscopy (SEM) and energy-dispersive X-ray fluorescence analysis (EDX) using Applied Materials’ SEMVision and the JEOL SEM. The equipment for backside defect metrology included KLA-Tencor SP1-BSIM and the Applied Materials SEMVision.

The Applied Materials Compass and SEMVision and the KLA-Tencor AIT tools were utilized for frontside defect quantifications.

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This systematic, step-wise correlation from end-of-line sort yield back to frontside inline defectivity data shows that the same defect type found at end-of-line strip back was previously detected inline at several locations such as Poly 2 and the origin of the defect source is the Poly 1 module. Extensive defect partitions and investigations proved the majority of these embedded defect types were first detected in the Poly 1 process module.

For the various processes and equipment tool sets that comprised the Poly 1 module, we collected frontside overlay defect maps for test wafers used for the various defect qualifications and found a similar spatial defect signature as in Figure 1 above. As Figure 2 shows, the overlay defect maps for the bare Si test wafers (particle qualification tests) for furnace film (Y) had the best spatial match to Figure 1 (c). The overlay defect maps from other furnace films used in the Poly 1 area of the line did not show a strong spatial correlation. Therefore, ��� that furnace film ��� (Y) was the major ��� defect we suspected contributor causing the die yield edge loss.

Correlating Yield Losses to FEOL Furnaces

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Figure 1. Overlay of wafer maps showing the correlation of edge die losses with frontside inline defect spatial signature and SEM of those defects at a) end-of-line die yield, b) frontside inline defect maps of FEOL at 2nd Poly Gate, and c) frontside inline defect maps of FEOL at 1st Poly Gate.

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Figure 2. Frontside defect overlay wafer maps of bare Si test wafers for furnace defect qualifications showing the inline spatial signature for furnace film (X), (Y), and (Z), respectively.

A scatter plot of the frontside inline production wafer defect levels vs. the furnace process (Y) test wafer qualification defect values showed a strong correlation for furnace test wafers that are placed under production material ��� in a furnace load (see Figure 3). There was no ��� ��� correlation of inline defectivity with the defect levels of bare Si test wafers placed under other bare Si test wafers. The strongest defect correlation existed for bare Si test wafers that were placed under standard, full flow production wafers. Therefore, a backside transfer ��� mechanism was possibly operating and causing the edge defectivity and subsequent die yield losses. ����������������������������� ��

Improving IC wafer edge die yield is a key focus for all manufacturing facilities. Characterization of process signatures and defect types that are responsible for yield losses on the edges of wafers is important in determining the major contributors. Correlating the yield and end-of-line loss signatures with inline defect data and defect types is key in identifying the exact processes causing the yield losses. Figure 1 below is an example of such a correlation. An overlay of numerous end-of-line die yield maps and end-of-line stripback data allowed us to identify similar FEOL inline defect spatial signatures and types, as well as their origins.

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Figure 5. Schematic diagram of a vertical diffusion furnace with frontside and

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backside wafer maps showing examples of backside defects that have translated

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Figure 4. Wafer spatial correlation of (a) die yield losses at end-of-line, with (b) frontside inline production defect measurements post diffusion processing, and (c) furnace tool qualification frontside defect data.

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Testing Backside Defect Transfer Mechanism Theory for Furnace Film (Y)

It has been previously shown that backside defect transfer mechanisms can operate in vertical diffusion processes.

Below is a schematic diagram showing the loading sequence and backside defect transfer that can occur in a vertical��� diffusion furnace [from a 200 mm microprocessor fab and KLA-Tencor case study].

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a similar spatial defect pattern onto the frontsides of wafers positioned below them.

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To show a backside defect transfer mechanism occurring during the deposition of furnace film (Y), we evaluated and quantified the frontside defectivity of test wafers oriented below a) new bare Si test wafers, vs b) full flow���production material in the Poly 1 module for the furnace film (Y). As shown in Figure 6, for the bare test wafers placed under other bare Si test wafers, the frontside defect levels were significantly lower than those bare Si test � wafers that were oriented below the standard full ������������� ������������������ flow production wafers processed for furnace film ��������� (Y). In ����������� ���������� addition, the defect overlay wafer maps showed that ���� the bare Si test wafers under the production material had a predominant edge signature similar to Figure 4.

Frontside overlay defect maps for each group of wafers in Figure 6a (under bare test wafers) and 6b (under full flow production wafers) show the respective frontside defect spatial signature for each test. To further prove that a backside defect transfer mechanism was operating during the processing of furnace film ��� ���(Y), we also evaluated and quantified the frontside defectivity of full flow production wafers oriented below Figure 6a (bare Si test wafers) vs. Figure 6b (full flow production material for the furnace film (Y)).

As��� shown in Figure 7, for the test wafers placed under other test wafers, the defect levels were significantly lower than the test wafers that were oriented below the standard full flow production wafers processed with furnace ���film (Y). In addition, the frontside defect overlay

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Based on the data above, we have shown that using endof-line wafer spatial yield loss patterns in conjunction with inline production and tool qualification frontside ��� is an effective method ��� ��� specific defect data for identifying process operations contributing to the yield losses. This is shown in Figure 4.

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wafer maps showed the production wafers inserted under the production material had the edge signature similar to Figure 4 above and those under bare Si test wafers did not show the predominant edge signature.

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Figure 6. Normalized overlay wafer maps for bare Si ��� frontside defect levels and��� test wafers (FMs) placed under (a) bare Si test wafers (FMs), and for bare Si test wafers placed under (b) full flow production wafers for furnace film (Y).

Production wafers under production wafers show an edge-centric defect signature similar to the bare Si test wafer signature under full flow production wafers in Figure 6 and similar to the frontside defect signature in Figure 4. Furthermore, the spatial signatures are similar to the edge yield loss patterns of Figure 1a, 1b, and 1c.

Partitioning Defects on the Backside of Production Wafers

Using the KLA-Tencor SP1-BSIM tool, we characterized the defect signatures of the backside of production wafers incoming to and after deposition of furnace film (Y). Note, no comparison of other backside scan tools were made in this study. To enhance the signal-to-noise for the backside scans, we utilized double sided polished (DSP) Si starting material for characterizations of backside defects. Figure 8 below shows backside defect levels pre-FEOL processing, as well as the same wafer post FEOL post-processing up to and including STI, implants, and the Poly 1 module and deposition of furnace film (Y).

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Figure 8. KLA-Tencor SP1-BSIM backside scan of a double sided polished wafer (a) before FEOL processing and the same wafer (b) after processing in the FEOL up to and including the furnace film (Y) processing.

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Figure 7. Normalized JMP graph for frontside defect levels and representative frontside wafer maps for full flow production wafers placed under (a) bare Si test wafers and under (b) full flow wafers during the deposition of furnace film (Y).

Note the three-fold clustered, dense set of defects around the edge of the backside wafer map in Figure 8a.

This three-fold symmetry pattern remains ����� ������ after multiple FEOL processing steps and modules in the FEOL. Also, numerous backside defect signatures are apparent on the wafer map in Figure 8b. The interesting defects from an edge yield perspective are the backside defects located around the perimeter of the wafer in Figure 8b.

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mechanisms to prevent backside defect transfers in various batch process tools such as clean sinks and vertical diffusion furnaces. Several of the defect signatures we observed on the wafer map in Figure 8b are understood as having ongoing FEOL defect reduction projects.

Yet, the three-fold symmetry pattern detected on the starting Si wafer map in Figure 8a was a new defect mechanism, of which we had previously been unaware.

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Therefore, we partitioned the FEOL for the source of these large defects. SEM inspection of the three-fold backside edge defects post Poly 1 furnace processing shows multiple, greater than 100 µm in length scratching patterns. Representative SEMs of the scratch defects ��� ��� are shown in Figure 9 below.

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Figure 10. KLA-Tencor SP1-BSIM backside scan and SEM images of the backside roughness and scratches of production wafers prior to processing. Supplier (a) did not have the three-fold scratches, whereas (b) and (c) both showed the ������ three-fold symmetry ��� scratch defects.

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Figure 9. Representative backside SEM images taken of the three-fold symmetry gouge/scratch defects on a production wafer.

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We partitioned these three-fold defects at 10 sequential locations in the FEOL from the furnace film (Y) process, in the Poly 1 module, back to the beginning of processing in the FEOL. We found that these scratches occurred prior to processing in our IC manufacturing facility.

Using the KLA-Tencor SP1-BSIM tool, we inspected��� and characterized the backsides of wafers from each of our silicon suppliers. The inspection revealed that two Si vendors were producing these severe scratch defects ������to our fab. Figure 10 on every Si wafer they supplied ��� ��� shows the three-fold defect spatial signature of���these gouges and low-resolution backside SEM images of wafers from multiple Si vendors. SEM and EDX elemental characterization of the scratch defects were performed and some defects were found embedded in the scratched locations. These were comprised of Si and C as shown in Figure 11.

Figure 12 shows a backside ���� defect wafer map overlay of 25 wafers of a lot prior to processing. It indicates random rotational orientations of the three-fold symmetry patterns on the wafers. Please disregard the wafer handling patterns in the center of the overlay wafer map. ��� 28

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Figure 11. EDX spectra of backside embedded defects in the three-fold scratch patterns on production wafers.

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Figure 12. Backside defect wafer overlay map of 25 wafers prior to FEOL processing. We relayed the new defect information to our various Si suppliers and, based on the data, the backside three-fold symmetry pattern matched exactly with a marginal furnace anneal and SiC boat configuration being used in the preparation of the Si wafers. The SiC EDX spectra identified the supplier boat material causing the scratches; the three-fold spatial locations matched the supplier’s furnace boat rail orientations, and the random rotation of the three-fold symmetry scratches matched up with the fact that the suppliers were not notch aligning prior to the marginal furnace anneal process.

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Degradation of Backside Scratch Defects During FEOL Processing

Figure 13 shows the effects that FEOL processing, in high temperature diffusion pre cleans and furnace processes in the poly 1 loop, can have on scratch type defects that originate on the backside of Si wafers at lot start. As shown in the SEM images, subsequent FEOL processing ��������� and temperature cycles can degrade the defect locations and cause scratch defects to crack, propagate, and produce particles that may be transferred to the wafer frontside in batch type ������ processes or even cause ��������������� subsequent photolithography patterning issues.

These SEM images were collected on separate wafers that had received a BSIM pre-scan at lot ����� start. To collect the data, we re-reviewed the same ����� ������������������� scratch defects after various diffusion clean/furnace processing in the poly 1 loop. Because a non-destructive review tool or methodology to collect ����� true defect propagation data on the same wafers ���� after multiple processing ����������������� steps does not exist, we flipped each wafer upside down on the SEM tool and removed them from subsequent processing ���� because the patterned side of the wafers were severely damaged by the ���� ����������������� SEM chucks.

Figure 13. Backside SEM images of

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scratch defect degradation due to FEOL diffusion pre clean and furnace processing.

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Conclusions and future actions

Detailed FEOL characterizations revealed a previously unknown, Si supplier-generated backside defect mechanism. According to the various suppliers, no other IC manufacturer had brought this to their attention.

Subsequently, each supplier now has corrective actions in place to reduce and eliminate these backside scratches and defects. Based on the data from this study, our manufacturing facility plans to monitor backside defectivity levels for starting Si material due to the defect transfer effects these large, gouge/scratch type defects can have in our various single wafer and batch processes.

As IC manufacturers progress into 110, 90, and 65 nm technology nodes, large backside defects will cause lithography edge focus marginalities; polish, etch, and film chucking; and edge process uniformity issues.

Our plan is to continuously monitor these backside defects on incoming Si production material nondestructively with our backside scan tool. For future backside defect characterizations, a non-destructive method of SEM review of backside defects is a critical requirement. It is essential to be able to collect nondestructive, in-situ SEM and EDX characterizations for backside defects and contamination so that root causes can be identified inline and corrective actions can be quickly implemented to reduce defectivity and increase semiconductor die yields.

Acknowledgements

The authors would like to thank the Spansion Fab25 CFM organization and Mike Brooks, Director of Yield Management, of Spansion, LLC for supporting these extensive characterizations.

References 1. F. Kroninger, N. Streckfuss, L. Frey, T. Falter, C. Ryzlewicz, L. Pfitzner, and H. Ryssel, “Application of advanced contamination analysis for qualification of wafer handling systems and chucks,” Appl. Surface Sci., vol. 63, no.

1-4, pp. 93-8, January 1993.

2. R. Miura, H. Ishigaki, and Y Matsunaga, “Backside particle reduction on PI9500 series ion implanter,” in Proc. of the Eleventh Int. Conf. on Ion Implantation Tech., June 1996, pp. 174-7.

3. F. Beaudoin, M. Meunier, M. Simard-Normandin, and D. Landheer, “Excimer laser cleaning of Si wafer backside metallic particles,” J. Vac. Sci. Technol. A, vol. 16, no. 3, pp 1976-9, May-June 1998.

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4. W. Frutiger, R. Eddy, D.A. Brown, and M.E. Mack, Production proven electrostatic platen for medium current implantation,” in Proc. of the Eleventh Int. Conf. on Ion Implantation Tech., June 1996, pp. 346-9.

8. Kay Lederer, Matthias Sholze, Ulrich Strohback, Andreas Wocko, Thomas Reuter, Angela Schoenauer, “Wafer Backside Inspection Applications in Lithography,” Advanced Semiconductor Manufacturing 2003 IEEE Conference Workshop, 31 Mar – 1 Apr, 2003, p. 1-8.

5. Krishnamachar Prasad, “Optoelectronic and Microelctronic Materials and Devices”, 2000 COMMAD Proceedings Conference, 6-8 Dec 2000, p. 25-28.

9. Christopher Maleville, Lisa Cheung, Dieter Mueller, “Fabricating and Inspecting Ultathin Silicon-On-Insulator Wafers”, Micro Magazine.com, 1997.

6. Lesley A Cheema, Leonard J. Olmer, Oliver D. Patterson, Susan S. Lopez, Mark B. Burns, “Wafer Backside Inspection Applications for Yield Protections and Enhancement”, Advanced Semiconductor Manufacturing 2004 IEEE Conference Workshop, 30 Apr – 2 May, 2004.

10. Kazuyuki Hozawa, Hiroshi Muyazaki, Jiro Yagami, “True Influence of Wafer-Backside Copper Contamination During the Back-End Process of Device Characteristics,” Electron Devices Meeting, 2002, IEDM ’02 Digest International 8-11 Dec, 2002.

7. Patrick Taylor, Thuy Pham, Charley Wang, “Applications for Automated Wafer Backside Inspection,” Advanced Semiconductor Manufacturing 2004 IEEE Conference Workshop, 4-6 May, 2004.

This article is based on a paper that was originally presented at ASMC 2005.

Yield Management Seminar A valuable venue for innovative ideas

KLA-Tencor’s Yield Management Seminars (YMS) focus on the latest solutions and strategies for accelerating yield through critical technology transitions. Participants have the unique opportunity to learn and gather information from several leading experts in the field.

Key topics include achieving high-yield copper interconnects, and solutions to control lithography process windows and gate dielectrics.

To register online for the upcoming YMS, please visit us at: http://www.kla-tencor.com/seminar Date: Monday, October 3, 2005 Time: 11:30 am – 5:30 pm Location: Monterey, California

Call for future papers

Papers should focus on using KLA-Tencor tools and solutions to enhance yield through increased productivity and performance. If you are interested in presenting a paper at one of our upcoming yield management seminars, please submit a one-page abstract to: Cathy Silva by fax at (408) 875-4144 or email at cathy.silva@kla-tencor.com.

YMS at a Glance

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BROADENING the s e n s i t i v i t y zone 2800 Tackles Pattern-Limited Yield, CMOS Power Crisis At 65 nm and below, chipmakers face unique challenges that, left unresolved, could prove detrimental to yield. On the one hand, shrinking process tolerances and the widening sub-wavelength gap are creating a pattern-limited yield crisis. This has given rise to systematic defects, primarily in the photolithography module, that are extremely difficult to detect and resolve. At the same time, the CMOS power crisis has generated a wide variety of new defect types and new noise sources, as manufacturers innovate with new materials, device structures, and litho techniques.

These new challenges require highly flexible inspection tools with the broadest spectrum of sensitivity to find all defects in all layers. To this end, KLA-Tencor offers the 2800, a single, flexible brightfield inspection platform with UV and DUV wavelengths, designed to enable the widest capture of yield-relevant defects.

Production-worthy for shrinking design rules Designed for inspection of critical patterning layers, the 2800 represents KLA-Tencor’s next-generation DUV/UV/ visible patterned wafer inspection system.

The system meets the resolution and throughput needs for production and development nodes for logic and memory devices. Its production-worthy advantages include a high numerical aperture (NA) for all illumination modes, configurability for unique applications, defect binning capabilities, and 2X better throughput than the previous-generation DUV inspection tool.

The 2800 enables fabs to achieve fast time to results in detecting the smallest of yield-impacting defects, particularly on litho and etch layers. Its broadband capability suppresses color noise and allows tuning of signals to isolate defects of interest. In addition, the 2800 brings

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Compared with single wavelength technology, broadband illumination enables detection of the full range of critical defects.

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Developed with KLA-Tencor’s longstanding technical expertise in broadband brightfield technologies, the 2800 platform is extendible to support capacity expansion and design rule shrinks. further advantages when implemented with unique brightfield applications such as Process Window Qualification (PWQ) and Photo Cell Monitoring (PCM). PWQ enables fabs to efficiently evaluate and, if necessary, adjust reticle designs. PCM facilitates faster, more cost-effective identification of root cause of litho defects.

Part of a comprehensive inspection strategy Sharing a common user interface and recipe components with the Puma 9000 next-generation darkfield inspection tool and the eS3X electron-beam inspection tool, the 2800 is part of a comprehensive patterned wafer inspection portfolio. These commonalities enhance ease of use, lowering the training burden and associated costs; provide fabs with a brightfield baseline of traditional darkfield layers; and facilitate migration of the inspection process from development to ramp to production. With the 2800, KLA-Tencor continues its leadership in brightfield technology, enabling fabs to meet the increasingly complex challenges of design rule shrinks.

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Pushing Scientific Boundaries

Mehdi Vaez-Iravani Named First KT Fellow

Scientific study is in Mehdi Vaez-Iravani’s blood. Growing up in Iran, Vaez-Iravani observed and followed suit as his three older siblings excelled at mathematics, something of a tradition in the family. “Like all young kids, I was curious about things. In particular, I always had an interest in mathematical reasoning — tr ying to get to the essence of things.”

Today, Vaez-Iravani is still striving to get to the essence of things, applying his technical expertise as vice president of technology for KLA-Tencor’s Wafer Inspection Group (WIG). In recognition of his efforts in developing innovative technologies that help customers accelerate their yield, Vaez-Iravani has been named the first KT Fellow.

ways to inspect wafer backsides for the Surfscan Division.

While exploring oblique laser illumination angles and long, narrow line scans for backside inspection, the team found a way to apply these techniques to patterned wafer inspection.

And, thus, the breakthrough Streak technology was born.

“As a KT Fellow, my role will include helping to ensure that with every technology we pursue, we are operating at the pinnacle. I will also be available to help new engineers develop their careers here,” he explains. The responsibilities of the KT Fellow will continue to be defined. At any given time, there will be three or four KLA-Tencor technologists in this role.

Vaez-Iravani’s path to KLA-Tencor was paved in high school, where students challenged each other to push the boundaries in math, physics, and chemistry. He recalls, “It was an environment where your best friends were also your biggest rivals, and you needed extra books—beyond the required texts—to get through the exams.”

A Founder of Revolutionary Streak™ Technology

The fruits of one of Vaez-Iravani’s most recent engineering successes can be found in the new Puma™ 9000 wafer inspection tool, which is designed to deliver high sensitivity at optimal throughput. This core capability is enabled by Streak technology, which combines high-resolution imaging with advanced ultraviolet (UV) illumination optics.

Vaez-Iravani collaborated with technologists Guoheng Zhao and Stan Stokowski to develop Streak technology. At the time, the team was also examining efficient, effective

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Solving Real-world Problems

While high school classes were primarily theoretical in nature, college courses at the University College London in England allowed Vaez-Iravani to apply the concepts he had explored.

He experimented in optics, photo-acoustics, and laser-based microscopy. After earning his Ph.D. in electrical engineering, Vaez-Iravani became a researcher at Royal Philips Electronics Laboratories in New York and, later, a faculty member at the Rochester Institute of Technology’s Center for Imaging Science. There, he taught students about high-resolution near-field optical microscopy, atomic force microscopes, and optical, acoustic, and photo-thermal photo-acoustic beam propagation.

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“I love translating theory into actual experiments,” he says. “Early on, I was drawn to optics because of all of the possibilities of the laser. I was fascinated by how you could play modulation tricks with it to extract signals from a noisy background. It’s fun.”

In 1995, he joined Tencor Instruments, which merged with KLA in 1997 to become KLA-Tencor. Over the years, Vaez-Iravani has had the opportunity to mentor some of the company’s brightest engineers. “Young engineers have good ideas, but sometimes they need someone to be a sounding board, to help them develop those ideas into something practical,” he notes.

That’s a very familiar concept to Vaez-Iravani. His career at KLA-Tencor has been all about developing practical products that help customers solve difficult problems. His current effort addresses the price vs. performance trajectory.

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Taking the Right Risks to Generate Rewards Looking ahead, Vaez-Iravani believes that the chip-making industry will need to take an increasingly holistic approach to chip design, addressing such challenges as heat management as the relevance of Moore’s Law begins to wane. Technologists are pushing the limits of physics, and will need to continue incorporating new materials such as organic structures and leveraging nanotechnology to create “smart” materials. For KLA-Tencor, the future in process control tools will involve such requirements as improved algorithms, new light sources for enhanced sensitivity, and more efficient utilization of available processing power.

“I believe in taking calculated risks, but not wasting money,” he says. “We have to challenge ourselves at every step, so that what we do is always state of the art. Ultimately, good work pays off in terms of the value we can deliver to our customers.”

KLA-Tencor Trade Show Calendar September 12-14, 2005

SEMICON Taiwan, Taiwan World Trade Center

September 20-21

DISKCON USA, Santa Clara, California

September 26-28

SEMICON Expo CIS, Moscow, Russia

October 4-5

BACUS/Photomask, Monterey, California

October 6

FSA, San Jose, California

December 7-9

SEMICON Japan, Makuhari, Japan Summer 2005

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Breaking Through Barriers At < 65 nm nodes, chipmakers face the continued introduction of new processes and new materials, along with unrelenting pressure for cost-effective manufacturing. To address these industry challenges, KLA-Tencor offers the Puma 9000 family, our next-generation darkfield technology.

Designed to enable cost-optimized patterned wafer inspection, Puma 9000 provides high sensitivity at productionworthy throughput levels to enable detection of critical, yield-impacting defects on various layers. The core enabler of this tool is Streak™ technology.

Streak technology brings new life to traditional darkfield technology. Resolution in traditional darkfield technology is directly related to the illumination spot size. Shrinking design rules have forced the migration to smaller spot sizes to gain resolution; however, this puts the brakes on throughput.

In addition, traditional darkfield technology relies on a photo multiplier tube (PMT) and an acoustic optical device, which has a data rate limitation of about 300 megapixels per second. These inevitable limits in throughput and detection capacity drove an innovation in technology to extend the production-worthy line monitoring capabilities of darkfield systems. Streak technology is the unique combination of illumination orientation, collection, and a multi-pixel sensor design that allows the Puma 9000 to achieve extremely high data rates and smaller pixels sizes.

The increased resolution extends the tool’s capabilities beyond traditional laser scattering applications, supporting a mix-and-match approach with KLA-Tencor’s brightfield tools that enables higher sampling rates to protect more wafers in

Puma 9000 Offers High-Sensitivity Inspection Without Compromising Throughput progress. Its programmable Fourier filter increases sensitivity in array regions of the wafer, suppressing diffraction pattern noise. The tool also shares a common software platform and recipe components with the 23XX brightfield tools, as well as with KLA-Tencor’s eS3X family of electron-beam inspection solutions. Such commonality facilitates a cost-effective patterned wafer inspection strategy, and supports rapid integration into the production environment.

The Puma 9000 also enables: �����������

• Higher sensitivity to critical defect types with������ Streak technology

• High throughput at required sensitivity for advanced design rules ���������� ������������ �������������

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• Lower training burden and faster implementation inline due to common platform with 23XX and eS3X • Fast yield learning with real-time defect classification through integrated inline automatic defect classification (iADC) • Support for specific application needs through flexible ����� configurations • Capital extension through an extendible architecture

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KLA-Tencor’s innovative Streak technology enables the Puma 9000 to provide high sensitivity at optimal throughput. �������������������� ��������� ���������

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This series of images depicts a logic device (top) and a DRAM device (bottom) as viewed through a traditional darkfield inspection tool and the Puma 9000. Enhanced signal-to-noise and improved resolution on Puma 9000 enable better defect capture on both devices.

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Getting What You’re Entitled To A New Approach for Reducing Pattern-Dependent Yield Loss Jaione Tirapu Azpiroz , James Culp, Scott Mansfield , IBM Microelectronics William Howard, Yalin Xiong, Chris Mack, Gaurav Verma, William Volk, Harold Lehon, Yunfei Deng, Rui-fang Shi, KLA-Tencor Corporation

With the current approach to optical proximity correction (OPC) verification, OPC decoration is verified by a design rule or optical rule checker, the reticle is verified by a reticle inspection system, and the final wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with little or no data flowing between them. A new inspection system called DesignScan connects the data between the various abstraction layers. DesignScan inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window. The simulated images are compared to the desired pattern, and defect detection algorithms are applied to determine if any unacceptable variations in the pattern occurs within the nominal process window. The end result is a new paradigm in design verification, moving beyond OPC verification at the design plane to process window verification at the wafer plane, where it really matters.

Introduction

Pattern Dependent Yield Loss

In previous design nodes, yield loss was mainly driven by random effects such as defect density. Since then, systematic effects, such as pattern dependent yield loss (PDYL), have become dominant1,2. PDYL is characterized by one or more of the patterns on the device layer failing prematurely in the process window. These patterns, which are called “weak designs” or “hot spots”, are most sensitive to changes in focus and exposure and, therefore, have smaller process windows.

Since the effective process window is only as large as the intersection of all the component pattern process windows, yield loss results. This phenomenon is illustrated in Figure 1, which shows how the process window diminishes because of two such weak designs.

resolution enhancement techniques (RET) processes in the hope that this information can improve yield and prevent such weak designs. These approaches have, in fact, been very useful but not completely successful, and PDYL is still problematic3. ����

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Figure 1. The entitlement process window (depicted as a solid ellipse) is that which is expected based on the process capability. When “weak patterns” or ������ windows (depicted as two dashed “hot spots” exist in the design, their process

The general approach to reduce PDYL is to employ strategies that bring process and lithography knowledge into the design and 36

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ellipses) are smaller than the entitlement process window. Since the actual process ��� process windows���������� window is the intersection of all component (shown as the ����������

shaded region), PDYL results. ����������� ������������

Yield Management Solutions ���

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Any successful design for manufacturing (DFM) system must have two components. First, it must be possible to detect and isolate problems. Second, it must facilitate the resolution of the problems. Several point solutions might form a working DFM system if they are integrated and their various strengths combined in a constructive way. As an example, reticle inspection systems play a vital role to ensure that the desired design is properly transferred to the reticle. However, these inspection systems do not verify that the design will result in high yield for the given lithography process. So, reticle inspection should be combined with a system that checks lithographic performance through the process window. This study briefly reviews two existing DFM technologies, and then discusses a new���� approach to evaluating a design for process window sensitivity that can strengthen the suite of tools available for a complete DFM solution. �����

Current solutions for design validation

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Figure 2, MBV systems can be used in the process flow immediately following RET and, therefore, one of their strengths is that problems are found immediately before further investment of resources.

In general, this optical inline checking technique works by parsing the input design edges into small edges.

Then, each edge is used to find the simulated process response from a calibrated model. This simulated process response is then checked with standard DRC tools to look for conditions approaching fail limits. For cost savings, typically the same vendor is used for OPC and MBV. These systems are integrated into the design flow that facilitates feedback of errors and correction of the OPC decoration process. ������ �������

������ Wafer Print Validation

The second type of system for verifying OPC is based on wafer print inspection. Here we will consider a specific solution – process window qualification (PWQ).

As a starting point for reviewing currently available DFM solutions, it is helpful to examine the flow of information through the design process. Figure 2 shows a simple block diagram containing some important stages.

PWQ utilizes an intelligent wafer layout that is inspected on KLA-Tencor’s 23xx series brightfield wafer inspection system. PWQ compares dies with modified lithography parameters against dies at best focus and exposure conditions. The resulting data are analyzed �������������������������� Model-based Verification to identify and prioritize repeating regions of process One technology used to validate the post-RET design window marginality. This method detects problems is called model-based verification (MBV). As shown in that cause failure within the nominal process window or just outside of it. This allows for more informed decisions about how to ������ improve the size of the lithography process ���������� ��� ���������� window. The PWQ system detects problems through the process ����������� ��� ������������ window, facilitating the detection of weak designs. �������������� �� ��� Since the PWQ validation �������������� takes place after the development of wafers, �� ���������� the validation includes all aspects of the lithography ������������� process up to that point. ����������������� For example, the impact of any reticle manufacturing ������������ issues is automatically included. Some effects that are difficult to model Figure 2. Flow diagram of the RET verification process using two technologies available today: MBV and PWQ. MBV is used or account for in other immediately after the RET process and is rule-based. PWQ uses wafers exposed through the process window. systems – such as wafer Fall 2005

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Synergy of Existing Solutions

As stated earlier, a comprehensive DFM system comprises several point solutions that are integrated together to take advantage of the relative strengths of each component. It is easy to see how MBV, PWQ and, for example, reticle die-to-database inspection can be used synergistically.

Although each component is a valuable part of the whole, the desired outcome is to find DFM issues as early as possible because this results in the largest savings of resources and money. For example, a defect found before the reticle is made might be corrected in a few days time and with the expenditure of thousands of dollars. By comparison, a defect found during wafer manufacture could easily cost 10 or 100 times as much with a similar increase in lost time. Even more important is the reduction in time-to-market and shortened learning and solution cycles. Therefore, an optimal DFM solution would include systems that would thoroughly validate the design at an early stage – optimizing the design for the actual manufacturing process.

We now discuss a new approach that can be used to further integrate and strengthen the DFM solution.

Following this explanation, we detail the progress of an on-going evaluation of system performance.

����������������� The DesignScan system consists of hardware and software components, many of which are based on the KLA-Tencor ������������ TeraScan die-to-database reticle inspection system and the KLA-Tencor PROLITH simulation software. Prior to the DesignScan inspection, the post-RET/OPC

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topography and pattern collapse – are also included in the inspection.

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Figure 3. A depiction of the DesignScan inspection paradigm. A patch of the final post RET design is simulated at nominal focus and exposure conditions (center image) and forms the reference. The patch is then simulated at a wide

Simulating design transfer

DesignScan is a new inspection system from KLA-Tencor that detects pattern dependent (featurebased) systematic defects in the lithography process window of the post-RET design. The inspection is accomplished by simulating the transfer of the design to the reticle plane and the subsequent projection of the reticle image into photoresist. The simulations are conducted at nominal conditions and at several focus-exposure points through the process window.

The best focus and exposure condition is the reference for comparison of all other off-focus and exposure conditions. Each simulation within the process window is compared to the one at nominal conditions to detect any unacceptable variation in pattern fidelity.

It is important to recognize that DesignScan assumes, before its inspection, that the best focus and exposure condition has been verified by MBV. This approach is represented in Figure 3.

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range of focus and exposure conditions away from nominal conditions (the images on the perimeter), and each of these simulated results is compared with the nominal.

designs are accessed by the TeraPrep subsystem and converted to a format optimized for inspection throughput. At run time, the converted design is segmented into patches and fed to the proprietary image computer, which is used for both the simulation of the design patches and the detection of defects. The image computer is a multiple-processor based supercomputer capable of simulating multiple jobs simultaneously. Design patches that fail within the process window are noted as defective. Defect reports are sent to the operator console, which is also used for inspection setup and review. The system hardware components are shown in Figure 4.

The simulation models three distinct steps in the lithography process: the transfer of the pattern to the reticle, the formation of the aerial image, and the formation of the resist image. The model for the reticle manufacture process is based on TeraScan technology used for die-to-

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independent defect sensitivity settings. The runtime setup process typically takes less than 10 minutes.

Figure 4. The DesignScan system hardware. The operator console is shown on the left. The TeraPrep sub-system is shown in the dark chassis and the image

At the end of the recipe definition, the inspection process begins and each patch of the design is processed through the simulation and defect detection models.

As explained earlier and depicted in Figure 3, it is at this stage that the various simulations for each design patch are compared to the simulation at nominal conditions. The defect detection algorithm checks for the following types of defects: bridges, breaks, extra and missing printed features, minimum resist width, and minimum space width. The defect detection is based on any topographical change between a test resist profile and the reference resist profile. The minimum resist width and minimum space width defects are those that are close to failing.

computer is shown on the right. A second operator console connected to the TeraPrep is not shown.

database reticle inspection. The aerial image formation uses a vector imaging model. The resist image formation and development are based on a proprietary fast resist model and PROLITH technology.

Each of the three models is calibrated or specified separately and, by design, they are independent and interchangeable. Physics-based models are used to simulate reticle images from the design. The images are compared with reticle SEM images to extract model parameters. The aerial image model is specified by providing the following basic illumination parameters: illumination wavelength, parametric or measured source shape, and objective lens NA. The resist model is calibrated by matching physical parameters to tuning data. The tuning data consists of focus-exposure CD data from 1D lines and spaces at various pitches and sizes. The tuning process has evolved from that used in previous research4.

At runtime, the user creates a recipe through a menudriven graphical user interface (GUI) shown in Figure 5.

It is at this point that the design to be inspected and the previously calibrated or specified models are recalled.

The user also selects the range of focus and exposure conditions to be used in the inspection during this step.

Each focus and exposure point can be defined individually and need not be a regular array of points. Any segment of the design that has been converted to the DesignScan format can be inspected. The system supports the definition of multiple inspection areas, each of which can have

Figure 5. The DesignScan setup GUI. The recipe is created in a series of steps that begin by selecting the design to be inspected.

These defects warn the operator of locations in the design that might fail either later in the process (such as during etch) or if focus and/or exposure deviate any further from the nominal conditions.

A proprietary defect binning model is used to group all identical defects. This greatly improves review efficiency and leverages the hierarchy of the design. The efficiencies gained by the defect binning system will be dependent on the hierarchy of the design and many other factors.

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In the initial tests of the system, using the candidate designs described below, a reduction in the number of unique defects by a factor of seven has been observed.

Review can occur after or concurrent with the inspection. The defect review application shown in Figure 6 can be used to display a wide range of information and the display is user-configurable.

The inspection throughput is a function of the number of focus-exposure points specified for validation and the size of the inspection area. For a 5x7 focus-exposure array (34 test simulations and one simulation at nominal conditions for the reference) the system will inspect an 8 mm x 8 mm patch (wafer scale) in approximately two hours.

Figure 6: The DesignScan review GUI. This interface is configurable and multiple configurations can be saved as templates.

DesignScan inspections are expected to be used as a final verification before the manufacture of the reticle.

At this point in the process flow (see Figure 2) the design has already passed MBV at the nominal conditions. As stated above, it is at this point that the information is most valuable because solutions can be implemented before the expense of making reticles or wafers has been incurred. But, more importantly, any issues can be resolved early in the process, reducing critical cycle time and improving time to market.

Experiments and results

In this section we present the results of the on-going joint evaluation of DesignScan performance by IBM and 40

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KLA-Tencor. Various aspects of the evaluation are presented and analyzed. The results are organized based on three different perspectives: process model calibration accuracy, inspection throughput, and inspection capability.

Process Model Calibration Accuracy

The current mask and wafer models balance the tradeoff between accuracy and calibration effort. Current calibration procedures require detailed wafer linewidth measurements for three simple patterns: an isolated line, an isolated space, and a dense line/space pattern.

Detailed Bossung curves across a range of focus and dose variation were provided through scanning electron microscope (SEM) wafer CD measurements to calibrate a 90 nm gate level at 193 nm wavelength. Mask models were calibrated using reticle SEM images for more accurate modeling of the nonlinearities of the mask manufacturing process and corner rounding.

To facilitate DesignScan’s ability to detect areas of weak process window, DesignScan must accurately predict how the resist images change as focus and exposure vary in the process window. Hence, we focused on evaluating the accuracy of the differential CD predicted by DesignScan models compared to a standard of wafer data measured using a CD SEM. For this study, we used a number of test patterns, including 1D lines through pitch and 2D line ends. Two sets of data were collected for the differential CD from nominal conditions to positive defocus and negative defocus values. Additional measurements throughout a range of dose at nominal focus were also obtained for this accuracy assessment.

Figures 7(a) and 7(b) display a sample of the differential CD measurements on 1D lines from nominal conditions to the out-of-focus conditions that exhibit a reasonably good agreement with the differential CD predicted by DesignScan models at the same conditions. Based on the SEM data, the differential CD accuracy of DesignScan was found to be bounded by ±5 nm (3 sigma) for 1D patterns. Regarding the 2D line ends, the differential CD accuracy of DesignScan was bounded by ±15 nm (3 sigma).

Inspection Throughput

Current versions of the algorithms are not yet optimized for full speed capability. Nevertheless, the current tool capability allowed for an average of 5-1/2 hours runtime on a full 90 nm chip of 7 mm by 9 mm area (wafer scale) at 14 different focus and exposure conditions. Since the time of these inspections, system improvements have been made and the inspection throughput is close to the target capability of two hours for 35 different focus and

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exposure conditions over an 8 mm x 8 mm area (wafer scale). More throughput improvements are planned.

Inspection Capability

The accuracy and efficiency of the inspection algorithm is of critical importance to enable effective optimization of the design for the lithographic process. The accuracy is measured by its capability to capture 100 percent of the failures limiting the process window, and the efficiency is assessed in terms of the number of nuisance defects reported. The current version of DesignScan is able to detect catastrophic defects, which are identified as shorts or opens and missing or extra printing features.

Two additional failure-capturing algorithms capable of finding minimal linewidth and spacewidth violations are now implemented in DesignScan, although they were under development at the time of this evaluation.

This capability reports a defect if the absolute linewidth or spacewidth value at certain focus and exposure setting falls below a predefined CD threshold. This threshold can be adjusted during the inspection setup to an optimum value that minimizes the number of nuisance defects.

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We inspected two candidate 90 nm designs with DesignScan for process window sensitivity using 14 different focus and exposure conditions. Models were calibrated using FEM data exposed with conventional illumination, while the devices analyzed in this paper used annular illumination. Due to the two different illumination conditions, a dose offset was observed. The reference or nominal inspection dose was set using a feature of known size on the wafer. The first candidate design had known process marginality that was further confirmed by DesignScan inspection result of Figure 8a.

The second candidate design had less process sensitivity, and this was correctly captured by DesignScan inspection results of Figure 8b. The inspection results for the first device reported more than 35,000 defects. Of these, 384 were catastrophic; that is, they included gaps and shorts, and the rest were minimum linewidth or minimum spacewidth violations. DesignScan inspection on the second device returned 1193 defects, of which 1080 were shorts from underexposure conditions. DesignScan was able to evaluate the performance of both candidate solutions across a large range of process conditions with small inspection runtimes.

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� Figure 7. Differential CD SEM measurements and differential CD simulated values on 148 different 1D lines. A (top) From nominal conditions to negative defocus, B (bottom) from nominal conditions to positive defocus.

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To further quantify this difference in process window size, we inspected each candidate design with a much larger number of dose and focus points using a smaller increment of each. Based on DesignScan inspections and the point of failure of the most sensitive patterns, we estimate that, for an exposure latitude of ±10 percent, the depth of focus (DOF) for design candidate 2 was larger than the DOF for candidate 1 by 66 percent.

The evaluation of the accuracy of the results was critical for this work. Hence we confirmed on both designs that DesignScan was able to detect all known catastrophic defects within the process window. These catastrophic defects were confirmed by SEM images obtained from

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wafers exposed according to a matrix of focus and dose conditions. Two examples of catastrophic line gaps detected by DesignScan and confirmed with SEM images can be seen in Figures 9 and 10, which also illustrate the Inspection Review GUI resist image gallery of the �� corresponding defect. Figure 11 displays an example of catastrophic bridge or short defect occurring at lower

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dose. These SEM images also show some of the lines collapsing at large negative defocus. This effect, which is presumably produced by a thinning at the bottom of the resist profile, is not being modeled by the current version of DesignScan. Therefore, this type of defect could not be captured. Modeling of this resist failure mechanism will be discussed in the future work section.

In addition to the catastrophic type of defects, DesignScan detected numerous minimum linewidth violations. This capability checks for absolute linewidth values falling below a certain threshold at each focus and dose setting and, as a result, it is very sensitive to model inaccuracies. An example of a minimum linewidth violation was found on an H-bar shown in Figure 12.

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Figure 8. DesignScan full chip inspection defect map on a design with (a) marginal process window and (b) less process sensitivity.

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Figure 9. Inspection Review GUI along with SEM image confirmation displaying one example of catastrophic gaps. The image gallery in this example shows the resist image predicted by DesignScan at 14 different focus/exposure conditions. The nominal condition is shown outlined in a blue dashed box. The blue ellipses circle the defect at points for which we have confirmed the results using wafer print studies.

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The cross member of this H-bar is slightly shorter than the one in Figure 9. According to DesignScan results, this line remains standing at the extremes of the process window, but it gets thin and eventually becomes problematic. This same behavior was observed in the wafer SEM images, also shown in Figure 12. Overall qualitative analysis of SEM images confirmed that those locations identified as minimum linewidth violations were potential process window limiters.

These initial results validated the performance of the minimum linewidth detectors in a qualitative manner. However, no linewidth measurement was taken that would allow a more quantitative analysis, and a more thorough evaluation of this capability is being carried out.

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Figure 10. SEM confirmation of a second example of catastrophic gaps. The top SEM image on the right validates the nominal

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Detailed analysis requires multiple focus/exposure points

Initial evaluation of DesignScan capabilities showed satisfactory results in terms of the model differential accuracy, inspection accuracy, and inspection throughput.

DesignScan capability to quickly verify different RET solutions across the entire process window by detecting process-limiting geometries was demonstrated. Overall, there was good qualitative correlation to SEM images from printed wafers through the process window, and more quantitative work continues.

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focus/exposure resist image prediction of DesignScan. The middle image confirms the defective location������������ to which it points. The bottom SEM image affirms one of the non-defective predictions.

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Figure 11. Resist image gallery and SEM image confirmation of a bridging defect. It is important to note that this defect does not occur at the corners of the process window.

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A comparison of the defects shown in Figures 9 and 12 shows that the designs are not significantly different and the context around the designs is also similar. The main difference between the two designs is the length of the cross member of the H-structure. However, the process window sensitivities of the two design segments are quite different. This enforces the concept that seemingly small differences in design can have significantly different lithographic performance across the process window.

To evaluate the lithographic performance of the design across the process window, one must use many focus and exposure points and not merely those at the corners of the process window. In particular, the bridging defect shown in Figure 11 fails at

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One important future challenge that has been identified is the prediction of resist feature collapse.

DesignScan does not currently have this functionality. This capability will be a focus of work over the next several months. At present, this enforces the synergistic nature of DFM as other systems (such as PWQ) are capable of finding such defects. The current best practice is to understand, leverage, and integrate each system’s strengths for a complete DFM strategy.

Several new enhancements to the system, such as a Figure 12. Qualitative confirmation against SEM images of a defect reported by DesignScan as a minimum linewidth violation. The defect binning capability, bottom SEM image on the right confirms the DesignScan resist image prediction at nominal conditions. were too recent to be included in this study. an under-exposure condition only when at nominal focus We plan to evaluate their effectiveness and report on – so this defect would not have been caught had only the them in the future. corners of the process window been checked. Further, were only a few focus/exposure conditions used, it would Acknowledgements not be as easy to differentiate between a weak pattern that fails only at the extremes of the process window and The authors acknowledge the contributions of IBM’s patterns that are even “more weak” that fail closer to OPC team for providing the design data used in this nominal conditions. The inclusion of multiple focus/exstudy and the lithography team for providing wafer posure points facilitates a more detailed analysis to find verification data. We also want to thank the entire the most critically weak patterns.

KLA-Tencor DesignScan R&D and engineering team.

Conclusion

References

These initial results are viewed as proof of DesignScan’s potential to quickly evaluate the DFM quality of final designs at an early stage when corrections can be made most cost-effectively. The system throughput is such that faster learning cycles for RET development should be possible, leading quickly to the reduction of PDYL.

1. R. Radojcic and M. Rencher, “Old Rules No Longer Apply,” EETimes, April 29, 2003.

Future work

4. S. Jug, R. Huang, J.D. Byers, and C.A. Mack, “Automatic Calibration of Lithography Simulation Parameters,” Lithography for Semiconductor Manufacturing II, Proc., SPIE 4404, pp. 380-395, 2001.

Work is in progress on the tuning of additional processes to be used to inspect several 90 nm and 65 nm designs for various layers. This wide range of use provides valuable information to improve DesignScan performance and functionality.

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2. L.Peters, “Roadmap Challenges Underscore Troubling Trend in Yields,” Semiconductor International, February 1, 2004.

3. L. Peters, “Demystifying Design-for-Yield,” Semiconductor International, July 1, 2004.

This article is based on a paper that was previously published in the SPIE Proceedings 5756-7.

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YWCA of Silicon Valley: Recognizing Executive Excellence

For the past 21 years, the YWCA of Silicon Valley has been recognizing women executives for their leadership and professional accomplishments. This year’s Tribute to Women and Industry (TWIN) honor includes three leaders from KLA-Tencor: Lynn Stasi, Leslie Cross, and Lydia Young. Here’s a look at their roles in helping our customers accelerate yield.

GIVING EMPLOYEES TOOLS TO TURN IDEAS INTO ACTION

KLA-Tencor’s learning organizations offer many online and instructor-led classes globally. Topics range from high-tech speaking to deep ultraviolet (DUV) technology and optical alignment techniques—all customized for the company. Over the past few years, Training Magazine has named KLA-Tencor the fifth best provider of workforce development initiatives in the nation in its ranking of the top 100 companies.

Lynne Stasi VP and Chief Learning Officer When Lynne Stasi joined KLA Instruments Corporation nine years ago, there were no corporate trainers, learning was tracked on multiple systems, and there were no online learning classes. Today, Stasi is Vice President and Chief Learning Officer at KLA-Tencor, overseeing KLA-Tencor’s learning organizations, which are central to the corporate culture.

“We strive to keep our employees’ skills current and sharp, so that what they give to customers is their best,” says Stasi. “By having every KLA-Tencor employee work at his or her most optimal level, we can drive innovation into our tools and help our customers accelerate yield.”

For her role in guiding the company’s Corporate Learning Center, Stasi recently received a TWIN award.

“I’m very excited about this honor,” says Stasi. “Being acknowledged in Silicon Valley is a big thrill, considering all of the innovation that goes on here. I also value having a senior management team who believes that learning creates our culture of innovation and strengthens our competitive advantage.”

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Some other semiconductor companies, according to Stasi, just don’t compare with their learning capabilities.

“Other places have a different mentality, where classes are treated as events rather than as part of a strategic employee development process. At KLA-Tencor, the emphasis is not just on exposing our workforce to ideas, but to enable our employees to implement those ideas to produce a business result,” she explains.

INVESTING IN INNOVATION

With bachelor’s and master’s degrees in learning and adult psychology from the University of Arizona, Stasi’s resumé also includes similar roles at Varian’s Semiconductor Division and Advanced Cardiovascular Systems, a subdivision of Guidant. At KLA-Tencor, a given day for Stasi is filled with back-to-back meetings. She generally assumes the role of a consultant, helping to find cost- and time-efficient ways to deliver relevant learning solutions.

She also reads voraciously, keeping current on the topics that senior management has on their bookshelves.

From change initiatives and new processes to best known methods, KLA-Tencor’s Corporate Learning Center continues to support and enable a variety of critical company objectives. Stasi and her team are understandably excited about the future. “Every time I talk with KLA-Tencor employees, I feel energized by their

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2005 Tribute to Women and Industry innovative ideas and desire to be on the cutting edge of technology,” says Stasi. “KLA-Tencor learning’s charter is to develop our employees to accomplish KLA-Tencor’s mission of enabling our customers to learn faster and yield higher.”

For her leadership in materials management, Cross was selected to receive a TWIN award. Says Cross, “I’m delighted to receive this acknowledgement, as it reflects my team’s real impact on the company’s bottom line and our customers’ satisfaction.”

QUALITY THROUGH BEST PRACTICES

Cross’s key responsibilities include purchasing, supply chain management, inventory control, outsourcing, and production control. A typical day for her may involve everything from expediting parts to setting the global sourcing strategy for a new PSG product.

Leslie Cross Sr. Director of Operations Patterning Solutions Group Leslie Cross knows well the balance required to meet customers’ product needs and also keep corporate inventory levels as low as possible. As a Senior Director of Operations in the Patterning Solutions Group (PSG), Cross is responsible for ensuring that parts are available to build and deliver KLA-Tencor tools on time and to specifications, while also reducing operating costs.

“What customers need and when they need it can be very dynamic,” says Cross. “Our group maintains relationships with an array of suppliers who provide us with materials on flexible schedules as well as access to key technologies that we can incorporate into nextgeneration solutions. We also interact daily with Sales, Engineering, and Marketing to ensure that we deliver on our customers’ expectations.”

To effectively manage changing customer and business needs, her team relies on best practices in supply/demand management, vendor relationship building, contract negotiation, and material flow techniques. “We help our customers accelerate their yield by making sure that we deliver quality tools on time, which we accomplish by sourcing the highest quality parts and making them available at the right time.”

CUSTOMER FOCUS BREEDS SUCCESS

In nearly eight years at KLA-Tencor, Cross has progressed up the materials management career path. She started out as a materials manager, working on master scheduling for the Wafer Inspection Division (WIN). Before joining PSG, Cross was responsible for supply/demand processes at the corporate level.

Together with her team, Cross will continue to focus on cost reduction, keeping inventory levels low and, of course, promoting quality. For women who are making their start in the business world, she offers this advice: “Don’t worry about gender. Instead, understand how you can bring value to your company, and tie your efforts to helping the company make money and meet customer needs.”

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gest reward comes from watching individuals or teams increase their confidence, finally succeed in reaching a goal, and realize, often with surprise, “We did it!”

COMMITTED TO EXCELLENCE IN E-BEAM OPTICS

Program Manager E-beam Review and Classification Division

Seeking a well-rounded education, Young earned her bachelor’s degree in physics from Mount Holyoke College in South Hadley, Massachusetts. Along with a solid scientific background, her program also enabled her to explore the arts and humanities. For her graduate work, Young earned an M.S. degree in applied physics and a Ph.D. in nuclear science and engineering, both from Cornell University in Ithaca, New York.

As a child, Lydia Young didn’t necessarily know what engineering was, but she knew she enjoyed taking things apart to figure out how they worked. Today, Young applies her innate curiosity toward the development of electron beam-based technologies, as Program Manager for the E-beam Review and Classification (EBRC) Division at KLA-Tencor.

She is currently the recipient of 11 patents—with several pending—in the fields of e-beam lithography, chemical vapor deposition, very low k (VLK) dielectrics, and wafer inspection technologies. Some of the biggest challenges that she tacked with her team at the E-beam Center of Excellence related to the nature of e-beam technology.

Over the years, Young has applied her technical savvy to many product areas in the company. Prior to joining EBRC, she was Director of Engineering and Program Manager in KLA-Tencor’s E-beam Center of Excellence in the Patterning Solutions Group (PSG).*At the E-beam Center of Excellence, cross-divisional engineers collaborate on the development of standardized technologies in the areas of electron optics and platform. Young led the electron optics group, which oversees the electron-optics subsystem for multiple e-beam based wafer metrology and film tools. The next-generation automated CD SEM metrology tool and the next-generation SEM review tool are two of the latest products that will incorporate the fruits of their work.

As Young explains, yield-impacting defects are becoming smaller, so the signal will drop for the fixed beam current. But an increase in beam current risks destroying the defect of interest with too much energy, or washing out the image due to charging. As charged particles, electrons can be steered to analyze materials or provide contrast in images. However, if there are insulating materials in the area where the electrons are steered, the e-beam can be misdirected. As a result, the e-beam delivery system must always remain very clean.

Lydia Young

Through her career at KLA-Tencor, Young has also served as Director of Engineering and Program Manager for the Viper 2430 automated macro defect inspection system and as Program Manager for the 2360 patterned wafer inspection tool. Her leadership in the 15-month development and release of the 2360 system led to her recognition with a 2005 TWIN award.

“I’m very grateful and appreciative of receiving this external recognition,” Young says. “Over the years, I’ve had excellent staff members and have tried hard to help them grow as individuals and in teams. By far, the big-

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“Our challenge was to provide electron optics subsystems that deliver a beam where we wanted it, whenever we wanted it,” says Young. “Simply put, these subsystems must meet product requirements for beam quality, remaining highly stable over time.”

As Young and her team strived to meet these beam quality requirements, the end result is clear: Better technologies provided to the product divisions, to integrate into tool platforms that ultimately help customers accelerate their yield. *At press time, the E-beam Center of Excellence was merged into an overall engineering organization supporting several related product divisions.

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Considering Overlay Metrology in the DFM Discussion Mike Adel, KLA-Tencor Corporation

Overlay metrology has become a cornerstone requirement which enables modern lithographic patterning. The mantra of metrology engineers in the litho cell and tool vendors alike has traditionally been TMU — Total Measurement Uncertainty — a metric which combines all sources of metrology tool-related uncertainty. Although relentless TMU reduction is essential, it is certainly not a sufficient condition to meet the overlay control needs for the 32 nm node and below. Many other “on wafer” contributors must be factored into the uncertainty equation. A wider scope in the definition of the overlay metrology process is required, particularly one which views it as part of the greater IC manufacturing process. Current and emerging overlay metrology industry practices will be reviewed in light of the increasing complexity associated with the interactions between metrology tool, target design, and the sampling plan.

Introduction

where reference is made to precision with the qualification that it includes tool-to-tool matching3. That is why the overlay metrology process should be viewed as part of the greater IC manufacturing process. This is illustrated schematically in Figure 1. In this article a definition of the meaning of Design for Manufacture (DFM) in the context of overlay metrology will be proposed. The design process will then be illustrated by two case studies which exemplify two of the steps in the process.

TMU is a statistical concoction whose definition varies markedly over the globe1-2, but is generally structured as a root sum squares of a combination of short-term precision, long-term precision, across wafer tool induced shift variation, and tool-to-tool matching. Interestingly, with respect to overlay metrology, the term TMU does not even appear in the 2004 ITRS roadmap,

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Figure 1. Schematic depiction of uncertainty contributors to overlay model residuals.

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driven by specific sample plans.

This approach may seem obvious but has not necessarily been the case in the past. As will be demonstrated in the example below, significant opportunities exist to improve the DFM process on overlay metrology.

Example 1 — Sampling and Model Optimization

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Modeling of overlay metrology data is performed routinely on data acquired on product wafers.

This type of modeling serves two primary purposes, lot dispositioning and feedback of correctibles to the exposure tool.

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���������������������������������������������������� Figure 2. Schematic depiction of DFM methodology for overlay metrology, showing the three elements of sample and model, metrology target, and metrology tool. Semiconductor manufacturing processes are at the center, driving the requirements of all three elements.

Today, a frequently applied method of overlay modeling is the “double pass” method

What is DFM for overlay metrology?

DFM in overlay metrology dictates recognition of the three elements in the metrology process: sample plan/model, overlay target, and overlay tool. Figure 1 is a graphical representation of these three overlay metrology system components and the dependencies between them.

A DFM approach puts the semiconductor manufacturing process at the center, driving the requirements for each of the elements. Amongst the three elements exists a clear hierarchy within the triad, defining the sequence of optimization. The sample plan and the model must be a primary consideration in the overall system design, as this is driven directly by the overlay control error budget and the sources of variation characteristic of the alignment scheme in question. Next in the optimization sequence is the overlay mark design. This is impacted directly by the sample plan, e.g. target size requirements.

Compatibility with the semiconductor manufacturing process, e.g. maintaining pattern density requirements for compatibility with CMP, is also a factor. The metrology tool is placed at the bottom of the hierarchy, since its design and performance parameters are derived by demanding compatibility with all of the above; for example: the ability to meet metrology uncertainty requirements on optimized metrology marks with throughput, which meets cost of ownership requirements

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Figure 3. Typical overlay metrology modeling sequence, known as the double pass method enabling both lot rework and scanner adjustment decisions.

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Example 2 — Target Optimization

Figure 4. Modified overlay metrology modeling sequence, in which the mean

Today, virtually all semiconductor manufacturers live with model residuals which are well beyond the level anticipated based on metrology tool or lithography process uncertainty contributors. Furthermore, some manufacturers are forced to add costly process steps because the metrology tool/target interaction is negatively impacted by CMP, deposition, or etch processes.

intrafield model step is modified and additional weighting is enabled.

described in the flowchart, depicted in Figure 3. In this method it is assumed that the sources of overlay variation across the wafer may be divided into wafer level or “interfield” contributors and field level or “intrafield” contributors. In keeping with this assumption, under normal high-volume production circum�� stances, only two sets of correctibles, one linear �� in wafer coordinates and one linear in field coordinates, are fed back to the exposure tool’s �� wafer and reticle stages, respectively. �� �� �� � ������������

These correctibles are also used for the purpose of computing a lot dispositioning parameter such as maximum predicted overlay (MPO), the second key decision driven by overlay metrology data. This procedure is diagrammed in Figure 3.

Overlay metrology data may show significant field-to-field variation in the intrafield model terms4. As a result, the model residuals— that is, the differences between the measured overlay and that computed by the model at the same point—are often strongly influenced

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This is a strong indication that an opportunity exists to improve lot dispositioning and correctibles accuracy.

An alternative modeling sequence to that in Figure 3 is shown in Figure 4. In this case, intrafield correctibles are computed field by field prior to calculation of MPO or any other lot dispositioning parameter. Furthermore, the intrafield correctibles sent back to the scanner can now be determined in a more sophisticated fashion, which may give weight to or even ignore certain fields based on other criteria such as overlay target asymmetry, target noise, or even alignment data from the scanner.

Alternatively, if the intrafield model is allowed to vary from field to field, then the impact of this field averaging on the model residuals can be quantified. Figure 5 shows the three sigma overlay model uncertainty at the field corners due only to the field-to-field intrafield correctibles variability. This calculation has been performed on overlay data from both production environments and R&D studies.

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or even dominated by the field-to-field variation, since the standard model relies on “average” intrafield model terms.

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Figure 5. Three sigma overlay model uncertainty at the field corners due only to the field-to-field intrafield correctibles variability. Data from 130 and 90 nm processes in both production and R&D environments.

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Figure 6. Overlay metrology targets: left box-in-box targets from two different sites on the wafer; right, AIM grating targets from same sites. Box targets suffer from strongly asymmetric contrast variations compared with AIM. Courtesy of ST Microelectronics.

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Conclusions

A DFM approach to overlay metrology dictates an optimization sequence as follows: 1. Optimize model and������ sample plan for sources of variation. ����� �������� ����������������� 2. Optimize target for 1 above and for semiconductor manufacturing process.

3. Optimize tool for 1 & 2.

Figure 6 shows box-in-box and AIM targets from different locations on wafers from a 130 nm FEOL flash Examples of optimization from steps 1 and 2 have been �� memory process. The two examples of box targets on shown. In the first case it was shown that field-to-field the left are from two different locations on the wafer. �� intrafield variability in model terms is a significant conStrong variations in target asymmetry are observed �� tributor to model residuals. Under these circumstances, in the images. On the right of the figure, images are model and sample optimization is proposed which can �� shown of AIM targets printed adjacent to the box potentially improve lot dispositioning and correctibles �� targets on the left.

Although a contrast reversal is accuracy. In the second case, target optimization for �� observed in the grating image between the two locacompatibility with the semiconductor manufacturing � tions, image asymmetry is significantly reduced to process was shown to significantly reduce overlay model � enable a major improvement in metrology robustness. residuals and improve residuals XY symmetry.

In� this particular case, migration of the metrology � process from standard box targets to AIM targets In the near future, the metrology tools themselves will � resulted in a 50 percent reduction in overlay model have to be further optimized not just for reduction in ����� ������ �������� residuals, as shown in Figure 7. A careful inspection of ����������������� tool uncertainty as quantified in brief evaluations. The this data also reveals a reduction in the XY asymmetry optimization metric will be the enabling of a rapid inherent in the box-in-box residuals. transition to consistent peak performance on processcompatible metrology marks for new and challenging process layers in an expanding repertoire of sample plans.

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� A number of advanced IC manufacturers are overcoming these challenges by adopting new practices including � using AIM targets for improved process compatibility � and stability. The AIM target, as opposed to the box� in-box target, is comprised of a grating structure5, allowing it to meet pattern density requirements set down by other manufacturing steps such as CMP or etch. This has been characterized in a number of ways in previous publications6-7.

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Figure 7. Three sigma overlay model residuals in nm from a 130 nm flash memory process, before and after transition����������� from BiB to AIM based metrology. Data courtesy of STMicroelectronics - R2 Technology Center FTM - Lithography, Agrate B. Italy.

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Acknowledgments

The author would like to thank the OCSLI consortium partners for providing part of the data. Thanks also to STMicroelectronics - R2 Technology Center - FTM - Lithography, Agrate for allowing the use of the AIM residuals data. The author is indebted to the following individuals for their contributions in the preparation of this work – Pavel Izikson of KLA-Tencor Israel for his probing statistical analysis, John Robinson of KLA-Tencor, and Austin and Bernd Schulz of AMD Saxony for insightful comments and discussions.

References 1. A. F. Plambeck, “Overlay metrology as it approaches the gigabit era,” Microlithography World, Winter 1996, pp.

17-22.

2. C. Gould, “Advanced Process Control: Basic Functionality Requirements for Lithography,” 2001 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 49-53.

3. International Technology Roadmap for Semiconductors (ITRS) 2004 Update, Section Metrology, p. 6, Table 117a Lithography Wafer Metrology Technology Requirements— Near-term.

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4. P. Leray, I. Pollentier, E. Kassel, P. Izikson, M. Adel, B. Schulz, R. Seltmann, J. Krause “In field overlay uncertainty contributors” in Proceedings of SPIE Vol. 5752, Metrology, Inspection, and Process Control for Microlithography XIX, D. J. Herr, Editor, (SPIE, Bellingham, WA, 2005), to be published.

5. M. Adel, M. Ghinovker, B. Golovanevsky, P. Izikson, E. Kassel, D. Yaffe, A. M. Bruckstein, R. Goldenberg, Y. Rubner, and M. Rudzsky, “Optimized Overlay Metrology Marks: Theory and Experiment” IEEE Transactions on Semiconductor Manufacturing, Vol. 17 , No.2, May 2004.

6. M. Adel, J.A. Allgair, D. C. Benoit, M. Ghinovker, E. Kassel, C. Nelson, J. C. Robinson, G. S. Seligman, “Performance Study of New Segmented Overlay Marks for Advanced Wafer Processing,” in Proceedings of SPIE vol.

5038 Metrology, Inspection, and Process Control for Microlithography XVII, D. J. Herr, Editor, (SPIE, Bellingham, WA, 2003) pp. 453-463.

7. M. Adel, M. Ghinovker, J. Poplawski, E. Kassel, P. Izikson, I. Pollentier, P. Leray, D. Laidler, “Characterization of overlay mark fidelity,” in Proceedings of SPIE Vol. 5038, Metrology, Inspection, and Process Control for Microlithography XVII, D. J. Herr, Editor, (SPIE, Bellingham, WA, 2003), pp. 437444.

This article is based on a paper that was originally presented at The International Conference on Characterization and Metrology for ULSI Technology 2005.

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Product News Archer AIM+

Advanced optical overlay metrology

Featuring an improved optics design, enhanced light system, and a new advanced focus mechanism, the Archer AIM+ continues to set the standard for lithography process control through the ≥ 45-nm node. By leveraging the field-proven box-in-box (BiB) and AIM grating-style technology with hardware and optics improvements, the Archer AIM+ further reduces the measurement uncertainty associated with traditional overlay metrology at shrinking design rules. Fabs using the tool, which provides 20 percent better throughput than previous-generation solutions, can achieve tighter overlay control, improved yield, and enhanced cost of ownership.

Archer AIM+

Archer XT+

Advanced overlay metrology

The Archer XT+ provides an advanced optical overlay metrology solution with an improved optics design, enhanced light system, and a new advanced focus mechanism. The tool further reduces the measurement uncertainty associated with traditional overlay metrology at shrinking design rules. Based on the widely adopted Archer platforms, the Archer XT+ improves yield and cost of ownership by boosting throughput 20 percent over previousgeneration solutions.

Phoenix Handler

Standardized platform for better performance and cost control

To continue driving enhancements in performance, cost, reliability, and serviceability, KLA-Tencor’s Automation Standards Division (ASD) has launched a standardized tool handler platform, the Phoenix handler. Supporting nearly all KLA-Tencor wafer inspection and metrology tools, the Phoenix handler provides a dual-blade robot design that brings enhancements to several areas:

Archer XT+

• Reliability: Mean cycle before failure (MCBF) and mean time before failure (MTBF) have been extended, in one case by as much as 4x • Serviceability: The new handler offers ease of service with slide-out access to electronics and fast module replacement, and a diagnostics graphical user interface (GUI) that is accessible via laptop or the tool • Performance: Wafer placement repeatability is 50 percent better, and tool- and recipe-dependent throughput have been improved by up to 30 percent Phoenix Handler

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• Cleanliness: The new handler offers a 10x improvement in airborne performance, with a positive exhaust flow, no re-circulation zones, and no dead zones. In other words, much less frequent occurrence of frontside and backside particles.

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Online Recipe Services

Faster tool recipe qualification and troubleshooting

Online Recipe Services leverages online access to KLA-Tencor applications experts worldwide to speed tool recipe qualification and troubleshooting.

Available through iSupport—our highly secure network that includes expert onsite support, 24/7 online support, and e-diagnostics built into every new KLA-Tencor tool—Online Recipe Services delivers fast response to recipe issues through measurement effectiveness. When a recipe issue arises, applications experts can remotely access the tool from a worldwide online support center to quickly troubleshoot the issue or help qualify a new recipe, reducing or eliminating the wait time needed for onsite support.

Onsite personnel, in the meantime, can focus their efforts on the highest priority tool and recipe issues. Online Recipe Services also helps facilitate customer training and knowledge transfer in the customer’s local language.

Online Recipe Services

SP2 Wins 2005 Best Product Award KLA-Tencor’s Surfscan SP2 unpatterned wafer inspection system has earned one of Semiconductor International’s 2005 Editors’ Choice Best Product Awards.

The product was honored, along with other winners, during SEMICON West, held in July in San Francisco, California.

As one of 20 products selected to receive this honor, the SP2 met the publication’s stringent criteria for, in its case, proven excellence in the advancement of wafer processing. The magazine’s editors rated award entries based on answers to key questions, their own knowledge of the products, and user feedback.

The Surfscan SP2 is the most sensitive bare wafer inspection tool on the market. Wafer and IC manufacturers recognize SP2 as TOR, and utilize the tool to qualify current and next-generation substrates and to qualify and monitor process tools at the 90-, 65-, and 45-nm nodes, respectively. Introduced in June 2004, the SP2 incorporates revolutionary UV laser technology, darkfield optics, and advanced algorithms to find defects as small as 30 nm. The production performance of the SP2, and the extendibility of the technology, are marked by the size and number of defects that the tool can reliably detect on a bare wafer with a shorter wavelength UV laser. Compared to the previous industry benchmark system, the Surfscan SP1, the SP2 offers up to a five-fold throughput increase for wafer manufacturers and a three-fold increase for IC manufacturers. The platform is also the only productionworthy solution that enables consistently reliable and accurate defect detection on sub-45-nm engineered substrates, including SOI, strained silicon, and strained silicon-on-insulator.

“We are delighted to receive this honor from Semiconductor International,” says Mike Kirk, vice president and general manager of KLA-Tencor’s Surfscan Division. “This award recognizes the value that our customers already experience in the SP2—that it is a high-performance solution delivering the low cost of ownership that wafer and IC manufacturers need in order to thrive amidst increasingly challenging demands for quality.”

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