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Where in the World is the Process Yield Window? Conjoint DFM and APC Strategies for Reducing Hidden Systematic Errors at 65 nm and Below Kevin Monahan and Brian Trafas, KLA-Tencor Corporation
Immersion lithography at 193 nm has emerged as the leading contender for critical patterning through the 32 nm technology node. Super-high numerical aperture (NA), along with attendant polarization effects, will require re-optimization of virtually every resolution enhancement technology and the implementation of advanced process control (APC) at intra-wafer and intra-ďŹ eld levels. Furthermore, interactions of critical dimensions (CDs), proďŹ les, roughness, and overlay between layers will impact design margins and become severe yield limiters. In this work, we show how design margins are reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmodeled, and uncorrectable components. We apply four new process control technologies that use spectroscopic ellipsometry, grating-based overlay metrology, e-beam array imaging, and simulation to reduce hidden systematic error. Feedback of super-accurate process metrics will be critical to the application of conjoint design for manufacturability (DFM) and APC strategies at the 65 nm node and beyond. Manufacturing economics will force a trade-off between measurement cost and yield loss that favors greater investment in process control. Addressing pattern limited yield
In this work, we assess the impact of hidden error on pattern limited yield and generate unique CD and overlay-limited yield models for the 65, 45, and 32 nm nodes. We expect 193 nm immersion lithography to remain the dominant patterning technology at the 32 nm node (Figure 1). Even at the 130 nm node, the interaction of more complex designs with shrinking process windows was already evident. In memory manufacturing, for example, ramp delays of several months were common, leading to revenue losses in the tens of millions of dollars per product and reduction of ROI for 300 mm factories. Ramp delays occur primarily for two reasons: lengthy process optimization for smaller yield windows and increased time allocated for more complex intra-ďŹ eld corrections (e.g., re-design and re-layout). We and the semiconductor industry are Fall 2005
Yield Management Solutions
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