Kronse kt luf2012 final by KLA Corporation

LITHOGRAPHY CHALLENGES FOR (SUB-)20NM SEMICONDUCTOR TECHNOLOGY NODES KURT G. RONSE 12 FEBRUARY 2012

KLA-T LITHOGRAPHY USERS FORUM 2012

MOORE’S LAW CONTINUING NEW DRIVERS

~ 16-14 nm

~ 90 nm

Litho Enabled Scaling

Patterning Enabled Scaling

Materials Enabled Scaling

“PATTERNING”,

 Films (deposition)  Lithography  Dry etch

3D Enabled Scaling

MOORE’S LAW CONTINUING NEW DRIVERS

~ 16-14 nm

~ 90 nm

Litho Enabled Scaling

Patterning Enabled Scaling

Materials Enabled Scaling

“PATTERNING”,

 Films (deposition)  Lithography  Dry etch

3D Enabled Scaling

GEOMETRICAL SCALING BASED ON 3 CORNER STONES

Layout

Scanner enhancements

Advanced Patterning

GEOMETRICAL SCALING BASED ON 3 CORNER STONES

compliancy Layout DR Design decomposition

Computational litho (SMO, ...)

Scanner enhancements

ÂŠ IMEC 2012 K. RONSE - KLA-T LUF 2012

Advanced Patterning

GEOMETRICAL SCALING BASED ON 3 CORNER STONES

Layout

Scanner enhancements Advanced Patterning New Scanner ‘Knobs’ Flexray, Flexwave, ... CDU/OVL control

Multiple patterning LPLE, LELE, SADP, DSA

Complementary (insertion of EUV) 6

GEOMETRICAL SCALING BASED ON 3 CORNER STONES

Layout

Scanner enhancements

Advanced Patterning Multiple patterning LPLE, LELE, SADP, DSA

Complementary (insertion of EUV) © IMEC 2012 K. RONSE - KLA-T LUF 2012

OUTLINE Introduction Advanced patterning Layout trends in advanced logic (incl. SRAM) EUV lithography status and insertion Scaling limited by overlay ? Summary and conclusions

ÂŠ IMEC 2012 K. RONSE - KLA-T LUF 2012

SPACER DEFINED PATTERNING SELF ALIGNED DOUBLE PATTERNING - SADP

Potential Process flow ▸ Advantages ; -

Frequency doubling Precise CD control (linked to film thickness) Improved LER Self-alignment Potential to repeat : SAQP (quadruple spacer)

▸ Challenges : - Complex patterning stack requiring multiple deposition and etch steps (CoO) - Precise dose control (pitch-walking) - Requires at least 1 and often 2 additional litho steps : cut mask / pad mask

▸ Application : - 1. Flash memory - 2. Advanced logic (FIN, gate, ...) - 3. DRAM ??? © IMEC 2012 K. RONSE - KLA-T LUF 2012

Source : www.itrs.net

Paper 8326-12 Alexander Miloslavsky et al, Tue 14.00 9

Self aligned double pattering with EUV litho

15 nm

ÂŠ IMEC 2012 K. RONSE - KLA-T LUF 2012

DIRECTED SELF-ASSEMBLY THE SUCCESSOR OF SADP ? ▸ Principle Self-Assembly - Block co-polymers can give microscopic phase separation

▸ Directed self-assembly (DSA) : guiding patterns - Topographical guiding : grapho-epitaxy

- Chemical guiding : chemo-epitaxy

Paper 8325-16 Mark H. Somervell et al, Tue 9.40am

A DSA PROCESS FLOW EXAMPLE UW FLOW (CHEMO-EPITAXY)

X-PS cross-linking

Pattern the PR

-OH brush grafting

ÂŠ IMEC 2012 K. RONSE - KLA-T LUF 2012

BCP annealing

O2 etching

PR strip with solvent

PMMA removal

12 Paper 8323-12 Paulina A. Rincon Delgadillo et al, Tue 11.40am

DIRECTED SELF-ASSEMBLY ▸ Potential power : - Frequency multiplication (x N : extention of SADP) - Pattern “healing” (e.g. contact hole local CD variation)

60nm

▸ Key questions to be answered :

29nm

Source : Joy Cheng et al, IBM, Miami 2011

- Material purity for IC processing (“from lab to fab”) - Process flow and material stability and control (process windows) - Resolution, defect density – pattern fidelity © IMEC 2012 K. RONSE - KLA-T LUF 2012

OUTLINE Introduction Advanced patterning Layout trends in adv. logic (incl. SRAM) EUV lithography status and insertion Scaling limited by overlay ? Summary and conclusions

ÂŠ IMEC 2012 K. RONSE - KLA-T LUF 2012

LOCAL INTERCONNECT

EXTRA LAYERS IN-BETWEEN TRADITIONAL FRONT- AND BACK-END

Simple example: one Active and one gate contact Metal1

Without LI

Contact Poly Active

STI

Metal1 Via0

With LI

LI2 LI1 Poly Active

STI

Why LI?: • Offers advantages in electrical performance & reliability, cell-routability and litho printability ⇒ generally adopted from 20 nm node onwards

An approach using 2 LI layers seems to be adopted in the industry • But: no industry standard on how exactly to implement

• The introduction of LI completely changes the layout of Logic & SRAM cells • LI eases the printability of backend layers (esp. Metal; contacts become trenches) • Contact is replaced by 4* (critical) layers *LI1, LI2A, LI2B and Via0

SRAM LAYOUT: IMPACT OF USING LI PLANAR TYPE OF DEVICE (I.E. NOT FINFET) LI2A - LI2B

Via0 – Metal1

Via1 – Metal2

Via2 – Metal3

without LI

Active – Gate - LI1

Dual-layer LI

Metal1: cannot be printed any more beyond 28 nm node

All layer-layouts (except Front-End) are very different © IMEC 2012 K. RONSE - KLA-T LUF 2012

LOGIC-CELL LAYOUT: IMPACT OF USING LI EXAMPLE: XOR, METAL1 LAYER

without LI

High Metal1 density Severe Splitting conflicts ⇒

Dual-layer LI

Reduced Metal1 density Pattern splitting = easier

• Multiple (>2) patterning (), or • Re-layout (with area increase) © IMEC 2012 K. RONSE - KLA-T LUF 2012

OUTLINE Introduction Advanced patterning Layout trends in adv. logic (incl. SRAM) EUV lithography status and insertion Scaling limited by overlay ? Summary and conclusions

ÂŠ IMEC 2012 K. RONSE - KLA-T LUF 2012

EUV FOCUS AREAS 2007-2011:

22 NM HALF-PITCH INSERTION TARGET 2007 / 22hp 2008 / 22hp 2009 / 22hp 2010 / 22hp

2011 / 22hp

1. Reliable high power source & collector module

1. Long-term source operation with 100 W at IF and 5MJ/day

1. Mask yield & defect inspection/review infrastructure

1. Long-term reliable source operation with 200 W at IF*

2. Resist resolution, sensitivity & LER met simultaneously

2. Defect free masks through lifecycle & inspection/review infrastructure

2. Long-term reliable source operation with 200 W at IF

1. Long-term reliable source operation with 200 W at IF

2. Mask yield & defect inspection/review infrastructure

3. Availability of defect free mask

3. Resist resolution, sensitivity & LER met simultaneously

2. Resist resolution, sensitivity & LER met simultaneously

3. Resist resolution, sensitivity & LER met simultaneously

4. Reticle protection during storage, handling and use

• Reticle protection during storage, handling and use

• EUVL manufacturing integration

5. Projection and illuminator optics quality & lifetime

• Projection / illuminator optics and mask lifetime

HVM introduction in late 2013 if productivity challenge can be met © IMEC 2012

2011 EUVL Symposium

ASML NXE:3100 AT IMEC

0.25NA FULL FIELD EUV SCANNER

ASML NXE:3100 interfaced to TEL Lithius Pro EUV and equipped with Ushio DPP source © IMEC 2012 K. RONSE - KLA-T LUF 2012

NXE:3100 CHAMPION RESOLUTION 16NM HALF PITCH RESOLVED

18nm hp

17.5nm hp

17nm hp

16nm hp

33mJ/cm2 30°Dipole σ 0.8/0.7

8322-54,Tom Wallow et al, Thu 9.30am

EUV RESIST STATUS

RLS TRIANGLE FOR 25NM L/S ON NXE:3100

Sensitivity (mJ/cm2) 25

50nm FT 40nm FT

20 15 NXE Target for 25nm LS

dipole 5 2

2.5

3.5

4.5

LER (nm)

LER is the biggest issue to meet the specs © IMEC 2012 K. RONSE - KLA-T LUF 2012

LWR REDUCTION

BY POST-PROCESSING (SMOOTHING MODULE ON TEL LITHIUS PRO )

Post-Litho

Post-Smoothing

LWR= 5.7nm

LWR=4.7nm

3sigma LWR 17% (high/mid range spatial frequency) © IMEC 2012 K. RONSE - KLA-T LUF 2012

8322-77 Hideo Shite et al, Thu 18.00-20.00

LWR REDUCTION

BY DRY ETCH PRE-PLASMA TREATMENT Post-Litho

5.5

LWR

LWR and LER (nm)

Post-Etch

LER 4.5 4 3.5 3 2.5

EUVL H2 PPT Encap Exp

ULE

HMO

Si-Et

Si Et (Opt)

3sigma LWR and LER improved by 30%

24 8328-19 Efrain Altamirano-Sánchez et al,Tue.15.30

NXE:3100 OFF-AXIS ILLUMINATION 27NM DENSE CONTACT HOLES

Conventional 14% EL 240nm DOF

Quasar

19% EL 320nm DOF Biggest issue is local CD variation © IMEC 2012 K. RONSE - KLA-T LUF 2012

8322-21 Roel Gronheid et al, Tue 14.50

OTHER RESIST/PROCESS ISSUES ▸ Outgassing ▸ Pattern collapse

8322-50 James H. Underwood et al, Wed 17.40

8325-27 Gustaf Winroth et al, Tue 17.20

▸ Process defectivity ▸ ...

Important engineering work but no fundamental show stoppers © IMEC 2012 K. RONSE - KLA-T LUF 2012

EUV MASKS

DEFECTIVITY KEY CONCERN

▸ Multilayer defects (ML) - Substrate / blank

▸ No pellicle : - reticle handling in fab to avoid particle adders (EUV PODS)

▸ Defect repair - Successful repair on EUV absorber defects demonstrated by Zeiss (also compensation repair on some ML defects)

▸ Defect inspection : - Actinic blank inspection under development (EIDEC) - EUV AIMS under development (Zeiss – EMI) - Performance of today’s state-of-the-art inspection tools

8322-11 Markus Waiblinger et al,Tue.9.00

COMPARISON PATTERNED EUV MASK VS WAFER DEFECT INSPECTION PROGRAMMED DEFECTS

detected capture rate <90% not detected

Defect design 14nm

16nm

18nm

20nm

22nm

24nm

26nm

28nm

30nm

32nm

36nm

40nm

Image on mask

KT Teron PMI capture rate Image after nitride etch KT 2835 WI capture rate (nitr. etch)

• Wafer(1X): programmed defects confirm ~20nm protrusion is about detection limit • Mask (4X): detection limit can go beyond printing defects (for absorber defects) © IMEC 2012

K. RONSE - KLA-T LUF 2012

8324-20 Dieter Van den Heuvel et al,Tue.13.30 28

EUV INSERTION OPPORTUNITIES ▸ EUV insertion mainly in BEOL (contacts, trenches) rather than FEOL - Very high resolution long FINs and gates can be nicely patterned using 193i with SADP - The benefit of EUV has to come from its intrinsically higher resolution for printing holes, trenches, high resolution cuts...

EXAMPLE : PV BAND SIMULATIONS 14NM HIGH DENSITY SRAM LI1

LI1: SP

LI1-Fill: SP

LI1-Fill: DP

EUV

LI1 target

Fin Gate IM1 MEF

193i

Pitch: about 60 nm Smallest gap: 25 nm

X 30

▸ These benefits become visible at the 14nm logic node - The gain is in number of masks... - On the condition that the overlay to193i is good enough

OUTLINE Introduction Advanced patterning Layout trends in adv. logic (incl. SRAM) EUV lithography status and insertion Scaling limited by overlay ? Summary and conclusions

ÂŠ IMEC 2012 K. RONSE - KLA-T LUF 2012

MAIN EUV-SPECIFIC SCANNER CONTRIBUTIONS TO OVERLAY – AS LEARNT FROM ADT CONTRIBUTION Reticle (clamp) flatness (e-chuck)+ non-telecentricity) (e-chuck

Vacuum purge chamber and thermal stability

Wafer clamping (e-chuck)

EFFECT ON OVERLAY

Intrafield distortion

Wafer grid and intrafield stability

Wafer grid stability

KLA-TENCOR SCANNERTEMP SOLUTION SCANNER TEMPERATURE MONITORING

ScannerTemp wafer (Sensarray wafer)

▸ To investigate thermal behavior, the wireless ScannerTemp wafer from KLA-Tencor is used ▸ Wafer temperature stability and uniformity is measured during exposure sequence

Non-contact BaseStation

THERMAL BEHAVIOR OF FIRST WAFER

= wafer alignment 1

2 1. 2.

Wafer exposure preparation Wafer exposure

Wafer temperature stable before and during “exposure” of a first wafer on NXE:3100: no large wafer expansion difference expected © IMEC 2012 K. RONSE - KLA-T LUF 2012

8322-1 Jan V. Hermans et al, Mon 13.30

IMPACT OF THERMAL BEHAVIOR ON FIRST WAFER

ADT

Scaling X (ppm)

Scaling Y (ppm)

0.2

0.150

0.15

0.100

0.1

Scaling (ppm)

0.200

0.050 0.000 -0.050 -0.100

Scaling Y (ppm)

0.05 0 -0.05 -0.1

-0.150

-0.15

-0.2

Wafer #

-0.200

Scaling (ppm)

Scaling X (ppm)

NXE:3100, Single chuck mode, Chuck 2

Wafer #

No clear first wafer effect on wafer scaling on NXE:3100 due to improved thermal stability ÂŠ IMEC 2012 K. RONSE - KLA-T LUF 2012

XT:1900GI TO NXE:3100 – EXPECTED VS MEASURED PERFORMANCE USING ALL THE TOOLS AND ENHANCEMENTS AVAILABLE TODAY (HIGH ORDER GRID AND INTRAFIELD CORRECTIONS)

Measured

frequency

Expected

3σ: X = 5.6nm, Y = 5.5nm.

3σ: X = 6.0nm, Y = 5.6nm.

8326-22 David Laidler et al, Wed.8.20

XT:1900GI TO NXE:3100 – EXPECTED VS MEASURED PERFORMANCE USING ALL THE TOOLS AND ENHANCEMENTS AVAILABLE TODAY

frequency

Measured

3σ: X = 6.0nm, Y = 5.6nm.

8326-22 David Laidler et al, Wed.8.20

OVERLAY REQUIREMENTS LOCAL INTERCONNECT LI1 TO GATE

▸ Challenge : LI1 should not contact the gate : - Narrow trench width ! - Alignment budget becomes very thight !

20nm 82 24 5 26

14nm 58 20 5 18

5 39

SELF-ALIGNED PROCESSES PRINCIPLE

Non-self-aligned

Self-aligned: • LI1-mask: trench >> intended LI1 width • Spacer requirement: high etch selectivity

• Litho target trench-widths can be ‘larger’ (~P_Gate/2) • Self-aligned ⇒ no impact of LI1-Gate overlay errors • Process : difficult (find the materials with the right etch selectivities © IMEC 2012 K. RONSE - KLA-T LUF 2012

SUMMARY AND CONCLUSIONS ▸ IC scaling continues to follow Moore’s law ▸ Advanced patterning techniques have become the main driver for geometrical scaling in 193 immersion ▸ Layout optimization and design for manufacturability are key requirements ▸ EUV momentum continues but source power and reliability remain the most critical focus item ▸ Overlay budgets are getting extremely tight and require clever process solutions ▸ 193nm immersion and EUVL are the key technologies for volume production of the next technology nodes © IMEC 2012 K. RONSE - KLA-T LUF 2012

SUMMARY AND CONCLUSIONS/2 ▸ Alternative lithographies like e-beam direct write are behind in terms of momentum but may find their own niche markets (e.g. fast prototyping, advanced mask writing, ...) - Interesting progress has been reported with KLA-T REBL

ACKNOWLEDGMENTS ▸ KLA-T ▸ Lithography and Patterning teams at imec ▸ Special thanks for input to this presentation : -

Peter De Bisschop Mieke Goethals Roel Gronheid Vincent Wiaux Jan Hermans Dieter Van Den Heuvel David Laidler Eric Hendrickx Shaunee Cheng Geert Vandenberghe Steven Demuynck ....

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