Magazine autumn98 p22

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Yield Enhancement with Bitmap Analysis

by Ken Bernstein, Program Manager

Review of failing bit data collected by automated test equipment (ATE) is an essential tool used by engineers to improve the yield of memory arrays. While visual inspection of this data provides the engineer with the locations of failing bits, analysis of the failing bit patterns can help pinpoint the cause of bit failures.

With the introduction of KLA-Tencor’s BitPower™ Analysis System, bitmap analysis has transitioned from an offline engineering function into an ongoing manufacturing process for yield improvement. With this system, bitmap data is collected during production test, failing bit patterns are automatically extracted, and the data is passed to Klarity™, KLA-Tencor’s automated analytical software module, where it is analyzed in conjunction with the physical defect data collected at in-line inspection points. Such analysis helps correlate defects detected earlier in the manufacturing process to an electrical failure identified at the end of the process. This bitmap line monitor is illustrated in figure 1. When off-line engineering analysis is required, KLA-Tencor’s BitPower System provides powerful bitmap review software for full reproduction and visualization of failing bit data and their exact topological locations, thus preserving the ability to view original and absolute bit coordinates.

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Figure 1. (a) KLA-Tencor’s BitPower system collects data from ATE. (b) Bitmap data is converted from electrical to physical coordinates and bit patterns are extracted. (c) Physical bit pattern data is transmitted to Klarity. (d) Klarity can analyze the bitmap data in conjunction with other data sources.

Bitmap line monitor step 1: Data collection

As the first step in implementing the bitmap line monitor, the KLA-Tencor BitPower system collects raw electrical bitmap data from the ATE. Memory testers are the traditional source of bitmap data; but with the memory content rising in non-memory devices, it has become increasingly common for logic and mixed signal testers to have the ability to produce bitmap data. KLA-Tencor’s BitPower system can accept data from any of these sources.

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Bitmap line monitor step 2: Electrical-tophysical conversion

In order to understand the cause of an electrical failure of a die, it is important to pinpoint the exact location of the failure point on that die. Converting electrically failed bit data into meaningful, physically correct coordinates has traditionally been a time-consuming and errorprone process due to complex internal address scrambling of the memory arrays. The BitPower system provides revolutionary new utilities that allow the user to easily create die models that perform the map-

ping between electrical addressing and physical coordinates. Any die type can be modeled, including those with multiple on-board memory arrays such as DSPs and microprocessors.

As the physical data is created, the original electrical data is not discarded. Instead, it is compressed and saved to allow off-line manual analysis of the bitmap data with BitPower’s Bitmap Review Software. Such analysis is often required to review optically invisible defects that have resulted in the electrical failure of a die. The soft-

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ware allows the user to view failures at the wafer level or the die level.

The wafer-level bitmap viewer (figure 2b top image) is capable of displaying the bitmap data across the wafer. The die-level bitmap viewer (figure 2b lower image) provides the more traditional die and sub-die-level bitmap representation.

Bitmap line monitor step 3: Bit-pattern extraction

After the bitmap data is converted into physically correct coordinates, it can be searched for patterns such

Figure 2. Conversion of physical defect data to topological location of a bit failure.

Figure 2a. Top: Physical wafer map from inspection sys-

Figure 2b. Top: BitPower’s wafer level bitmap viewer shows the location

tem. Bottom: Exploded view showing die level defects.

of the electrical failures. Bottom: BitPower’s die/sub-die level bitmap viewer lets the user precisely locate the positions of failing bits and to view failing patterns at the bit level.

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Failing bit patterns vary by product. Circuit design, circuit layout, and process technology all play a part in determining the likely patterns that occur in a memory array. The BitPower system allows the user to create custom pattern descriptions for each device type.

The final step: Automated analysis

Once extracted, the failed bit patterns are transmitted to the Klarity automated yield analysis system for further analysis and correlation to defect data obtained from inspection points. Klarity accepts the bitmap data from the BitPower Analysis System as it would from other data sources within a fab. The bitmap data can be incorporated into Klarity’s unique Decision Flow Analysis recipes for automated monitoring and analysis (figure 3).

For example, recipes can be generated according to userdefined criteria to automatically trend failed bit classifications, identify repeating failure patterns, identify bit

failure excursions and send notification of such excursions to interested parties in the fab automatically.

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The combination of BitPower data and in-line inspection Figure 3. Regular monitoring of failed bit patresults provides terns extracted with BitPower can identify outKlarity with of-control conditions. powerful information required to determine the relationship between in-line defectivity determined earlier in the process/line, and bit failure patterns extracted by BitPower from electrical tests at the end of the process. Based on correlation results, Klarity’s built-in use of conditionals and filters allows selected wafers from a lot to be sent for further SEM review or failure analysis.

This helps faster identification of the process zones contributing to yield loss, improves failure analysis efficiency and accelerates resolution of the yield problem.

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as single-bit failures, word-line failures, bit-line failures, etc. Each of these patterns provide clues to the potential cause of the failure at specific process steps. For example, a paired bit failure may be indicative of a missing field oxide or a failing word-line could be indicative of missing contacts.

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