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Inspection Implications of a Design-Rule Shrink by Mark Keefer, Technical Marketing Manager
The current semiconductor business environment has caused most semiconductor manufacturers to postpone new fab construction or expansion of existing fabs. However, competitive pressures require improved, more cost-effective manufacturing processes. One way to achieve higher revenue is to produce more die per wafer. As the transition to 300 mm wafers is delayed, alternative approaches to increase the number of die per wafer are occurring: decreasing the design rule of the circuits (linewidth “shrinks”) and product redesign (compaction). Two benefits can be realized — the increased circuit density results in increased capacity (number of die per wafer start), and shrinks can also improve device performance, which allows higher average selling prices. Shrinks are cost-effective since they do not require an entirely new processing equipment set (except photolithography). As minimum feature sizes shrink, IC manufacturers face an increasing challenge to maintain and increase wafer yields and chip performance. New process technologies may have implications for the existing metrology and inspection equipment. Since smaller feature sizes are susceptible to electrical faults induced by smaller defects, defect inspectors must become more sensitive. Cost-effectiveness can be achieved in part by extending existing capabilities, rather than investing in a completely new equipment set. Defect inspection systems and strategies are changing to support shrinking design rules, and to accommodate new technologies or materials, as well as increased financial considerations. In-process wafers have more die per wafer and, therefore, higher value, requiring optimal defect inspection and sampling plans to decrease the amount of product at risk due to an undetected yield excursion. Processing and defect inspection trends of linewidth shrinks
The 0.5 to 0.35 µm process shift is characterized by adoption of oxide CMP processing and use of i-line lithography on critical layers. Global planarization by CMP is an enabling technology for the transition to 0.35 µm and below linewidths. The flatter wafer surface enables finer resolution of device features by reducing the stepper
depth of focus requirement. However, new yield-limiting defect types introduced by the oxide CMP process include residual slurry, microscratches, and surface voids. The 0.35 to 0.25 µm process shift is characterized by adoption of tungsten CMP steps, use of DUV lithography, new inter-layer dielectric (with low dielectric constant k) and interconnect materials, and shallow trench isolation replacing LOCOS for tighter packing density. Additional defect types introduced by the metal CMP process include residual tungsten (puddles or stringers), recessed or cored plugs, and metal dishing and oxide erosion. The use of anti-reflective layers results in other new defect types such as pinholes. Inspection trends include the initial use of patterned wafer tool monitoring (reduced use of unpatterned monitor wafers), and initial use of automatic defect classification (ADC) in production. The 0.25 to 0.18 µm process shift will probably incorporate an unprecedented number of material and processing changes. It will likely see some combination of Cu interconnects and low k dielectric materials in a dual damascene architecture that replaces metal etch Autumn 1998
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and oxide CMP with oxide patterning and metal CMP low energy implants for ultra-shallow junctions, and step-and-scan DUV lithography coupled with resolution enhancement techniques. The increased value of wafers in process may alter inspection strategies. More fabs will adopt patterned wafer tool monitoring and, also, introduce photolithography cell monitoring to provide high sensitivity inspection and rapid feedback.
illumination rather than monochromatic reduces the effects of color variation resulting from thickness variation. Not only does this result in increased defect capture rate with lower nuisance defect counts, but it also results in more robust wafer alignment. In some cases, the reduction in color variation results in sufficiently increased defect capture rate that a larger pixel size can be used for inspection, increasing system throughput and lowering cost of ownership1.
mented by integrated classification and analysis tools that quickly convert defect data into corrective actions. IMPACT/ Online™ ADC, in production use, aids in process characterization and rapid identification of process excursions. Defects are classified quickly and accurately, and the results are sent to defect data management systems such as Quest/ Klarity for defect clustering, layer analysis, defect type trending, and SEM review sample selection. ADC greatly surpasses the speed
TDI Digitized Image
Segmented Image
Inspection technology enhancements
Many of the new processes in use today, such as CMP, result in new defect types. Killer defects must be detected with high confidence, which requires a clear distinction between defect signals and “noise” induced by process variations, such as film thickness variation and grain structure. Brightfield imaging inspection systems compare grayscale intensity levels from cell-tocell or die-to-die and interpret differences as possible defects. Color variations that result from film thickness variation result in a change in gray-scale levels. This noise reduces the sensitivity of the inspection system by raising the minimum threshold level required to interpret a difference as a defect. Metal grain structures have the same effect: creation of additional noise, potentially resulting in nuisance defects. Laser scattering systems also rely on detecting differences between die-to-die comparisons. Process variations that are unaccounted for result in having to set the detection thresholds higher, reducing inspection sensitivity. Inspection system technology has been developed to reduce the effects of process noise on the inspection process. Two key improvements are ultra-broadband brightfield illumination and Segmented AutoThreshold (SAT). Using broadband 26
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Figure 1. The SAT algorithm segments the different images used in die-to-die processing based on the mean and range value of each pixel. In the above example, two segments are used.
SAT is an image processing technique for die-to-die (random mode) inspections that increases sensitivity on wafers with grainy metal and color variations typically seen in CMP processes. SAT algorithms partition the wafer image into multiple segments based on mean and range pixel values for each pixel (figure 1). Then, a different threshold value is applied to each segment, and the threshold value is dynamically adjusted during the inspection. Lower thresholds are applied to areas with lower noise, maximizing defect capture while reducing nuisance defect counts. In a metal etch inspection on grainy metal, the use of SAT to suppress nuisance defects resulted in several times higher defect capture as compared to non-SAT inspection2. High capture of all yield-relevant defect types alone is not enough. Defect detection must be comple-
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and accuracy of manual classification, and defect trending by defect type reveals excursions missed when trending by total random defect count alone3. As linewidths shrink, smaller inspection pixels are used (since yield-limiting defects are smaller), and trending by defect type (rather than total defect count) reduces the number of lots at risk4. The ADC system uses brightfield image processing algorithms similar to the inspection equipment, so the defects can be re-detected in spite of image differences introduced by CMP color variations. Patterned wafer tool monitoring
Defect inspection can be broadly divided into three categories: process line monitoring, process equipment monitoring, and engineering analysis applications. Process line monitoring typically
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uses high-resolution brightfield imaging systems on product or short-loop patterned test wafers. Equipment or tool monitoring typically uses darkfield laser scattering inspection of unpatterned monitor wafers. An opportunity exists for cost reduction in the equipment monitoring area by inspecting product wafers. The National Technology Roadmap for Semiconductors (NTRS) calls for a reduction in test wafers from 33 to 28 percent for the 0.25 µm to 0.18 µm technology generation5. Benefits of patterned wafer equipment monitoring are a more accurate representation of the true process (shows process integration failures), cost savings by reduction of monitor wafers, and the ability to use the same inspections for device monitoring, which aids in defect source analysis and yield prediction6. Patterned wafer tool monitoring also reduces process excursion detection time, reducing the amount of product at risk — an important consideration for highvalue wafers. Tool monitoring can also improve process equipment overall equipment effectiveness (OEE), by optimizing the time between preventive maintenance.
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The majority of capital investment in a linewidth shrink is in photolithography. Benchmarking the defectivity of new lithography technology is essential for fast yield ramps. The critical defects scale with the design rule, requiring high sensitivity inspection. Defect evaluation for a new lithography process on product wafers is difficult due to pattern complexity, previous layer defects and process noise; and it becomes more difficult with each successive mask layer. Back-end layers with multi-level metallization and CMP thickness variations exacerbate the problem. Use of a shortloop photo cell monitor (PCM) wafer avoids these issues. Silicon wafers are fully processed through the photo cluster — coat/expose/ develop — using the same process conditions (resist and design rules), except that stepper focus and exposure settings are optimized for baresilicon wafers. Photo cell monitors can be inspected with high sensitivity, due to low process and substrate noise, allowing higher defect capture than is possible on after-develop inspection (ADI) production wafers. High-resolution brightfield
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inspection (small pixel size) is able to detect photo defects such as developer spots that are low topography and/or have subtle color variations. The advantage of a photo cell monitor, compared to individual photo tool monitors, is that inspection time is significantly reduced and fewer wafers are required. Sampling frequency can be determined statistically, based on the number of excursions detected. Application of this technique has recently been described7. Impact of product mix on inspection systems
With the decline in DRAM prices due to overcapacity, many semiconductor memory manufacturers are diversifying their product mix to include logic devices to achieve higher profitability. Given the costsensitive nature of DRAM manufacturing, inspection systems dedicated to inspection of memory arrays were developed that offer cell-to-cell (array mode) inspection only, with a reduced selection of pixel sizes. Logic products have large areas of the die that are not repetitive cells, requiring the use of die-to-die (random mode) inspections for complete die coverage. Logic product design has been driven by interconnect complexity, leading to multiple levels of metal and the use of CMP as the global planarization technique. Inspection of logic devices and/or devices processed using CMP benefits from die-to-die mode and suppression of process noise using techniques such as broadband illumination and SAT algorithms. Importance of fast yield ramping
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Year Figure 2. Each new device generation requires that yield ramps become steeper and probe yields at transfer from pilot line to production become higher. (Source: VLSI Research)
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Controlling and reducing defect levels becomes more important as linewidths decrease, for both development and production. Delays in finding and solving defect problems during development can delay the
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Revenue lost = $32 M 6 months Learn rate/month = 24%
Revenue lost = $403 M 18 months Learn rate/month = 9%
ENTITLEMENT YIELD: Do = 1.60/cm2
55% ( N D P W )
Revenue lost = $161 M 12 months Learn rate/month = 13%
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ASP/Wafer [@ present Do] = $5,800 Wafer starts/month = 0.3K to 10K (12 months)
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Wafer Dia = 200 mm Die area = 1.63 cm2
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YIELD MODEL: SEEDS (α = 1.0) T I M E
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Figure 3. Achieving competitive yield learning rates can potentially save hundreds of millions of dollars.
product transfer to manufacturing. Figure 2 shows the importance of yield ramping as a competitive advantage. As the industry moves to the next linewidth generation, both the initial production yield and the yield ramping rate are critical, especially as DRAM profitability has fallen severely8. Yield modeling illuminates the significant dollar savings that can be achieved with a fast, successful yield ramp (figure 3). Key to rapid yield improvement is the rapid identification of yieldlimiting systematic and random defects, so that engineering resources can focus on fixing problems.
die per wafer, and to increase product performance. With each technology generation, it becomes more important to achieve high yields quickly and sustain yield in manufacturing to ensure profitability. Processing changes associated with linewidth shrinks may require inspection system enhancements such as broadband illumination, SAT, and ADC to extend the life of inspection solutions. The increased value of each in-process wafer may force rethinking inspection strategies, such as adopting patterned wafer tool monitors or implementing photo cell monitors. 1 Metteer, B. et al, “TI MSTC/DP1 Evaluation of
Summary
Semiconductor manufacturers are decreasing design rules to reduce fabrication costs by producing more
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the KLA-Tencor 2138”, proceedings of KLA-Tencor Yield Management Seminar, Austin, TX, 1997. 2 Garver, J., Keefauver, K., Tinker, M., Improved
Defect Detection Performance at Metal and Contact Etch Levels Using a New, Optical
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Comparison, Segmented Auto-Threshold Technology, SPIE Vol. 3050, pp. 452-463, 1997. 3 Breaux, L., Kolar, D., “Automatic Defect
Classification for Effective Yield Management”, Solid State Technology, Vol. 39 No. 12, pp. 89-96, 1996. 4 Shanthikumar, G., “Sequential and Bypass ADC
Sampling Models”, KLA-Tencor SEMICON/ West ADC Workshop, San Francisco, CA, 1998. 5 The National Technology Roadmap for
Semiconductors, Semiconductor Industry Association, San Jose, CA, pp. 117, 1997. 6 Jackson, J. and Usry, W., “Inspection of Etch
Layers and Patterned Wafer Tool Monitoring With the AIT”, proceedings of KLA-Tencor Yield Management Solutions Seminar, San Francisco, CA, 1998. 7 Phan, K. et al, A Methodology for the
Optimization of an I-line Lithographic Process for Defect Reduction, SPIE Vol. 3332, pp. 309-320, 1998. 8 Peters, L., “Speeding the Transition to 0.18 µm”,
Semiconductor International, Vol. 21 No. 1, pp. 61-70, 1998.
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