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Inspection Implications of a Design-Rule Shrink by Mark Keefer, Technical Marketing Manager
The current semiconductor business environment has caused most semiconductor manufacturers to postpone new fab construction or expansion of existing fabs. However, competitive pressures require improved, more cost-effective manufacturing processes. One way to achieve higher revenue is to produce more die per wafer. As the transition to 300 mm wafers is delayed, alternative approaches to increase the number of die per wafer are occurring: decreasing the design rule of the circuits (linewidth “shrinks”) and product redesign (compaction). Two benefits can be realized — the increased circuit density results in increased capacity (number of die per wafer start), and shrinks can also improve device performance, which allows higher average selling prices. Shrinks are cost-effective since they do not require an entirely new processing equipment set (except photolithography). As minimum feature sizes shrink, IC manufacturers face an increasing challenge to maintain and increase wafer yields and chip performance. New process technologies may have implications for the existing metrology and inspection equipment. Since smaller feature sizes are susceptible to electrical faults induced by smaller defects, defect inspectors must become more sensitive. Cost-effectiveness can be achieved in part by extending existing capabilities, rather than investing in a completely new equipment set. Defect inspection systems and strategies are changing to support shrinking design rules, and to accommodate new technologies or materials, as well as increased financial considerations. In-process wafers have more die per wafer and, therefore, higher value, requiring optimal defect inspection and sampling plans to decrease the amount of product at risk due to an undetected yield excursion. Processing and defect inspection trends of linewidth shrinks
The 0.5 to 0.35 µm process shift is characterized by adoption of oxide CMP processing and use of i-line lithography on critical layers. Global planarization by CMP is an enabling technology for the transition to 0.35 µm and below linewidths. The flatter wafer surface enables finer resolution of device features by reducing the stepper
depth of focus requirement. However, new yield-limiting defect types introduced by the oxide CMP process include residual slurry, microscratches, and surface voids. The 0.35 to 0.25 µm process shift is characterized by adoption of tungsten CMP steps, use of DUV lithography, new inter-layer dielectric (with low dielectric constant k) and interconnect materials, and shallow trench isolation replacing LOCOS for tighter packing density. Additional defect types introduced by the metal CMP process include residual tungsten (puddles or stringers), recessed or cored plugs, and metal dishing and oxide erosion. The use of anti-reflective layers results in other new defect types such as pinholes. Inspection trends include the initial use of patterned wafer tool monitoring (reduced use of unpatterned monitor wafers), and initial use of automatic defect classification (ADC) in production. The 0.25 to 0.18 µm process shift will probably incorporate an unprecedented number of material and processing changes. It will likely see some combination of Cu interconnects and low k dielectric materials in a dual damascene architecture that replaces metal etch Autumn 1998
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