Magazine autumn99 newcmp

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New CMP Challenges for Unpatterned Wafer Inspection at 130 nm

by Hubert Altendorfer, Senior Product Marketing Manager; Lionel Kuhlmann, Senior Research Scientist; Henrik Nielsen, Senior Staff Electrical Engineer; and Mark Nokes, Principal System Design Engineer

Chemical Mechanical Polishing (CMP) has quickly become the standard planarization method in IC manufacturing.

However, for CMP to continue to mature and become a viable process for the 0.13 µm generation, it is important to look at some factors that may affect the CMP process such as variations in wafer surface topography. Currently, traditional wafer flatness criteria are used to manage the depth of focus budget in the lithography process. Additional flatness requirements are emerging, demanded by the use of CMP in the early stages of device manufacturing. Topography variations on unpatterned wafers in the nanometer range have shown to adversely affect post CMP uniformity of dielectrics. An automated, high-speed inspection solution is needed to control the wafer quality used for these devices. This paper will discuss how surface topology could affect IC devices and introduce a solution for such a future inspection step.

CMP and surface topography

Depositing a thin dielectric layer onto a wafer that exhibits surface topology variations results in a non-uniform film thickness after the CMP processing (figure 1). This non-uniformity leads to resistivity variations resulting in lower performance devices and eventually to a complete device failure.

Therefore, stringent control of starting material for these small topology variations has to be established. Traditional flatness tools neither have the spatial resolution or the vertical sensitivity to measure these features. A fairly sensitive piece of equipment that has been used thus far is known as the “Magic Mirror” revealing very small slope variations on the surface. While the Magic Mirror instantaneously produces an image of the full surface of the wafer, the results are seldom quantitative for magnitude and extent of a feature, which are critical parameters to assure that the wafers are within the specification limits.

The surface topology contains all the information of the deviations of a real surface from an ideal reference. The spatial frequency 20

Autumn 1999

Yield Management Solutions

range detected by scattered light depends on the optical configuration and usually collects the signal of surface features with very high spatial frequency. Darkfield optics can collect high spatial frequencies but are insufficient for features that exhibit lower spatial frequency.

On the other hand, brightfield optics can detect the lower spatial frequencies required to characterize surface topology.

PreCMP

PostCMP

Dielectric layer

Si

Si

F i g u re 1. Dielec tric film thickness variation s a fter CMP due to sur f a c e t o p o l o g y.

A viable solution

The KLA-Tencor Surfscan SP1 platform, with its second-generation brightfield capability (SNT™ – Surface NanoTopography), can provide quantified results

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F i g u re 2. Surfscan SP1 SN T height map.

F i g u re 3. HRP-200 pro f i l e r.

of the wafer surface topography with nanometer height resolution at exceptionally high throughput. A critical item for success is to provide distortion free wafer handling during the measurement. Small forces at any part of the wafer will introduce artifacts to the measurement.

The SP1 incorporates a proprietary edge handling design that enables distortion-free wafer handling at all times.

The SP1 Surface NanoTopography design allows orientation-independent capture of large features. These features can be up to several millimeters with only a few nanometer height. Figures 2, 3 and 4 compare surface topography maps produced by the Surfscan SP1’s SNT feature to those from the HRP-200 profiler and a Magic Mirror, respectively. The results clearly show very good correlation with equivalent sensitivity for these long spatial wavelength defects on the Surfscan SP1.

Compared to the Magic Mirror, the Surfscan SP1 with SNT has the added benefit of quantifying the surface topology.

The quantifiable result from the Surfscan SP1 allows grading of the wafers based on user definable criteria.

The final result presents the number of defects above a specified height and total surface area covered by these defects.

Conclusion

It is essential that variations in wafer surface topology be detected as design rules move towards 130 nm.

This will require a broad range of spatial wavelengths extending from particles to surface site flatness. As mentioned earlier, detecting the different defect types requires the use of several methodologies. These have been combined in a single instrument, the Surfscan SP1.

The SP1 can rapidly and non-destructively inspect wafers up to 300 mm. It meets the challenge of reliably

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F i g u re 4. Magic Mirror im age.

detecting particles in the 60 nm range, can separate crystal originated pits (COPs) from particles and measure surface topology in the nanometer height range.

The Surfscan SP1 offers a comprehensive inspection strategy for CMP challenges at 130 nm design rules. ❈ cir cle RS#013

P a n e l

D i s c u s s i o n

“Semiconductor Technology Challenges for CMP” (in conjunction with the 196th Meeting of The Electrochemical Society) Thursday, October 21, 1999 5:00 PM The objective of the panel discussion is to evaluate current state-of-the-art and predict the future requirements and the review the readiness of the industry at large.

Panelists representing lithography, capital equipment sector, technology integration, CMP and process consumable segments of the industry will be present to lead the discussion. Companies represented include KLA-Tencor, Intel, Motorola, and other leading semiconductor manufacturers.

196th Meeting of The Electrochemical Society, Inc. Honolulu, Hawaii October 17-22, 1999 Hilton Hawaiian Village

For more details, visit www.electrochem.org/meetings.html