Magazine spring00 lowk

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Cover

Story

THE CHALLENGE

OF

LOW

κ

Issues and Considerations for Accelerated Per formance by Peter Nunan, KLA-Tencor Corporation

Introduction

A review of Moore’s law shows that throughout the 1980’s the information handling capacity of integrated circuits doubled every 18 months. During the 1990’s, the pace was accelerated even further. The shrinking of circuit dimensions has been the primary driver behind this pace of development for over 15 years. It is becoming clear, however, that as lithography challenges continue to increase, the introduction of new materials will play a much larger role in allowing the semiconductor industry to keep pace with Moore’s law. In recent years interconnect performance has played an ever increasing role as a predictor of overall circuit performance. RC delay, capacitance, crosstalk/noise margin, and voltage drop are some of the major considerations during the design of high performance interconnect architecture. The primary avenues that are being explored for enhanced interconnect performance are the use of low resistivity interconnects, namely copper, and the use of interlevel dielectric materials with a low dielectric constant. Judging from recent production ramps and manufacturer roadmaps, it is clear that the transition to the adoption of copper in place of aluminum as the interconnect material is well ahead of a similar transition being made from SiO2 to low κ dielectrics. This article focuses on some of the challenges facing IC manufacturers and equipment suppliers as the industry moves towards the adoption of low κ interlevel dielectrics. Achieving higher performance

As noted, the demand for higher frequencies and overall performance of ULSI circuits has prompted extensive development of low κ (defined as κ< 3.0) interlevel dielectric. Interconnect scaling has been shown to have significant impact on overall performance due to its ability to reduce interlevel capacitance. Figure 1 shows that as line width decreases, the line to line capacitance begins to dominate the total capacitance of the circuit.1 In the most general terms, the dielectric constant is related to capacitance by the expression C = εεoA/d, where εo = permitivity of free space, ε = dielectric constant of interlevel dielectric, A = the area of the capacitor, d = distance between capacitor plates. Reducing the interlevel capacitance results in a reduction in crosstalk and an increase in signal propagation speed. In the extreme submicron regime, where resistance and capacitance parasitics begin to dominate circuit performance, the expression RC = 2ρεεo(4L2/P2 + L 2/T2) is used to describe interconnect delay2, where ρ = interconnect resistivity, εo = permitivity of free space, ε = dielectric constant of interlevel dielectric, L = interconnect length, Spring 2000

Yield Management Solutions

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