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THE CHALLENGE

OF

LOW

κ

Issues and Considerations for Accelerated Per formance

by Peter Nunan, KLA-Tencor Corporation

Introduction

A review of Moore’s law shows that throughout the 1980’s the information handling capacity of integrated circuits doubled every 18 months. During the 1990’s, the pace was accelerated even further. The shrinking of circuit dimensions has been the primary driver behind this pace of development for over 15 years. It is becoming clear, however, that as lithography challenges continue to increase, the introduction of new materials will play a much larger role in allowing the semiconductor industry to keep pace with Moore’s law.

In recent years interconnect performance has played an ever increasing role as a predictor of overall circuit performance. RC delay, capacitance, crosstalk/noise margin, and voltage drop are some of the major considerations during the design of high performance interconnect architecture. The primary avenues that are being explored for enhanced interconnect performance are the use of low resistivity interconnects, namely copper, and the use of interlevel dielectric materials with a low dielectric constant. Judging from recent production ramps and manufacturer roadmaps, it is clear that the transition to the adoption of copper in place of aluminum as the interconnect material is well ahead of a similar transition being made from SiO2 to low κ dielectrics.

This article focuses on some of the challenges facing IC manufacturers and equipment suppliers as the industry moves towards the adoption of low κ interlevel dielectrics.

Achieving higher performance

As noted, the demand for higher frequencies and overall performance of ULSI circuits has prompted extensive development of low κ (defined as κ< 3.0) interlevel dielectric. Interconnect scaling has been shown to have significant impact on overall performance due to its ability to reduce interlevel capacitance. Figure 1 shows that as line width decreases, the line to line capacitance begins to dominate the total capacitance of the circuit.1 In the most general terms, the dielectric constant is related to capacitance by the expression C = εεoA/d, where εo = permitivity of free space, ε = dielectric constant of interlevel dielectric, A = the area of the capacitor, d = distance between capacitor plates. Reducing the interlevel capacitance results in a reduction in crosstalk and an increase in signal propagation speed. In the extreme submicron regime, where resistance and capacitance parasitics begin to dominate circuit performance, the expression RC = 2ρεεo(4L2/P2 + L 2/T2) is used to describe interconnect delay2, where ρ = interconnect resistivity, εo = permitivity of free space, ε = dielectric constant of interlevel dielectric, L = interconnect length, Spring 2000

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introduction of low κ materials is becoming a necessity as operating voltages decrease and frequencies increase. In addition, the introduction of low κ materials can limit the number of metal layers in an architecture, thus reducing production costs and overall cost of ownership.

The evolution of low

F i g u re 1: Intercon nect capaci tance begins to domi nate tot al circuit cap acitance in the deep s u b m i c ron re g i m e . 1 1

P = interconnect pitch, T = interconnect thickness. From this expression, it is clear that reducing the dielectric constant of the interlevel dielectric will improve interconnect delay, as well as reduce AC power dissipation (power = CV 2f).

Although low κ materials have been targeted for the performance market and the reduction of interconnect crosstalk, the need to reduce bit line capacitance is driving memory chip designers to begin designing low κ dielectric materials into their advanced devices as well. Since devices are more susceptible to cross talk at lower voltages and inductive coupling becomes more of an issue at higher operating frequencies, the

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In pursuit of a reduction in RC delay, IC manufacturers have taken two different approaches. Many leading edge companies have either stayed with aluminum interconnect, introducing a low κ material as the interlevel gapfill dielectric (fluorinated oxides or silsesquioxanes), or they have introduced copper and continued their use of a conventional SiO 2 dielectric.3,4 The addition of fluorine to an SiO2 matrix reduces the dielectric constant from 4.2 (SiO2) into the 3.5-3.7 range by reducing the effective polarizability and increasing the free volume of the material. In contrast, the introduction of copper in place of aluminum allows thinning of the interconnect (thus reducing the area of the capacitor) while retaining the overall line resistance.

Although both approaches are currently in volume production and have been an effective means of achieving higher circuit performance, it is clear that merging copper with low κ materials will be necessary for further improvement.

Table I: Effective dielectric constant roadmaps generated by the ITRS committee for 1997 and 1999.

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The introduction of copper with fluorinated oxides is expected to be in volume production by several IC manufacturers in early 2000 at the 0.15 µm node.

The next step will be the introduction of lower κ materials (κ < 3.0) in conjunction with copper. This combination will be the source of the greatest challenges. The development and integration of low κ materials has already been more difficult than originally expected. These challenges have already been evidenced by modifications made to the 1999 International Technology Roadmap for Semiconductors as compared with the 1997 version. Table I5 shows that while the 1997 roadmap projected the implementation of low κ materials in the 2.5-3.0 range at the 180 nm node, the 1999 version shows the use of low κ materials in the 3.5-4.0 range at the same node.

A similar difference between the 1997 and 1999 roadmaps exists at the 150 and 130 nm nodes.

Interestingly, the two roadmaps converge at the 100 nm node, projecting the implementation of materials with κ values in the sub-2.2 range.

This indicates that the ITRS committee believes that the semiconductor industry must get back on track with the earlier versions of the roadmaps, if performance trends are to meet expectations.

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fundamentals

In order to comprehend the integration challenges associated with low κ materials, it is important to have an understanding of the fundamental nature of these materials. Many low κ materials show a decrease in κ at increasing frequencies.6 The variation in the dielectric constant is attributed to the frequency dependence of the polarization mechanisms that contribute to the dielectric constant.

The magnitude of the dielectric constant is dependent upon the ability of the material to orient to the oscillations of an alternating electric field. As shown in Figure 2, there are

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three components (electronic, atomic and dipolar) which contribute to the polarization of a material. At optical frequencies (1014 Hz), only the lowest mass species, electrons, are efficiently polarized. At lower frequencies, atomic polarization of heavier, more slowly moving nuclei also contribute to the dielectric constant.

Atomic polarization of induced dipoles can occur in the infrared (1012 Hz) or lower frequency regimes.

Dipole polarization is the redistribution of charge when a group of atoms with a permanent dipole align in response to the electric field. In the solid state, alignment of permanent dipoles requires considerably more time than electronic or atomic polarization, occurring at microwave (109 Hz) or lower frequencies.6 The polarizability, and thus dielectric constant, of each species is generally additive (i.e., electronic + atomic + dipolar). At optical frequencies, where only electronic polarization occurs, the dielectric constant κ is related to the refractive index, n, by Maxwell's identity, κ = (n)2.6 The introduction of free volume in a material decreases the number of polarizable groups per unit volume resulting in lower values for the atomic and dipolar contributions.

The addition of fluorine and/or carbon to a material can reduce κ in two ways. First, F and C provide the material with an inherently lower electronic polarizability. Second, both F and C force the material matrix to “open up”, introducing free volume into the structure. The next step in reducing the dielectric constant of materials is the addition of air, or porosity, to the matrix.

Introducing air, which has a κ =1, to the matrix is the most effective way to lower the dielectric constant. The drawback to this technique is that with the lower dielectric constant of air comes the mechanical properties of air, which are less than favorable for building integrated circuits.7 The addition of porosity to materials is particularly challenging and is

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typically reserved for materials targeted for κ < 2.2.

Material fundamentals

Generally, materials with κ < 3.0 fall into three categories: organic, inorganic, and hybrid materials (organosilicates). There are many types of materials currently under investigation as potential substitutes for SiO2 at the 0.13 µm generation and beyond as shown in Table Ia. Some of the most popular of these are listed by trade name in Table IIb. The typical IC manufacturer will investigate a number of materials closely as part of a low κ evaluation. Table III lists many of the mechanical and electrical properties to be considered, as well as measurement methodologies currently employed.8 The two deposition techniques being most strongly investigated are chemical vapor deposition (CVD) and spin-on deposition using track technology. The deposition parameters vary significantly, depending upon the precursor being used. Some CVD processes use plasma while others utilize a condensation reaction.

Although most spin-on processes employ a low temperature bake (~250°C) to remove solvent, combined with a higher temperature cure (~400°C) to build the material network, they vary considerably in the process details.

F i g u re 2: Schematic showing the nature of the e l e c t ron ic, atomic, and dipolar con trib utions to material pol ari zation. 6

Due to their hydrophobic properties and reduced polarizability, organic materials typically have a lower dielectric constant at equivalent porosity’s than do inorganic materials. However, inorganic materials, because they retain an SiO2-like matrix, generally are integrated more easily into existing SiO2 type processes.

Hybrid materials are typically materials with C doping of an SiO2 matrix.7 The idea is to gain some advantages from both the organic and inorganic regimes. Once the base material is selected (organic, inorganic, or hybrid), the next step in reducing the dielectric constant is the addition of porosity to the films.

With the exception of PTFE films developed by W.L. Gore, nearly all

Table II: Many of the types of low κ mat erials under i nvestigation, a s well as their re s p e c t i v e deposition met hods, are shown in (a).

Tra de names of s ome of the mos t a ggressively pursued

mater ial s are s hown in (b).

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cern to the IC manufacturer, and how they impact dual damascene integration.

Integration complexities

As noted above, integration of low κ materials poses a particular challenge for the IC manufacturer. At the 0.13 µm node, the issues of copper fill, etch selectivity, and barrier integrity will continue to be a challenge and will require significant process development. 10 The addition of low κ materials further complicates the integration equation. Issues related to the thermal, mechanical, and adhesive integrity of low κ films need to be addressed.

Table I II: Ma ter ial p ro p e r ties which are typic ally evaluated, and th e analysis method ologies which a re employed.

materials under investigation with a κ < 2.2 incorporate some porosity.

With a dielectric constant in the 2.0 range, the Gore material is the lowest full density material available.9 Although several techniques are being employed to add porosity to low κ films, currently all main stream porous materials are deposited using spin-on technology.

While the addition of porosity in a material succeeds in reducing the dielectric constant, the mechanical properties of the material, such as Young’s modulus, hardness, and fracture toughness, tend to suffer.

This is the dilemma facing the IC industry today — as κ decreases, so too does E, dropping to below acceptable limits as shown in Figure 3.

The primary requirements for porous films are that the modulus is 20

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In addition to the choice of low κ material to be implemented, there exist at least two important decisions that IC manufacturers will have to make in terms of low κ integration. First, either a single or dual damascene approach to building the Cu/Low κ architecture will need to be selected. 11 These two schemes are shown in Figure 5. The choice of single vs. dual damascene is one of cost versus ease of integration.

While single damascene eases some of the processing issues associated with dual damascene (most specifically patterning and Cu fill processes), the manufacturing cost will go up as a result of the additional processing steps required.

sufficient to withstand chemical mechanical planarization (CMP), that the pores are closed rather than open, and that the pore size is less than 10 percent of the minimum feature. The pore size is critical as larger pores are considered "killer pores" and can lead to significant reliability issues.

Overcoming the gap between material requirements and current material capabilities is a challenge that will require IC manufacturers and equipment/materials suppliers to work together. Figure 4 outlines some of the material properties F i g u re 3: A sch ematic re p resentation of the typical re l a t i o n s h i p which are of most con- between the modulus and the dielectric cons tant .

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rate of the low κ material.14

F i g u r e 4: Major i ssues and concern s with respect to the in tegration of l ow κ d ielectrics and Cu.

The second decision for IC manufacturers is whether to use the low κ material at both the via and the trench levels (homogeneous), or only at the trench level (embedded).

While the homogeneous approach may provide some integration advantages, the embedded approach may be more effective at reducing interconnect crosstalk due to a greater Cline-ground/Ctotal ratio.1 In addition, the embedded approach may provide better mechanical integrity and thermal conductivity than the homogeneous integration.

turable ash processes which utilize reducing chemistries. In terms of etch, organic low κ materials pose distinct concerns. It is important to have sufficient etch selectivity between the low κ material, the photoresist and the bottom etch stop layer. Photoresist faceting leads to via/trench blowout, while low selectivity to etch stop layers may lead to significant sputtering of Cu onto the via sidewall. The current challenge is that most etch processes which show a high selectivity to PR and ESL’s also have an unacceptable etch

Finally, wet cleans and solvent processes need to be developed which are compatible with low κ materials. Challenges at copper barrier and fill will be focused on high aspect ratio fill and the adhesive strength at the barrier/low κ interface. At CMP, the dishing of wide lines and erosion/scratching of the softer dielectric material will need to be closely scrutinized.

Reliability issues

While mechanisms for early failure continue to be studied extensively, the effect of low κ materials on long term reliability is only beginning to be studied. Excellent adhesion is required at the low κ/barrier interface, an area often considered the “Achilles heel” of devices built with low κ materials.13 Poor adhesion could create a fast diffusion path for copper along this interface. Many of the organic-containing low κ materials possess a high thermal coefficient of expansion (relative to

In selecting a low κ material and an integration approach, the IC manufacturer must consider a number of interrelated factors. The effect of etch stop and dielectric barriers on the effective dielectric constant must be weighed. As etch stop layers and cap oxides with higher κ values are added into the integration, the effective κ will increase due to the existence of fringing fields.12 Other considerations include the effective aspect ratio (single vs. dual damascene) and the potential for failing to clear and fill one of the millions of vias present in the circuit.

In choosing a low κ material, the effect of reactive etch and ash chemistries on the via/trench sidewalls are also important considerations. It has been shown that O2-based etch/ash processes can render low κ films hydrophilic, causing the κ value to increase significantly.13 Efforts are underway to develop manufac-

F i g u re 5: Schematic r e p resentation of sin gle vs. dual damascene i ntegration with Cu. 1

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the other materials in the system) which can cause high stress fields at the interface, leading to delamination and/or cracking.

Another major concern revolves around the thermal limitations of most low κ materials. The class of materials considered to be ultra-low κ typically have thermal conductivities that are much lower than SiO2.

This fact can result in extensive Joule heating of the interconnects under operating conditions. Since MTF ~ J-2exp(Q/kT), electromigration performance may suffer unless other methods are employed to dissipate heat from the interconnects.

In addition to these issues, the lower modulus, fracture toughness, and cracking thresholds of many of the low κ materials may require further development of packaging processes.

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Although circuit simulations give clear evidence that low κ materials are required for integrated circuit performance trends to continue, the challenges now apparent in the integration of these materials were initially underestimated. With a typical development cycle of three years, including materials characterization, pilot line integration, and tool purchases, leading edge IC manufacturers will need to make a dielectric decision for the 0.13 µm node in the very near future. By working to share information on the issues surrounding the choice of low κ materials and their integration, IC manufacturers and equipment suppliers can jointly help insure that these challenges do not prevent the industry from keeping up with the inexorable pace of Moore’s law.

References

Summary

The introduction and integration of low κ materials presents a significant challenge for both the IC manufacturer and the equipment industry.

Working together, manufacturers and equipment makers must ensure adequate solutions are in place to provide a smooth transition to this important technology. Methods are already being developed to measure the thickness of multilayered low κ stacks, surface roughness, the extent of cure, the water diffusion coefficient, pore size and connectivity, Young’s modulus, coefficient of thermal expansion, and fracture toughness.15,16,17,18 For example, the Quantox system from KLA-Tencor can be used for non-contact measurement of dielectric constant using Corona discharge methodology.19 Device yield and integration optimization of copper with low κ materials is also critical. Process control must be improved at CMP through in-line dishing/erosion metrology, at photo/ etch through inspection of high aspect ratio vias and sidewall striations, and at metallization through Cu void/delamination inspection. 21 22

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S.P. Jeng, R.H. Havemann and MiChang Chang., Advanced Metalization for ULSI Apps., 1994.

2. Mark T. Bohr, IEDM conf pro c e e dings, (1995), pg. 241.

3. J. Yota et al, Advanced Metallization for ULSI Applications, 1997, pg, 353.

4. S. Venkatesan et al, IEDM Conference Proceedings, (1997).

5. 1 9 97 a nd 1 99 9 S IA - I T RS Roadmaps.

6. J.O. Simpson and A. K. St. Clair, Fundamental insight in developing l ow k po l y im i d es , NAS A t ec h memo, NASA Langley Researc h C e n t e r.

7. A. Shiota, Low Density Low k Dielectrics, ACS Low κ w o r k s h o p concepts and needs of low k materials, Nov. 16,1999.

8. C. Case, The Evolution of Low k Dielectrics, ACS Low κ w o r k s h o p concepts and needs of low k materials, Nov. 16,1999.

9. B .N. Luc a s, C .T. Ro se nm ay er, W.C. Oliver, Mechanical Characterization of sub-micron PTFE Films, W.L. Gore publications Web Site.

1 0 . R. Elliot, Yield Management Solutions, Vol 2 Issue 1, Autum 1999, pg. C-26.

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1 1 . A. Singh et al, Electrochemical proceedings, Volume 97-8, 1997, pg.

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1 2 . R. H. Havemann, Mat. Res. Symp.

P roc., Vol. 511, 1998, pg. 3.

1 3 . R. Havemann, Process Integration Challenges for Cu and Low κ, ACS Low k w or k sho p -c onc e pts a n d needs of low k materials, Nov. 16,1999.

1 4 . I. More y, Review of Low κ D i e l e ctric Etching, ACS Low k workshopconcepts and needs of low k materials, Nov. 16,1999.

1 5 . A. Srivatsa et al, Measurement of Advanced Low κ Materials, Semiconductor Fabtech, 9th edition.

1 6 . K L A - Tencor applications note, FLX #4, V1.

1 7 . K L A - Tencor applications note, FLX #7, V1.

1 8 . KLA-Tencor applications note, PROF #2, V1.

1 9 . P.K.Roy et al, Electrochemical Soc. P roc., 97-12,280 (1997).

2 0 . A. Srivatsa and C.Ygartua, Pro c .

SPIE Vol. CR72, p. 61-77.

2 1 . Yield Management Solutions publ., Vol. 2 Issue 1, 1999, pg. C3-C28.

About the Author Peter D. Nunan V.P. Strategic Alliances KLA-Tencor Peter Nunan graduated from Lehigh University with a B.S. in Engineering Physics and M.S. in Electrical Engineering. He began his career in 1979 working on DRAM process development at AT&T (currently Lucent Technologies). He has been involved in all aspects of process integration during his career while working at Siemens, Sematech and ST Micro-electronics. He came to KLA-Tencor in 1998 to direct its strategic alliance activities. The author would like thank the following people for their contributions to this article: Bob Fiordalice, Anantha Sethuraman, Steve Oestreich and Manjunath Yedatore.