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Opening the Window to Higher Parametric Yield at 32 nm DFM and APC Strategies Tackle Process Window Limitations Kevin M. Monahan, KLA-Tencor Corporation © 2005 IEEE. Kevin M. Monahan, Enabling DFM and APC Strategies at the 32nm Technology Node. Reprinted, with permission, from International Symposium on Semiconductor Manufacturing (ISSM) 2005 Conference.

Most semiconductor manufacturers expect 193-nm immersion lithography to remain the dominant patterning technology through the 32-nm technology node. Even now, the interaction of more complex designs with shrinking process windows is severely limiting parametric yield. The industry is responding with strategies based upon design for manufacturability (DFM) and multi-variate advanced process control (APC). The primary goal of DFM is to enlarge the process yield window, while the primary goal of APC is to keep the manufacturing process in that yield window. This article discusses new and innovative process metrics, including virtual metrology, that will be needed for yield at the 32-nm technology node.

Introduction

Enabling DFM and APC strategies with metrology depends on innovation1. As a minimum, DFM will require feeding forward design intent, simulator output, layout clips, and design rule-check (DRC) hot spots to expedite setup of measurement tools. Current DRC and aerial image modeling at best focus and exposure conditions is increasingly unreliable. In the future, process windowaware approaches will require powerful full-chip simulators that can accurately predict and measure developed patterns in resist, along with accurate measurement feedback to calibrate the printability simulator.

To control development costs, the conversion of data to information, knowledge, and decisions must be taken as far upstream as possible.

On the process control side, implementing an APC strategy requires feeding forward both process context and measurement data.

In the future, we know that process context and measurement data must increase dramatically to support multi-variate control at the lot, wafer, field, die, and intra-die levels.

In addition, yield and performance losses 42

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are often caused by process integration issues or combinations of profile, shape, roughness2, thickness, and pattern placement errors. For these applications, new measurement types are required, creating a concomitant need to decrease the cost and increase the yieldrelevance of each measurement. In addition, combined dispositioning and parametric yield analysis will require data from multiple metrology tools.

New metrology requirements

The case for linking design, layout, mask, and wafer processes with metrology is compelling. Greater complexity is offset by the advantage of greater access to adjustment; an array of strategies generates higher return than just one. The increasing metrology needs of DFM and APC can be met by innovations in the measurement of pattern shape, profile, overlay, thickness, composition, and electrical properties. As an example, some of the key dependencies for device performance are given by the transistor drive current equation below:

( )

Id=1 W • ( e • µ) • ( V- V ) 2 t 2 L •T

Drive current at saturation depends on physical dimensions such as gate width W, gate length L, and gate oxide thickness T. It can limit the speed and, therefore,

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the average selling price of a device. Drive current also varies with electrical properties such as channel electron mobility µ, gate oxide dielectric constant x, and threshold voltage Vt. These, in turn, are affected by such factors as strain, composition, and transistor architecture. The following sections will explore innovations in physical dimension and pattern placement metrology.

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Figure 1: (a) Design-intent layout prior to simulation. (b) Noise-free SEM image simulation. (c) SEM image for comparison with layout.

From CD to Shape Metrology

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From CD to Profile Metrology

Scatterometry-based CD (SCD) metrology will evolve into more yield-relevant “profile metrology” and may become the reference tool for calibrating the CD SEM. SCD is able to accurately reproduce cross-section profiles imaged in a transmission electron microscope (TEM) (Figure 2a). The ability of SCD based on spectroscopic ellipsometry (SE) to accurately measure footing and notching at the base of gate structures has led to twofold improvements in correlation to electrical L-poly and drive current (Figure 2b). For this reason, SCD tools are currently displacing other metrology tools in feedforward APC applications from lithography to etch. In control applications for shallow-trench isolation (STI), significant cost savings have been realized by metrology convergence. SCD tools are currently displacing CD SEM, AFM profile, and SE film thickness tools for the control and monitoring of isolation (Figure 2c). The benefits are lower cost, shorter cycle time, and greatly reduced temporal, spatial, and technology de-correlation for the more performance-relevant compound measurements such as aspect ratio.

Scanning electron microscopy (SEM)-based CD metrology will evolve into more yield-relevant “shape metrology”. Measurements such as line-end shortening, miniFrom Scribe Line to In-chip mum gap, line roughness, and feature rounding will Traditional box-in-box (BiB) overlay metrology will be performed as commonly as standard CDs are today. evolve into more yield-relevant, grating-based overlay To decrease cost, multiple measurements will be made metrology (AIM). This will take measurement of pattern within the same image field to assess local pattern variation and provide robust averages for APC. OPC printability verification will be an increasingly critical DFM application for the SEM. Design-based metrology (DBM) will enable both APC and DFM strategies. Briefly, DBM is the use of design-intent and hot-spot information to define perfor B A mance-relevant measurement locations within a semiconductor device. A particularly powerful implementation3 is shown in Figures 1a-1c. It solves one of the most vexing DBM problems by simulating a noise-free SEM image from design input. The simulated image is then used for robust C pattern recognition and precise location of measurement Figure 2: (a) SCD profiles on TEM cross-sections. (b) SCD and SEM correlation to L-poly. (c) Simultaneous SCD sites. measurements on STI.

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Figure 3: (a) Traditional box overlay target. (b) Robust grating overlay target. (c) Small in-chip overlay target.

placement error to new levels of accuracy and enable combined CD and overlay dispositioning. At the 32-nm node, BiB overlay metrology (Figure 3a) will suffer from extreme process sensitivity, particularly with respect to reticle fabrication error, asymmetric deposition and etching, and chemical mechanical planarization (CMP).

Grating-based overlay technology (Figure 3b) can decrease process-induced measurement error by a factor of two. Remaining pattern placement error, including unmodeled intra-chip error, will be addressed with tiny in-chip grating targets4 (Figure 3b). These enable significant reduction of model residuals, the largest remaining source of overlay measurement error. In some cases, such small overlay targets may be combined with lineend-shortening (LES) targets that are used to monitor focus and exposure excursions in lithography cells. The benefits are lower cost per yield-relevant measurement and higher temporal, spatial, and technology correlation for rootcause analysis.

ment targets is critical; therefore, calibrated lithography models, such as PROLITH, will be employed to assist in the initial target optimization. These models must use realistic mask data and comprehend the most aggressive resolution enhancement technologies (Figure 4a).

Second, they must provide accurate results for immersion lithography at 193 nm (Figure 4b). Third, they must enable rigorous virtual metrology to supplement actual physical measurement (Figure 4c). The benefits are lower cost per measurement, inline validation of physical metrology, and upstream pattern analysis to reduce design, mask, and wafer-level yield loss.

Conclusions

This article identified four trends that address the metrology needs of semiconductor manufacturing at the 32-nm technology node. In particular, the focus has been on the physical parametric measurements that will enable future APC and DFM strategies. The key trends are: • The transition of the SEM from CD metrology to a more yield-relevant and cost-effective shape metrology utilizing critical design data.

• The transition of SCD from CD metrology to more yield-relevant profile metrology for gates, STI, sidewall spacers, and contact holes.

From Actual to Virtual Metrology

Traditional process modeling and simulation will evolve into yieldpredictive “virtual metrology”.

Even now, the measurement technologies discussed (SEM, SCD, and AIM) rely to some extent on simulation. Simulated SEM images assist with design-based pattern shape metrology. Rigorous coupled wave (RCW) algorithms generate libraries of ellipsometric spectra for comparison with actual SCD data. Overlay simulators5 predict the optical signatures of innovative overlay targets in order to maximize sensitivity and minimize response to process noise. Finally, robust printability of SEM, SCD, and AIM measure44

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C Figure 4: (a) Chrome-less phase mask structure. (b) Polarization simulation for I-193nm. (c) Calibrated virtual metrology simulation.

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• The transition of overlay metrology from box-in-box targets in the scribe line to more yield-relevant AIM grating targets inside the chip.

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References 1. K. Monahan and B. Trafas, SPIE Vol. 5756, 2005.

2. P. Leunissen, et al., SPIE Vol. 5752, 2005.

• The transition from actual to virtual metrology using calibrated process simulators, such as PROLITH and its derivatives.

3. L. Capodieci, et al., KLA-Tencor YMS West 2005.

Acknowledgements

5. L. Seligson, et al., SPIE Vol. 5752, 2005.

4. P. Leray, et al., SPIE Vol. 5752, 2005.

The author thanks Brian Trafas, Murali Narasimhan, Umar Whitney, John Robinson, Amir Azordegan, Gian Lorusso, Matt Hankinson, Ted Dziura, David Tien, Mike Adel, Chris Sallee, and Dan Wack for valuable inputs. © 2005 IEEE. Kevin M. Monahan, Enabling DFM and APC Strategies at the 32nm Technology Node.

Reprinted, with permission, from International Symposium on Semiconductor Manufacturing (ISSM) 2005 Conference.

Reticle Yield Management Seminar A valuable venue for innovative ideas

KLA-Tencor’s Yield Management Seminars (YMS) focus on the latest solutions and strategies for accelerating yield through critical technology transitions. Participants have the unique opportunity to learn and gather information from several leading experts in the field.

Date: Time: Location:

Monday, September 18, 2006 12:30-5:30 Monterey, California

Call for future papers

Papers should focus on using KLA-Tencor tools and solutions to enhance yield through increased productivity and performance. If you are interested in presenting a paper at one of our upcoming Yield Management Seminars, please submit a one-page abstract to: Nancy Williams by fax at (408) 875-4144 or email at nancy.williams@kla-tencor.com.

YMS at a Glance Date

Location

July 12

San Francisco, California

August

Singapore; Taiwan