Lithography M
e
t
r
o
l
o
g
y
Opening the Window to Higher Parametric Yield at 32 nm DFM and APC Strategies Tackle Process Window Limitations Kevin M. Monahan, KLA-Tencor Corporation © 2005 IEEE. Kevin M. Monahan, Enabling DFM and APC Strategies at the 32nm Technology Node. Reprinted, with permission, from International Symposium on Semiconductor Manufacturing (ISSM) 2005 Conference.
Most semiconductor manufacturers expect 193-nm immersion lithography to remain the dominant patterning technology through the 32-nm technology node. Even now, the interaction of more complex designs with shrinking process windows is severely limiting parametric yield. The industry is responding with strategies based upon design for manufacturability (DFM) and multi-variate advanced process control (APC). The primary goal of DFM is to enlarge the process yield window, while the primary goal of APC is to keep the manufacturing process in that yield window. This article discusses new and innovative process metrics, including virtual metrology, that will be needed for yield at the 32-nm technology node.
Introduction
Enabling DFM and APC strategies with metrology depends on innovation1. As a minimum, DFM will require feeding forward design intent, simulator output, layout clips, and design rule-check (DRC) hot spots to expedite setup of measurement tools. Current DRC and aerial image modeling at best focus and exposure conditions is increasingly unreliable. In the future, process windowaware approaches will require powerful full-chip simulators that can accurately predict and measure developed patterns in resist, along with accurate measurement feedback to calibrate the printability simulator. To control development costs, the conversion of data to information, knowledge, and decisions must be taken as far upstream as possible. On the process control side, implementing an APC strategy requires feeding forward both process context and measurement data. In the future, we know that process context and measurement data must increase dramatically to support multi-variate control at the lot, wafer, field, die, and intra-die levels. In addition, yield and performance losses 42
Spring 2006
Yield Management Solutions
are often caused by process integration issues or combinations of profile, shape, roughness2, thickness, and pattern placement errors. For these applications, new measurement types are required, creating a concomitant need to decrease the cost and increase the yieldrelevance of each measurement. In addition, combined dispositioning and parametric yield analysis will require data from multiple metrology tools. New metrology requirements
The case for linking design, layout, mask, and wafer processes with metrology is compelling. Greater complexity is offset by the advantage of greater access to adjustment; an array of strategies generates higher return than just one. The increasing metrology needs of DFM and APC can be met by innovations in the measurement of pattern shape, profile, overlay, thickness, composition, and electrical properties. As an example, some of the key dependencies for device performance are given by the transistor drive current equation below:
( )
Id=1 W • ( e • µ) • ( V- V ) 2 t 2 L •T
Drive current at saturation depends on physical dimensions such as gate width W, gate length L, and gate oxide thickness T. It can limit the speed and, therefore,