Magazine summer04 soi challenges

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SOI: Challenges and Solutions to Increasing Yield in an Ultrathin Age Christophe Maleville and George Celler, Soitec

Silicon-on-insulator (SOI) wafers are quickly making inroads into IC manufacturing, especially for chips destined for high-speed and/or low-power applications. Soitec has been manufacturing SOI wafers for more than ten years using our patented Smart Cut™ splitting and bonding technology. With our first high-volume factory (Bernin 1) in production since 1999 and our 300 mm factory in production since 2003, we have gained considerable manufacturing expertise that is relevant not only to us, but also to our customers. In this article, we’ll provide an introduction to SOI and related engineered substrates, and then examine some of the manufacturing challenges we have addressed to minimize defects and maximize yield. Finally, we will take a look at the yield challenges for upcoming generations of engineered substrates.

What is SOI?

In SOI-based IC manufacturing, traditional bulk silicon wafers are replaced by “engineered” substrates, which consist of multiple layers of substrate materials. The SOI wafer is a composite substrate with an active top monocrystalline silicon (Si) layer decoupled from the support wafer. It is the first example of an engineered substrate addressing mainstream MOSFET performance requirements. SOI now has a well-proven record. It makes a major impact on partially and fully depleted devices in terms of performance enhancement, reduction of leakage currents and power consumption, suitability for low voltage device architectures, and so forth. Soitec manufactures its Unibond™ brand of SOI wafers and other engineered wafers using its patented Smart Cut technology. Smart Cut is currently deployed commercially for SOI and strained silicon on insulator (sSOI). It has also been successfully demonstrated for many other major engineered substrates, which are scheduled for commercial release in concert with customer needs and the industry roadmap. 6

Summer 2004

Yield Management Solutions

Smart Cut is a revolutionary technique used to transfer ultrathin single crystal layers of wafer substrate material (such as silicon) onto another surface. Differing from traditional layer-transfer techniques, which are based mainly on wafer bonding and etch-back or epitaxial lift-off, the Smart Cut approach uses a thermal activation process as an “atomic scalpel.” It literally slices the wafer horizontally, lifting off a thin layer from the donor substrate and placing it onto a new substrate. Inherently, this process offers better control, and a single donor substrate can be reused many times for further layer transfers. The transferred layer thickness is predetermined by the cleavage zone created via ion implantation (of hydrogen, helium, argon, etc.). The implant energy is the primary factor determining the film thickness. After the layer transfer and bonding, the cleaved surface of the thin film is treated, annealed and polished to ensure a silicon film (in the case of SOI) and surface quality comparable to silicon prime wafers. SOI markets and roadmap

SOI wafer technology has reached maturity. But the demand for thinner and thinner films places new demands on the fabrication methods. At the same time


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