Magazine summer04 soi challenges

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SOI: Challenges and Solutions to Increasing Yield in an Ultrathin Age Christophe Maleville and George Celler, Soitec

Silicon-on-insulator (SOI) wafers are quickly making inroads into IC manufacturing, especially for chips destined for high-speed and/or low-power applications. Soitec has been manufacturing SOI wafers for more than ten years using our patented Smart Cut™ splitting and bonding technology. With our first high-volume factory (Bernin 1) in production since 1999 and our 300 mm factory in production since 2003, we have gained considerable manufacturing expertise that is relevant not only to us, but also to our customers.

In this article, we’ll provide an introduction to SOI and related engineered substrates, and then examine some of the manufacturing challenges we have addressed to minimize defects and maximize yield. Finally, we will take a look at the yield challenges for upcoming generations of engineered substrates.

What is SOI?

In SOI-based IC manufacturing, traditional bulk silicon wafers are replaced by “engineered” substrates, which consist of multiple layers of substrate materials. The SOI wafer is a composite substrate with an active top monocrystalline silicon (Si) layer decoupled from the support wafer. It is the first example of an engineered substrate addressing mainstream MOSFET performance requirements.

SOI now has a well-proven record. It makes a major impact on partially and fully depleted devices in terms of performance enhancement, reduction of leakage currents and power consumption, suitability for low voltage device architectures, and so forth.

Soitec manufactures its Unibond™ brand of SOI wafers and other engineered wafers using its patented Smart Cut technology. Smart Cut is currently deployed commercially for SOI and strained silicon on insulator (sSOI).

It has also been successfully demonstrated for many other major engineered substrates, which are scheduled for commercial release in concert with customer needs and the industry roadmap.

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Smart Cut is a revolutionary technique used to transfer ultrathin single crystal layers of wafer substrate material (such as silicon) onto another surface. Differing from traditional layer-transfer techniques, which are based mainly on wafer bonding and etch-back or epitaxial lift-off, the Smart Cut approach uses a thermal activation process as an “atomic scalpel.” It literally slices the wafer horizontally, lifting off a thin layer from the donor substrate and placing it onto a new substrate. Inherently, this process offers better control, and a single donor substrate can be reused many times for further layer transfers.

The transferred layer thickness is predetermined by the cleavage zone created via ion implantation (of hydrogen, helium, argon, etc.). The implant energy is the primary factor determining the film thickness. After the layer transfer and bonding, the cleaved surface of the thin film is treated, annealed and polished to ensure a silicon film (in the case of SOI) and surface quality comparable to silicon prime wafers.

SOI markets and roadmap

SOI wafer technology has reached maturity. But the demand for thinner and thinner films places new demands on the fabrication methods. At the same time

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SOITEC Thin Products Roadmap Start in Production Silicon Layer Thickness (Å) Si unif all site all wafers at +/-3 sigma (Å) Roughness AFM (RMS) •2x2 µm •10x10 µm Box Layer Thickness (Å) Box Layer TTV

CY 2002

CY 2003 CY 2004 CY 2005 CY 2006

1000

500-700 350-700 200-700 150-700

+/-75

+/-50

+/-30

+/-20

+/-10

1Å 1.5 Å

1.5 Å 2.5 Å

2Å 3.5 Å

2Å 3Å

2Å 2.5 Å

1450

1450

1450

1000 1450

1000 1450

± 4%

± 3%

± 3%

200 mm 300 mm • 3 mm Edge Exclusive • XUT products read for sampling Table 1. Soitec’s SOI product roadmap.

silicon germanium on insulator (SGOI) and sSOI, two new technologies, are moving into the pre-industrialization phase.

To accommodate the scaling parameters outlined in the ITRS roadmap, our wafer specifications (see Table 1) have quickly become more stringent. For the SOI wafers produced in 2002, which were targeted for partially depleted devices at the 130 nm node, the minimum top silicon layer thickness was 1000 Å, with uniformity of ±10%. In 2003 the thickness requirement was halved, and will be halved again for 2005. By 2006, fully depleted devices will require silicon layers as thin as 150 Å. With silicon uniformity of ±10%, mere angstroms in variation could affect device yield, making accuracy paramount. The insulating buried oxide layer, or BOX, is also thinning, but not as quickly.

As we expanded to 300 mm a few years ago, we also implemented new process generations in which splitting and surface smoothing conditions were optimized. This enabled us to create as-split structures approaching 1 Å thickness uniformity (1σ).

The need for tighter thickness control was coupled with the industry’s transition to 300 mm. While expanding to 300 mm, we introduced new, optimized process generations, which produced two significant results.

First, better control from oxidation to splitting led to drastic improvements in as-split uniformity and roughness. This enabled us to create, for example, as-split structures approaching 1 Å thickness uniformity (1σ).

± 3%

± 3%

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Surface smoothing to obtain the final structure has also been optimized to ensure that it does not degrade the assplit properties.

In addition to thickness uniformity, the other major parameter in SOI wafers is defect density. With the 300 mm ramp, optimized manufacturing processes yielded quality equal to or better than 200 mm, with a more aggressive edge exclusion specification: 3 mm versus 5 mm for 200 mm.

In parallel to ultrathin SOI, the roadmap also calls for sSOI. By introducing biaxial tensile strain into the silicon lattice, electron mobility is substantially increased. There are several approaches to creating strained silicon (see Figure 1).

In the first generation, which is targeted at partially depleted devices, the strained layer is maintained by a sub-layer template of silicon germanium (SiGe). This is referred to as SGOI. In the next generation, slated for the following year, the strained silicon will be bonded directly to the insulating layer, eliminating the template layer from the final product. This is referred to by various acronyms, including sSOI and SSDOI. It is targeted for fully depleted device applications, with the strained silicon layer thickness initially running equal to or less than 200 Å.

SOI is also of interest to those in the MEMS (microelectro-mechanical systems) and microphotonics domains. In SOI wafers for MEMS, the top monocrystalline silicon layer is typically quite thick (between 1 and 100 µm). Monocrystalline silicon offers many advantages over traditional polycrystalline silicon, and enables the creation of more complex structures. In photonics applications, SOI enables the creation of small optical waveguides with much sharper bends than would be possible with traditional glass waveguides.

Strained Si relaxed Si1-xGex BOX (insulation)

Strained Si BOX (insulation)

Si Base

Si Base

Figure 1. New engineered substrates: SGOI on the left; sSOI on the right.

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Yield challenges and strategies

Users of SOI wafers depend on the supplier to deliver high-quality wafers at reasonable prices. As is also the case for bulk and epi wafers, SOI wafers must meet very stringent flatness and defectivity standards. With the move to 90 nm geometries, all wafer suppliers must also tackle the issues of thickness, uniformity, and nanotopography. What makes SOI wafers different when considering metrology techniques are the Figure 2. A typical SFQR map on a 700/1450 Å wafer demonstrates the impact of the base very thin top silicon films and the mulwafer’s properties on the flatness of the final SOI structure. tiple Si/SiO2 interfaces. The challenges increase with each new scaling generaThe NP1 eliminates the challenges that were once tion. However, chipmakers have the benefit of the tools associated with measuring flatness on SOI wafers. and expertise developed by and for the wafer suppliers.

Figure 2 shows a typical SFQR map on a 700/1450 Å In the remainder of this paper, we’ll look at the primary wafer, using a 33x33 mm site size. When comparing areas where the techniques, tools, and processes we the geometric properties of the final SOI wafer with helped develop and use to increase yield and detect the initial handle wafer used for this SOI wafer, it is defects will also be useful to our customers as they clear that the final SOI flatness properties mimic the ramp their SOI-based IC fabrication. geometric properties of the base wafer. This is understandable, considering that Unibond fabrication using Flatness and nanotopography monitoring the Smart Cut process simply adds an ultrathin, uniform Site flatness and surface nanotopography (SNT) are two layer in a conformal way onto the handle silicon wafer. key parameters regarding device processing on a wafer.

Therefore, final SOI site flatness specifications are SOI wafers are used in advanced device manufacturing, directly linked to the initial properties of the incoming typically involving design rules of 130 nm or below, base wafers. requiring tight specifications both for lithography and process behavior. Site flatness and SNT impact the focus SNT typically shows the same behavior as site flatness budget of wafers in lithography and CMP steps such as as long as thickness uniformity is in the nm range shallow trench isolation (STI) planarization. SNT is also within 2x2 or 10x10 mm sites. In Unibond fabricacritical to SOI wafer manufacturing due to its impact tion, these advanced uniformity properties are verified; on bonding properties. Edge roll-off is another critical the initial base wafer SNT remains basically unchanged parameter for wafer bonding, as it drives wafer bonding on final SOI structure. quality in the near edge area (the last 3 mm), then defines the non-SOI area on an SOI wafer.

Defectivity monitoring

We use KLA-Tencor’s NanoPro NP1 differential interferometer to characterize the starting Si wafers and the SOI structures throughout the fabrication process. The NP1 enables us to look at both the front and back surfaces of the wafer, and to measure wafer shape, edge rolloff, thickness, flatness and nanotopology in a single scan. It also keeps roughness and reflectivityinduced artifacts to a minimum, due to oblique-angle illumination.

In the most recent ITRS roadmap, both threshold and defect density are aggressively reduced as device design

2µm

Figure 3. SEM images for main killer defects depending on substrate types. From left, COPs on CZ substrate, cr ystalline defect on an epi layer, and void in a Unibond SOI layer.

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Sum of Defects >0.1 µm (wafer)

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SP1

@488 nm

SOI

60

BOX Bulk

40

Bulk

Polished Wafer

SOI

20

Figure 5. Scattering modification is dependent on silicon and BOX

0 175

200

250

350

thicknesses.

700

SOI Layer Thickness (Å)

facturing and established as the tool of reference for SOI defectivity measurement.

Figure 4. Film thickness is not a factor in SOI product defectivity.

rules shrink. These defectivity requirements are set in order to protect device manufacturing yields, which means catching any potential killer defect at the incoming material stage. During the last generation, the starting substrate has significantly evolved. The active layer for transistor fabrication has changed from Czochralski (CZ) silicon to epitaxied silicon and to an SOI layer. Each of these substrates has shown different killer defects as illustrated in Figure 3. Crystal originated particles (COPs) have been demonstrated on CZ wafers as impacting the gate oxide’s reliability. With epi substrates, crystalline-type defects can be generated during the epi layer growth, resulting in large epi mounds or spikes exhibiting a very high killer ratio for devices. For SOI a typical defect type is the void, which is essentially a defective area where the SOI layer is missing.

Nevertheless, the SOI structure impacts the optical response from the SOI wafer (Figure 5). Whereas in a bulk wafer transmitted light is absorbed, SOI buried interfaces are able to reflect part of the transmitted light at the interface. Incoming and reflected beams interfere with each other, changing the apparent reflectivity of the SOI wafer and impacting surface defect scattering.

Figure 6 shows how scattering is modified depending on silicon and BOX thicknesses. Depending on destructive or constructive interference, scattering is decreased or increased and defects are undersized or oversized. The wafer itself drives sensitivity rather than the tool settings. Using all available features on the SP1 combined with an implementation of calibration curves, SOI wafer inspectability can be improved and accurate defectivity monitoring can be carried out in manufacturing.

Defectivity in SOI wafers is monitored using the same tool technology as bare silicon or epi substrates. The KLA-Tencor SP1 is now commonly used in manu-

200

BOX Thickness (nm)

With the move to the ultrathin film generation, particle contamination is kept at a very low level so that SOI product defectivity is not impacted in film thickness down to 175 Å (Figure 4).

BOX Thickness (nm)

For Smart Cut technology, as for all bonding-based SOI, voids are bonded defects, mainly induced by particles trapped at the Scattering, P-pol (arb. color scale) bonding interface when contacting 200 wafers. This is why tight particle control is required in all the processing 150 steps performed on seed and handle wafers before bonding.

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0 0

20 40 60 80 Top Si Thickness (nm)

100

Scattering, P-pol (arb. color scale)

150

100

50

0 0

20 40 60 80 Top Si Thickness (nm)

100

Figure 6. Left: Simulated scattering intensity depending on silicon and buried oxide thicknesses for SP1 constants, using P polarization and oblique incidence. Right: Simulated scattering intensity depending on silicon and buried oxide thicknesses for the new SP2 generation, using P polarization and oblique incidence.

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been proven false for SGOI, unless the film is beyond critical thickness (as defined by Matthews-Blakeslee criterion) and is in a meta-stable state. The silicon thickness limitations for sSOI are more complex, and are still the subject of continuing research.

Table 2 lists the key parameters to be examined when establishing target specifications for strained Si and the associated ranges that are likely for the earliest embodiments. In addition, Figure 7. A 0.15 µm threshold map of a 300 mm 700/1450 Å SOI wafer. This methods for measuring strained Si subtypical example demonstrates that low defect density is achieved on SOI. strate characteristics are tabulated: spectroscopic ellipsometry (SE), x-ray Figure 7 shows a 0.15 µm threshold map of a 300 mm diffraction (XRD), etch pit density (EPD), plan-view 700/1450 Å SOI wafer. This typical example demontransmission electron microscopy (PVTEM), atomic strates that low defect density is achieved on SOI. Tool force microscopy (AFM), and optical interferometry. It optimization has to be done for every thickness combiis important to note that the tabulated metrology nation, with a dedicated calibration curve, which adds methods represent the current state-of-the-art in complexity in metrology implementation on SOI. research and development applications, but some of the techniques will probably be replaced with more proGoing forward to the next design generations, more duction-friendly, nondestructive techniques. stringent requirements are described by industry roadmaps with, for example, 90 nm threshold inspecThe chief challenge in SGOI is ensuring that the lattice tion for the 65 nm node. mismatch is confined to the graded buffer layer, so that uniformity in the relaxed template layer is maintained.

New inspection capabilities are required at the 90 nm design rule and below. The new generation KLA-Tencor The ITRS document makes recommendations for SP2 responds to this need as shown in Figure 6, with a evaluating the critical parameters, but acknowledges constant scattering behavior for all silicon and box that some of the techniques will be replaced for highthicknesses down to 200 Å. Early results show detection volume production. at the 60 nm threshold, satisfying industry needs down to 45 nm. SOI will then behave as bare silicon wafers Table 2 shows the key parameters for strained Si wafers on an SP2, with one unique calibration curve whatever and the current metrology tools for measuring them. the product. It is important to note that ultrathin films Numerous development projects are underway, including (<200 Å) offer enhanced scattering, allowing easier work that Soitec and KLA-Tencor are engaged in to inspectability. ensure that the requisite metrology tools are in place in time to meet the roadmap requirements. Threading Strained silicon metrology dislocations and pileup densities comprise the primary Strained silicon introduces new metrology challenges. potential defects.

The key parameters and the methods for measuring them are detailed in the “Emerging Materials” docuShort-range and long-range surface roughness are also ment of the 2003 ITRS. issues. Short-scale roughness could impact transistor performance; long-scale roughness could impact lithogSome early strained silicon discussions suggested that raphy. Both are factors in metrology based on lightthermal processing would relax the strain.1 This has scattering (as discussed earlier).

1

Assumes the Ge layer is 100% relaxed with the SiGe lattice constant calculated by the Dismukes non-linear extrapolation. In the case of sSOI, although there is no Ge layer in the structure, the Ge content value represents what would result in the equivalent strain in the Si film.

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Next generation metrology Soitec and KLA-Tencor are jointly developing an inspection system that IC manufacturers can use in

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Strained Si Structure Bulk

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Strained Si Thickness (Å)

SiGe Thickness (Å)

Ge Content1

Strain Content (%)

Threading Dislocation Density (#/cm2)

Pileup Density (cm/cm2)

Short RangeAverage Surface Roughness (Å)

Long RangeAverage Surface Roughness (Å)

75-225

N/A

0.15-0.30

0.56-1.15

<5x105

<1

<1

<5

5

SGOI (PD)

75-225

225-725

0.15-0.30

0.56-1.15

<5x10

<1

<1

<5

SGOI (FD)

75-225

75-425

0.15-0.30

0.56-1.15

<5x105

<1

<1

<5

SGOI (PD)

500-800

N/A

0.15-0.30

0.56-1.15

<5x105

<1

<1

<5

SGOI (FD)

150-500

N/A

0.15-0.30

0.56-1.15

<5x105

<1

<1

<5

Metrology Technique

SE

SE

XRD/SE

Raman Spectroscopy

EPD/PVTEM

EPD/PVTEM

AFM/Optical Interferometry

AFM/Optical Interferometry

Table 2. Key Strained Si Parameters and Target Ranges

high-volume SOI and strained SOI-based manufacturing.

The goal is to optimize the Surfscan SP2 inspection tool for the 90 nm and 65 nm nodes, and make it extendable to other engineered substrate materials for future nodes.

Like its SP1 predecessor, it is designed for a wide variety of defects at high throughput.

To meet the ITRS targets, the suppliers of semiconductor equipment, materials and expertise are working on solutions for technology nodes that are still two or three generations away. Likewise, users of today’s SOI tools benefit from the accumulated expertise of the suppliers. So, as SOI enters the mainstream for leadingedge IC manufacturing, the high-volume, productionworthy metrology and inspection equipment is ready.

Reference 1. “Emerging Materials,” ITRS 2003

DR. GEORGE CELLER is chief scientist at SOITEC/USA. Previously, he spent 25 years at Bell Laboratories in Murray Hill, New Jersey, where he was a distinguished member of technical staff and technical manager. He received his M.Sc. degree from the University of Warsaw and a Ph.D. in solid state physics from Purdue

University. In addition to his long-term interest in silicon-on-insulator structures and their applications, he also investigated laser annealing and rapid thermal processing of semiconductors, diffusion phenomena in Si and silicon dioxide, and x-ray lithography. He has published over 170 articles and edited seven books, and was issued 15 U.S. patents. He is a fellow of the American Physical Society and of The Electrochemical Society, a member of IEEE and the Materials Research Society. He has received the 1994 Electronics Division Award of The Electrochemical Society, and two Bell Labs President’s Gold Awards.

CHRISTOPHE MALEVILLE, PhD is a process engineering manager at Soitec in Bernin, France. Since 1993, he has been involved with the development of the Smart Cut process in collaboration with the Commissariat à l’Energie Atomique/Laboratoire d’Electronique (CEA/LETI) and has worked on its application to the manufacturing of SOI wafers. Currently he participates in new SOI process development and in transferring SOI technology to production. He has authored or co-authored more than 30 papers dealing with SOI manufacturing and metrology and holds approximately 15 patents in that area. He received his PhD in microelectronics from the Institute Polytechnique de Grenoble.

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