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An Automated Recipe-Based Defect Analysis System for ASICs

by Manu Rehani, Bruce Whitefield, John Knoch, LSI Logic Erik Tandberg, KLA-Tencor Corporation This article is based on a transcription of a paper presented at the KLA-Tencor YMS seminar at SEMICON/Southwest 1999.

Manufacturers of application-specific integrated circuits (ASICs) face some unique yield-management challenges. At any given time, scores of different products and numerous different technologies may be moving through the manufacturing line – some ramping up, some already ramped, and some in a start-up phase. While any competitive semiconductor company must constantly refine and improve its defect detection and correction methodologies, an ASIC house is unmatched in its need for yield management methodologies that are simultaneously broad-based and robust. In this paper, LSI Logic describes how implementing a recipe-based defect analysis system has simplified management of their inline monitoring program, and accelerated yield learning by providing faster detection of defect excursions and faster, more reliable lot dispositions.

Limitations of an experiencebased defect analysis system

A recipe-based defect analysis system (DAS) is an automated system that allows the user to program the defect data analysis method and flow into a recipe. Historically, defect analysis methodology has been based on the operators’ and engineers’ experience. An operator would run a lot on an inspection system, then decide whether the defect count triggered a statistical process control (SPC) rule by referring to a spreadsheet.

The operator would extract data from the inspections and manually compare the results against the published SPC limits to look for anomalies or “triggers.” In practice an operator could handle only a limited number of trigger types effectively.

Typically, total defect density (TDD) was well-monitored, but other triggers based on subsets of the total defect population were less effectively followed. When limits were changed, it could take days before the change would take effect. Furthermore, the operators’ experience and attitude were not uniform across shifts, and this showed up in the results.

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If the lot passed, it was moved to the next production step. If the defect count violated an SPC rule, the operator would take some pictures of the defects, put the lot on hold, and call the engineer to make a decision on the lot. Disposition of an out-of-spec lot could take 15 minutes to 24 hours, depending upon the skill and availability of the engineer. The potential to miss systematic yield-limiting defects and subsequent effect on cycle time was high.

Benefits of an automated recipe-based defect analysis system

With a recipe-based analysis system such as KLA-Tencor’s Klarity Defect, the operator starts up the Klarity Defect application after completing the inspection. After entering the lot ID and the layer inspected, the operator receives a report in less than a minute. The report provides the operator with information of interest that can be user-defined. For example, total defect density of only large defects, the percent of die affected by large defects, the total density of unclustered defects, composite wafer maps by layer or by defect class, Pareto charts by defect class, and many other quantities (Figure 1) can be automatically generated. Images of defects identified by the automatic defect classification (ADC) system as defects of interest are automatically taken to enable further analysis.

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The benefits LSI Logic found in implementing a recipe-based DAS included the following: • Ensuring uniform analysis and disposition methodologies across all manufacturing and engineering groups through standard analysis recipes and in-house analysis macros • Bringing together the collective knowledge of the organization to ensure the methodologies are best-known methods • Making the process of modification of the methodologies faster and easier – key for the ASIC environment • Minimizing the impact of changing the methodologies on day-to-day operations F i g u r e 1. Sta ndar d Klarity Defec t re c i p e .

Results from the Klarity Defect report are then input into Excel, where macros designed by LSI compare the various defect counts against centrally managed SPC limits, and flag any defect excursions (see Figure 2).

If an excursion is identified, the lot is sent for further review. Defect source identification is initiated, and corrective action is taken.

• Enabling shift operators to perform initial analysis and disposition without needing as much engineering intervention • Capturing layer-by-layer defect excursions sooner • Decreasing lot disposition time Together, these benefits have had a measurable impact on the yield learning rate in Fab 1, as described below.

Implementation

LSI Logic has a number of inspection and review tools supplying data to their data analysis system, along with various other systems, either commercial or developed in-house (Figure 3). Engineers responsible for in-line

F i g u re 2. The Excel macros a re based on data generated by Klarity Defect. Wafers that fail accor ding to SPC trigg ers a re clearly identified in t he Excel output. In this example the operator would know immediately that the total def ect density and the total unclus tered defect d ensi ty is no t high, so he or she would not expect too many d efects o n thes e wafers. However, on three out of the four wafers th ey woul d expec l a rge defects, and these would need their atten tion. Th e oper ator would then click on ADC. The Excel output tells the operator which defect class has fa iled – in this case, large particle s. T his lot was inspected with sizing and ADC and within a minute an operato r r an Klarity Defect an d Excel, an d the lot went on its way.

F i g u r e 3. This d iagr am s hows a schematic lay out of the syst ems tha t generate or access the defect data i n F ab 1 at LSI Logic.

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monitoring use Klarity Defect clients installed locally on their machines, which affords more flexibility in their analysis activities. The Klarity Defect clients for routine analysis in the fab are supported through a centrally managed thin client server.

At LSI, routine analysis recipes are centralized on one shared drive. This means that only one recipe table needs to be maintained, and by virtue of the thin client architecture, only one installation needs to be managed.

Such a centrally managed installation provides a common template for all LSI fabs from Gresham to Santa Clara, Colorado and Japan enabling all LSI Logic fabs to access a common pool of production data and carry out routine, yet complex analysis without reinventing the approach.

Figure 4 is a simplified flow chart that illustrates the process for allowing wafers to move from process step A to process step B. After an inspection at process step A, the decision of whether the lot should be analyzed is made for the operator by the Klarity Defect-Excel combination. If the answer is no, the lot goes on to the next step. If the answer is yes, the lot moves into the first level of analysis (facilitated by in-house Excel macros), which involves looking at a top-down view of the inspection results. After the first level of analysis the operator takes the lot to a review station, either optical or electron-beam, for further analysis. Thus the first level of analysis is initiated by Excel and the second level of analysis is initiated by Klarity Defect and the results from the review tools.

After the second level of analysis, the question of whether the lot should be processed further must be

addressed. This decision is automatically made by the Klarity Defect-Excel combination as well. If the answer is no, it goes into scrap or off-line analysis, which feeds information into the identification and corrective action process. If the answer is yes, the lot passes to process step B. At this point, the baseline data has been collected and the in-line monitoring system has been exercised.

Klarity Defect’s role in the decision flow is as follows.

First, the operator runs a standard recipe in Klarity Defect. The recipe performs predetermined calculations and generates the charts and maps the operators need to see. It also generates a data summary that enables the Excel macros to make disposition decisions. LSI Logic has found that using standard recipes generates focused information to enable appropriate lot disposition.

After running the Klarity Defect recipe, the operators run the Excel macro which compares the results from Klarity Defect against a central database and tests whether the lot has passed or failed in accordance with predefined triggers. A typical output from Excel is shown in Figure 2.

Once lot disposition is completed, the identification and corrective action process becomes critical. At LSI Logic, certain engineers responsible for in-line monitoring are assigned responsibility for individual critical layers.

They monitor the behavior of that layer on a daily basis and report on a weekly basis to the group (Figure 5).

Klarity Defect and the Excel macros help the identification and corrective action process function more smoothly because the engineers can more readily drill down to the level details and report the defect trends and their correlation with historical changes to SPC limits, etc.

Similar corrective action events are grouped together to form Corrective Action Cases. Analysis of these cases enables the root cause to be fixed and ultimately affects the bottom line. Figure 5 shows that in Q3 of calendar year 1999 the majority of the cases at LSI Logic were detected by the line monitoring program. Many of the manufacturing issues throughout process, sort, and e-test also used Klarity Defect in gathering evidence to make their individual events into cases. Klarity Defect contributed more than 80 percent of the cases calling for corrective action in that quarter.

F i g u re 4. This flow char t capt ures th e decision flow that is used at Fab 1 to move a lot of wafers f rom p rocess s tep A to pr ocess step B.

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In essence, Klarity Defect’s role in this system is primarily to control data flow. Managing in-line defect data and work in progress (WIP), Klarity Defect (together with

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This integration has allowed LSI to take advantage of some underutilized features of the inspection and review tools, like defect sizing and ADC, to make effective decisions in real time on the fab floor. Dispositions that would have taken from 15 minutes to an entire day were completed in under a minute after implementing the Klarity Defect-Excel combination. LSI has 23 in-line inspections for any given process flow, but the high level of automation has meant that inspections are not a bottleneck to production.

F i g u re 5. This graph shows Total Unclustered Defect Densi ty versus Time for a hypothet ical et ch layer. Klarity Defect and th e Excel macro s p rovided key infor mation, allowing both an overall view of the situation and the ab ility to drill do wn to detai ls with an notation s. This par t i c u l a r c h a r t illustrates that th e system allowed the r e o c c u rrence of an old p robl em (redistributed parti cles) to be fix ed with mini mal impa ct.

the Excel macros) standardizes and automates defect analysis methodologies across all shifts. Utilizing input from the in-house experts, Klarity Defect implements clear and uniform automated lot disposition procedures.

The result has been a reduction in lot disposition time by a few orders of magnitude. Analysis is standardized through Klarity Defect recipes and Excel macros, which automate tasks like limit checking and trend reviewing.

Klarity Defect data also contributes substantially to solving defect sourcing or corrective action cases.

Managing integration of the analysis system into the production flow is critical to successful implementation of Klarity Defect. This involves training the line monitoring operators on tool operation, standardized data analysis, standard dispositions, corrective actions, and communication procedures.

Results

LSI Logic found that integrating Klarity Defect into production has provided significant benefits in several areas. They found that the automation of lot disposition decisions enabled faster response to yield excursions.

They also found that using Klarity Defect for rapid prototyping of new analysis methods was valuable.

Implementing a Klarity Defect-Excel combination has greatly simplified management of the yield program at LSI. For example, an in-line monitoring program consisting of 20 inspection points with 5 parameters monitored per inspection and 30 operators will result in 3000 variables that need to be managed. Such a program would be overwhelming to manage without a recipebased system or a centralized control on SPC limits.

With Klarity Defect integration, the number of variables has been reduced from 3000 to 1, because one engineer or one group can easily manage the whole system.

Reference 1.“Automating Routine Tasks in Yield Management,” Nicola Kamper and Rebecca Howland Pinto, Semiconductor I n t e rnational, June, 1999.

Klarity Defect is part of PMC-Net™, the industry's first software solution to connect all yield, process and test-floor data into a single, automated, customizable and easy-to-use data collection, analysis and reporting system. PMC-Net comprises a centralized database (that stores in a common format all yield critical data generated by a fab's data-generating tools) and the PMC-Net Applications Suite™, an expanding range of modular and customizable yield analysis programs using the decision flow analysis software architec ture. With applications available for Defect Reduction, Process Parametric Control, and Test Floor Control, PMC-Net provides information from the entire fab operation for accelerated yield analysis and control.

For more information please contact: erik.tandberg@kla-tencor.com

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