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Challenges for the Sub-0.18 µm Era by Didier Lamouche, ALTIS Semiconductor
The primary challenge for the sub-0.18 µm era lies in bringing the semiconductor industry to maturity. In this paper the concept of a mature industry will be discussed, the gaps between the present state of our industry and a mature version will be explored, and suggestions for how to drive the maturity of the industry will be offered.
Familiar classical predictions of the challenges of the sub-0.18 µm era include the following:
out of the door and accelerate the yield curves, it is worthwhile to look ahead to see what challenges accompany sub-0.18 µm technology.
• Lithography will push the limits of optical resolution.
Our immature industr y
• Plasma etch and deposition will be challenged by issues of aspect ratio and selectivity. • Planarization will be a key challenge, as CMP becomes the pervasive technique, and brings issues of uniformity and end point control.
Figure 1 illustrates how the industry has been progressing since 1993. This chart shows the area of silicon needed to make up 256 MB of memory, whether from sixteen 16 MB chips, (Luna E and the ES chips, 1993-1997); four 64 MB chips (Prism, La Tierra and Viper, 1997-1999), or one 256 MB chip (Cromus, 1999). The silicon area needed for 256 MB of DRAM is shrinking rapidly—and the latest generation of chips is a factor of two smaller than Cromus.
• Silicon area efficiency will emerge as an important issue, as feature size continues to decrease, and the I/O density begins to limit the shrinking of the overall device. While each of these technical arguments has merit, the more general topic of the maturity of the industry has received less attention. For that reason, this article will bypass the classical arguments and focus on the larger perspective. To discuss the challenges for sub-0.18 µm device manufacturing does not imply that all problems for the pre-0.18 µm technology node have been solved. Most fabs today still struggle to scale the reliability curves for technologies that remain above 0.18 µm. As the industry works to get more chips 54
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F i g u re 1. The sil icon area re q u i red to comprise 256MB of DRA M using 16MB, 64MB or 256MB chi ps has shrunk dramat ically since 1993.
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F i g u re 2. Lar ge growth rates and rap id swings ar e a key indicator o f the immaturi ty of the s emicond ucto r i ndus tr y.
Looking at the industry from a different perspective, Figure 2 reveals the immaturity of our industry more directly. This chart shows the year-to-year growth or recession of our industry since 1978. Growth rates of 20%, 30%, or even 40%, are followed by brutal recessions of 10% or 20%. These swings are typical of an immature industry. When a mature industry like the automobile industry has a good year, they grow at 5% to 10% per year globally; a bad year would be characterized by 5% recession. A focus on yield is one key element that differentiates an immature industry from a mature one. In the manufacturing environment, mature industries like the automobile industry or the tire manufacturing industry focus more on reliability and defects than on yields. No one would imagine GM or Ford throwing away 20% of their cars at the end of the manufacturing line. At the other end of the scale, an emerging industry is not ready to focus on yield; it is focused on having a working product. In this learning phase, 5% or 10% yield is acceptable. In between the mature and emerging industries are the growing, immature industries where yield is extremely important—such as the semiconductor industry. These industries have yields in the range of
20% to 80%. The fact that our industry is preoccupied with yields is a key proof that it is not mature yet. In the early 1980s when the design rule was 1 µm, some people predicted that sub-micrometer devices would not be manufacturable. Twenty years later, we manufacture 0.15 µm products. Another interesting study by an American scientist calculated the global revenue of the semiconductor industry, under the assumption that the industry would grow at 20% per year indefinitely. His conclusion was that the revenue of the total semiconductor industry would exceed the world GDP in 2040, which is by definition impossible. Given that the industry has to saturate one day, what will happen to the yield? Figure 3 shows the yield learning that has been achieved since 1990 for DRAM technology. The vertical axis shows the wafer yield, and the horizontal axis gives the number of wafers that were expended before that level of yield was achieved. The desirable part of the curve is in the upper left-hand region—the fewer wafers needed to get to higher yield, the more cost-effective the product ramp. This chart shows that the trend is becoming steeper and moving towards the left: yields that used to take years, now take months. Another way to represent the same information Spring 2001
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is that the number of wafers needed to achieve a given yield has decreased a thousand-fold in 15 years. Key market stimuli
Yield learning is an unavoidable race—one cannot simply stop when an industry has become mature. How quickly will our industry become mature? To answer that question one should look in detail at the boundary conditions and the stimuli that the current market is applying to the semiconductor industry. Four types of stimuli are important to the advanced semiconductor business; the first one is a decrease in product cycle. Even the consumer applications today tend to use more and more advanced semiconductor technologies. Five years ago only industry applications— high end personal computers or main frames—were using the advanced 0.5 µm technologies. Today, consumer applications are driving the race to produce leading-edge technology. For example, cell phones are equipped with 0.25 µm technology, and the product cycle of a cell phone is six to nine months. If a new phone is introduced too late for December sales, the impact on yearly revenue is significant. A yield bust in October would cause the cell phone manufacturer to
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miss a whole year of revenue. Shorter product cycles result in no time for yield learning. Second, investment rates are growing. Today a new fab costs US$1.5 billion. Consequently, rapid recovery of the initial start-up investment provides a strong stimulus to the semiconductor industry. Third, the race to function integration, or so-called “system-on-a-chip”, is about to explode. Even though today most applications based on multiple-chip solutions are cheaper than an equivalent integrated solution on one chip, performance will drive the integrated solution to dominate. The main driver again is consumer applications, especially the wireless phenomenon; the marketplace has an insatiable demand for smaller and smaller telecommunications appliances that enable instant, round-the-clock connectivity and remote data access. This is driving the integration of many different functions: DRAM, flash, high power devices, RF capabilities. The fourth market stimulus is the fast production ramp, which is really a consequence of the other three. Fabs need to be ramped up almost before they get started. Together these four stimuli drive the industry to a faster and more difficult yield ramp.
F i g u re 3. The yield lea rning t hat has bee n a chieved since 1990 fo r DR AM tech nolo gy has been dramatic, as th e number of wafers re q u i red to meet a given yield has b een reduced one thousa nd-fold .
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F i g u re 4. This ex ampl e from an embedded DR AM product at ALTI S demonstra tes that ma stering th e DRAM (ES products) and logi c components is not eno ugh; the challenge lies in the integra tion of the two.
Recommendations for success
The market stimuli of shorter product cycles, growing investment, function integration, and fast ramps are driving the need to migrate from a yield learning culture during the manufacturing phase towards failure mode prediction before the manufacturing ramp. This migration is driven primarily by function integration. Figure 4 provides an example from an embedded DRAM product at ALTIS. The vertical axis is the desired yield, and the horizontal axis is time in years or quarters. This chart shows good yield learning throughout shrinks from 0.5 µm to 0.45 µm to 0.4 µm to 0.35 µm, and yields were attained and stabilized well above 80% for a long time period. At the same time, ALTIS had a pure digital logic technology running at 0.35 µm, which was very stable also in the lower 90% yield range. However, when a new design was introduced that merged those two technologies into a new one called embedded DRAM—the first instance of a system-on-a-chip solution —ALTIS experienced a yield bust from which it took six months to recover. The message is that mastering the DRAM and logic components is not enough; the challenge lies in the integration. To enable future suc-
cess in integration, the key is to transfer one’s mindset from yield learning to failure mode prediction. The defect problems that were responsible for this yield drop were defects neither attributable to the DRAM nor to the logic, but rather to their integration. Failure mode prediction includes understanding various topology effects such as pattern density variations on a chip, focusing on local areas which might be sensitive to yield problems, and building more redundancy. Powerful CAD packages can be used to simulate materials properties and stacking of the various layers. Simulation of the 3D environment may point to specific topology problems, identifying local areas where problems might occur, so that additional redundancy can be built in. Alternatively, the inspection sampling strategy can be changed to monitor certain problem areas on the chip more carefully. The second challenge has to do with the manufacturing ramp—maintaining the maximum yield demonstrated during the development phase while the products are ramped. This challenge requires process control, tool control, tool and process fingerprinting and duplication, and very fast feedback loops. The graph on the Spring 2001
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left in Figure 5 compares a typical volume/capacity ramp with a non-competitive yield ramp. During the non-competitive yield ramp, yield busts occur from time to time, typically while ramping the capacity. These yield busts are particularly damaging with short product life cycles. In the future, the industry will need competitive yield ramps as shown on the graph on the right in Figure 5. In this example the yield is high from day one in the development phase, and the yield is maintained during an aggressive ramp, while new tools and products are introduced. The product cycle time drives this new requirement. The third challenge is the cost of capital. We have to invest $1.5 billion to put a new fab online. Depreciation is calculated on a five-year period; however, five years is more than the duration between two down cycles. Thus we need to get the cash out of the fab in less than the depreciation period, or we need to change the depreciation rule. Clearly, maximum return on investment means that yield busts cannot be tolerated. Instead, we must transform the yield learning culture to a failure
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mode prediction culture, and learn to accomplish a volume ramp while keeping the maximum yield. In conclusion, it is clear that a revolution in thinking is needed to bring our industry closer to maturity. Once it matures, we will not talk about yield or yield ramps any more. In the meantime, the yield ramps have to become steeper and steeper. As a consequence, the companies who win the semiconductor race will have to lead the yield learning race. The first key challenge and success factor is migration from a yield learning approach to a failure mode prediction approach, so that maximum yield is obtained before the manufacturing ramp. The second is the ability to maintain maximum yield during the manufacturing ramp. A key to failure mode prediction lies in simulation techniques that bring together the design and process in order to anticipate which device types could fail when they are integrated on a chip. Maintaining maximum yield during your manufacturing ramp up may require better process control, faster feedback loops, or better tool fingerprinting.
F i g u re 5. The graph on the left com pares a typical volume/capacity ramp with a non-competitive yield ramp ha ving an ob vious y ield bust . T he graph on t he ri ght shows the future re q u i remen t for competit ive yiel d r amps, where th e yield is high beginning in th e devel opmen t phase, and is mai ntained duri ng a n a ggressive ramp .
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