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Breaking Through the Copper/Low-κ Barrier Defect Management in Copper Devices Part 1: From Barrier/Seed Through Post-CMP Clean Paul Marella, Steve Fanelli, Vikas Sachan, and Dave Coldren, KLA-Tencor Corporation
While copper interconnects and low-κ dielectrics represent enabling technologies for current and future device performance, their use is accompanied by some unique and difficult challenges. Surface and sub-surface interconnect voids, plus copper CMP slurry and clean residues are among the most common types of defects found in the part of the copper process that begins with barrier and seed deposition, encompasses copper electroplating, annealing, and chemical mechanical polishing (CMP), and ends with post-CMP and backside cleaning. The new defect Pareto they create is founded on the unique material properties of copper and low-κ dielectrics and upon the architecture of the damascene process required to utilize these materials. These yield and reliability challenges are expected to deepen as devices evolve past the 130 nm node. Introduction
The performance enhancements granted by copper and low-κ dielectrics come at a cost. The materials are relatively new to chip manufacturers, and their properties present some challenges, especially in the areas of interconnect yield and reliability.1 New defect types are arising during photolithography and etch, as well as during deposition, anneal, polish and cleaning. Despite the difficulties, all of the world’s major chip manufacturers have incorporated, or are in the process of incorporating, copper/low-κ interconnects into their devices. Microprocessors with copper are in production; copper ASICs are mostly found in pilot-lines, and copper DRAMs are in the R & D labs. In some leading technology devices, copper and low-κ have completely replaced aluminum and oxide processes at every level. Copper/low-κ technology now dominates 130 nm devices, and will be crucial to the successful introduction of 90 nm and 65 nm devices. The use of copper and low-κ materials Spring 2003
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Impact
Voids
Barrier/seed deposition, ECD, anneal
Risk of opens in vias and trenches—device failure
Protrusions
ECD
Typically nuisance – CMP may eliminate
Copper hillocks
ECD, anneal
Nuisance
Remaining Metal
CMP
Interconnect shorts
Underpolish of Copper or barrier
CMP
Shorts
Overpolish
CMP
Opens or resistive leakage of copper into dielectric; thinning of stack accompanied by lower device yield
Scratches
CMP
Embedded Contamination
CMP
Microscratches are usually considered nuisance but larger scratches may lead to opens or shorts Electrical shorts; planarity loss at the dielectric level
Chatter marks
CMP
Dielectric rip-outs
CMP
Peeling (adhesion)
CMP
Scratching whole wafer – device failure
Corrosion
CMP clean
Opens or reliability issues
Residual Slurry
CMP and CMP Clean
Affects subsequent metallization layer: blocked etch
Clean residues
CMP clean
Affects subsequent metallization layer: blocked etch
May affect subsequent metallization layer; excess metal may generate shorts Next-level shorts
Table I. Common defect types in the copper/low- κ process.
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is also predicted to lead 300 mm wafer production in the near future. Despite the complexity and scaling of this leading-edge technology, expectations are that defect densities should be the same or better than in previous-generation devices. One of the keys to successful production of copper/low-κ devices is appropriate defect management. This paper is the first in a three-part series that will address defect monitoring from barrier/seed through cleaning, defect monitoring in the photo area, and inline electrical defect monitoring for copper/low-κ devices. New materials, new defect types
Within the scope of this paper several critical process steps are considered: PVD barrier and seed deposition, copper electroplating or electrochemical deposition (ECD), annealing, CMP, post-CMP cleaning, and finally a backside clean. Common defect types associated with these processes are given in Table I. While some of these defect types are well known from aluminum/oxide processes, many are new. What is it about copper and/or low-κ that has introduced these defects? Insight can be gained by examining some of the fundamental material properties of copper and low-κ insulators, and contrasting them with the better-known materials of aluminum and oxide dielectrics. Besides its superior conductivity, copper is reputed to offer better electromigration (EM) resistance than aluminum. In reality copper offers different EM resistance from that of aluminum. Copper EM processes are dominated by surface and interface diffusion, while aluminum EM processes are dominated by grainboundary diffusion. Electromigration in copper can result in diffusion of
Figure 1. Defect examples associated with barrier deposition or dielectric/barrier interface.
copper into neighboring dielectrics and silicon, potentially poisoning the devices by causing shorts or leaks. Thus, with copper devices, the integrity of the metal/dielectric interface is critical. It is necessary to introduce a more refractive barrier metal between the dielectric and the copper layers to encapsulate the interconnects adequately. Typically a tantalum/tantalum nitride (Ta/TaN) bilayer is used, a material that has shown excellent barrier properties up to 550 Celsius. If the barrier coverage is incomplete, or adhesion between the barrier and the dielectric is imperfect, copper may leak into the dielectric and cause performance issues, reliability issues or failure. Copper diffusion may also leave behind voids. After the barrier layer is deposited, typically by physical vapor deposition (PVD), a copper seed layer is deposited without breaking vacuum. The seed layer is necessary to assure adequate adhesion of the copper to the barrier, with good continuity and a minimum of voids. However, the seed layer represents an addi-
tional process step compared with aluminum-based devices, and any additional step is accompanied by defects (Figure 1). If the seed layer is not continuous, the conductive path from the edge of the wafer to the center, essential for copper electroplating, is interrupted. As a result, tiny copper voids may be created during ECD. During annealing — or later, as the device ages — electromigration can drive the small voids to combine. Such voids represent the biggest yield and reliability issue in these leading-edge devices.1, 3 A remedy for a discontinuous seed layer is to deposit a thicker seed layer. But with the high aspect ratio structures typically found in 130 nm devices and expected in future devices, a thicker seed layer means that the via opening could be narrowed or even pinched off from seedlayer overhang effects. A narrow opening to the via complicates copper fill, and large buried voids may result. Voids are also introduced through the mechanism of stress migration. Film stress, induced by repeated thermal
Figure 2. Void examples in interconnect.
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cycling of the copper films to accommodate deposition and annealing of subsequent layers, can also cause small voids to coalesce and migrate to the bottom of the via. Most of these voids are confined to the copper interconnect regions (Figure 2) and relate to the quality of the copper-tantalum interfaces, but the use of low-κ dielectrics, having different coefficients of thermal expansion from their oxide predecessors, can worsen stress management issues. Film stress gradients can also result in the formation of copper hillocks. This defect type is particularly of concern when the temperature is cycled prior to capping the annealed copper with a SiN or SiC etch stop layer. While copper hillocks are not usually a yield-limiting defect, they add nuisance defects to the total defect count, lowering the signal-to-noise ratio. The native oxides of copper are quite different from aluminum oxide, and this disparity leads to significant differences in the corrosion properties of the two metals. Copper is a stronger oxidizing agent than aluminum and forms a relatively soft and porous layer of hydrated oxides. In contrast, aluminum forms a thin and tough protective layer of Al2O3, which is self-limiting in thickness. Plasma treatments must be used to remove the surface oxides of copper before the metal is capped; furthermore, the time lag between copper CMP and cap layer deposition must be kept to a minimum unless the wafers are in protective pods. During CMP, corrosion can occur when the chemicals in the slurry or the cleaning solutions interact with the bare copper surface. Corrosion and oxidation defects affect the electrical integrity of the interconnects (Figure 3). Low-κ materials have a stronger tendency to interact with various surface functional groups during the numerous etch, deposition, polish, 20
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Figure 3. Copper corrosion and oxidation defects.
and clean steps, resulting in organic residues unfamiliar from last-generation dielectric processes (Figure 4). Residue removal — of metal, slurry or organic material — is more difficult with low-κ dielectrics because their surface wetting properties are more demanding, and less aggressive chemistries must be used.1
conditions affect the texture of the copper film during electroplating, which in turn affects the strength of the interface. Without adequate adhesion between copper and barrier metal, or between barrier metal and low-κ layers, or between copper and cap layers, CMP may tear apart the stack, causing local dielectric rip-out or delamination, or fissures at the interfaces (Figure 5). Exacerbating this problem is the low Young’s modulus of the low-κ materials, which causes them to flake easily. A final and very important difference between copper/low-κ devices and their aluminum/oxide predecessors is that the new devices are fabricated using damascene processes,
Figure 4. Organic residue defects.
Adhesion can be challenging in copper/low-κ devices because new materials necessitate new understanding of the physical chemistry of interacting neighboring layers. Adhesion is also a more difficult problem because the number of interfaces has been increased by the requirement for a seed layer for each copper metallization. Barrier-seed
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Figure 5. Delamination, dielectric rip-out, and interface fissure defects.
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YIELD DETERRENTS
Misc.
0%
Shorts
10%
OPENS
Misc.
20%
Shorts
0%
OPENS
10%
Voids (Open)
20%
YIELD DETERRENTS
Figure 6. Void formation is a major yield deterrent in copper devices.
while the older devices are fabricated using subtractive processes, such as reactive ion etch (RIE) (Figure 6). Because many acids do not react as readily with copper as they do with aluminum, a suitable copper etch chemistry has not been found. Thus, the industry has turned to single or dual damascene processes, based on previous experience with tungsten lift-off of larger-geometry devices. With single damascene, or the more cost-effective (but more difficult) dual-damascene process, the challenge lies in filling a high-aspectratio cavity. The difference in architecture between a damascene process and a subtractive process contributes to a change in the dominant defect types for each process. With RIE, particles that are left behind as contaminants of the etch process or incompletely etched material, may result in shorts (Figure 7) — or they may not cause a problem at all. In contrast, particles left behind during dielectric removal for the damascene process will ultimately result in voids, especially harmful after thermal cycling or device aging causes the voids to coalesce and migrate to the bottoms of the vias. Voids typically end up as opens. Complete opens will cause device failure, while partial opens will have an impact on reliability.
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dominate. Furthermore, the ratio of nuisance defects to yield-limiting defects is high. In this realm of defect management, extensive sampling is necessary for adequate excursion monitoring. Also, tracking defects by type is critical to yield learning and tool monitoring in the presence of high nuisance counts.
Typical Yield Deterrents in Copper versus Aluminum Interconnects
Cu Dual-damascene
E
Common practices for copper defect control
The number and variety of new defect types arising during copper processing is remarkable. Critical processing steps use new materials, processes and equipment. New processing parameters are required for ECD and anneal. The CMP consumables set is new — slurry, pad, and clean chemistry — to address new requirements for polishing copper and low-κ materials. Defect control in such an environment requires a well-planned methodology and precisely the right set of inspection tools. Because copper/low-κ is a relatively immature process, single-wafer excursions
While double-darkfield inspection is generally preferred for film levels, such as interlayer diectric and copper ECD,8 a study of several of the most successful foundries and integrated device manufacturer fabs in the US, Asia and Europe, has shown that the most common tool set for successful defect control at copper CMP is a mix of high resolution imaging and double-darkfield inspection. During the development and ramp phases, highresolution imaging is used for a greater percentage of inspections. As yield learning progresses and wafer sampling demands increase, double-darkfield inspection is increasingly used to meet the requirement for higher throughput (Table II).8 Post copper CMP, generally two wafers per lot are inspected in both logic and memory areas to measure CMP and ECD defectivity. At the same time, the substantial wafer-towafer variation from under-polish and residue defects drives the need for high within-lot wafer sampling. Here,
Technology Changes Redefine Fault Mechanisms Interconnect Solutions AI - subtractive AI
AI
Defect Type
Fault Mechanism
Static, on-surface
Particles
SHORTS
Dynamic, Sub-surface
Particles
VOIDS
OXIDE Defect Cu - damascene Cu OXIDE Defect
(opens)
(can grow & migrate)
Figure 7. The change from aluminum to copper technology has redefined defect mechanisms for interconnects, requiring new yield management solutions.
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4 Foundry and 4 Logic Fabs, 130 nm Inspection Technology
e-beam
High Resolution Imaging
DoubleDarkfield
Recommended Technology
Barrier Seed
0
1
4
Copper ECD
0
1
1
Copper CMP, M1-M2
3
7
3
High resolution imaging/ e-beam
Copper CMP, M3+
3
5
5
High resolution imaging/ Double-darkfield/e-beam
Double-darkfield Double-darkfield
Table II. Summary of technologies used by eight fabs to control defects in the copper process. These fabs are at various points between yield ramp and production. Adapted from Reference 8.
Recommended Technology
% Lots
Barrier/Seed Double-Darkfield
25-50
3-5
100
50
3-5
100
25-50
2
100
100
5-15
100
Copper ECD Double-Darkfield Copper CMP, High Resolution M1-M2 Imaging Copper CMP, M3+ Double-Darkfield
Typical Sample Plan # Wafers/Lot % Wafer Area
Table III. Summary of typical sampling plan recommended to control defects in the copper process during ramp and production. Adapted from Reference 8.
Inline electrical testing using voltagecontrast mode on an e-beam inspection system is essential for detecting buried voids — perhaps the most critical defect type generated within the copper process. This key technology will be explored in a later article in this series. The use of automated macro inspection, replacing manual inspection in the detection of gross polish defects, will also be explored in a later article, as will the use of unpatterned wafer inspection for tool qualification within the copper module.
have been identified and sourced, mostly by the yield engineers, defect management typically becomes the
Effective tool monitoring during the copper process necessitates closely monitoring each deposition, polishing and cleaning system. The inspection system needs to be situated close to the process tools, not only for convenience and to reduce response time to excursions, but also to minimize exposure time for the copper layers before capping. Finally, contamination considerations often dictate that the inspection system be dedicated to the copper area. Texas Instruments in Dallas, Texas, described the detection of surface and sub-surface voids using optical and e-beam voltage contrast inspection, respectively, in a recent article. TI’s Kilby Development Center (KFAB) used double-darkfield inspection to
Darkfield Inspection Post-ECD and Post-CMP Post-ECD
Post-CMP
Long Pit
Void ECD Void
ECD Void
70%
Post-CMP Pareto
double darkfield inspection is often chosen for its high throughput capabilities (Table III).8
responsibility of the process engineers. The process engineers take ownership of statistical process control (SPC) charts and control limits, and manage the defect excursions within their module. By taking over the tool monitoring, the process engineers free the yield engineers to focus on process and inline monitoring.
Case studies
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Missing Material
Scratch
Particle
Long Pit
0
Void
Short-loop experiments of various kinds take place during the copper process, to work toward resolving defect problems unique to copper/ low-κ devices. Once the common defect types
ECD Void
Figure 8. KLA-Tencor’s AIT darkfield inspection was implemented post-ECD and post-CMP, and utilized to partition the source of patterning and underlying defects.
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eS20XP Via Void Evaluation
eS20XP Defect Scan Summary
Wafer Map Anneal "A"
Total Defect Count
Anneal "B"
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causing yield problems. Screening the pre-ECD seed conditioning, the pre-ECD rinse conditioning, and the postECD anneal, they discovered that the anneal was the problematic area (Figure 9). By changing the anneal conditions they reduced the subsurface void formation to acceptable levels.3
Figure 9. This summarizes the results of the second experiment,
Infineon Technologies in Dresden, Germany, used pre-ECD rinse, and post-ECD anneal on copper voids. The double-darkfield inspecvast majority of defects found by the KLA-Tencor eS20XP were tion to systematically sub-surface defects as opposed to surface or particle defects. investigate the effectiveness of various post oxide uncover a characteristic spatial pattern CMP cleaning process parameters on of surface voids in the defect wafer memory products, and their potential maps after ECD, after CMP, and after impact on final device yield (Figure the CMP clean, for a 130-nm copper 10). As the post-CMP rinse procedure dual-damascene device. This study was varied, electrical characterization revealed that the root cause of the showed post-CMP defects primarily voids was in the ECD; the voids were affected the wafer’s subsequent metsubsequently enlarged and uncovered allization layer. Slurry agglomeraby CMP and the post-CMP clean tion defects had the greatest impact (Figure 8). TI developed an out-ofon yield, causing shorts between control protocol, and transferred the metal lines. Because nuisance defects process to production.3 showed the greatest variation in number as the rinse parameters were A second experiment by the same varied, tracking by total defect group used an inline e-beam inspeccount would not have been useful. tion system in voltage contrast mode Instead, tracking by defect type to detect sub-surface voids that were was critical, and the inspector’s Real Time Bin 72 Bin 82 Bin 92 Classification option Multi erates m (RTC) was able to distinlo ng co Slurry Channel guish “killer” slurry Detection agglomeration defects from nuisance defects Scratches Single (flat, chopstick-shaped Channel Flat geometrical particles silicon oxide, and microDetection scratches) with no Bin 81 Bin 71 Bin 91 impact on throughput Anomalous 0 100 800 Pixel Area (Figure 11). Infineon determined the optimum cleaning rinse solution Figure 10. Defect binning scheme set up using the AIT’s RTC and process time — and option. The numbers 7, 8, and 9 represent size characterization; the result proved to be a the second digits, 1 and 2, represent single-and multichannel compromise between detection, respectively. which compared the effect of ECD pre-conditioning anneal,
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Figure 11. Images by optical microscope and SEM of typical defect types: Flat, chopstick shaped particles (top), which are regarded as nuisance defects, and spherelike slurry agglomeration (bottom), which affect device yield.
maximizing device yield and minimizing both the process time and cost of consumables.6 TI DMOS 6, TI’s first 300 mm fab, was interested in ramping their 130 nm copper devices on 300 mm wafers quickly. They faced some challenges, particularly because they were bringing up new tools (Figure 12). In phase I (process qualification and integration) they used the KLA-Tencor 2350, high resolution imaging inspector to determine that more than 30% of the die on the wafer were affected by copper seam defects, post CMP. The defect provided problems for vias landing on the leads, and for line resistivity (Figure 13). DMOS6 was able to optimize their CMP process and eliminate the galvanic corrosion that was responsible for the copper seam defects. In phase II (yield ramp) a missingmetal defect, detected post CMP by high resolution imaging, was affecting 3-5% of the die, with excursions affecting up to 20%. The source was found to be TaN barrier particles interfering with the subsequent copper plating. After improvements to
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Inspection Strategy for New Technology/Ramp
Effectiveness
Efficiency
Rationalization
Phase 1/Transfer Finger printing,
Phase 3/Production
Phase 2/Ramp
Max sensitivity -- Look for unknowns
Excursion Control - Yr
YsYr - Integration
(Qualifications / Integration issues)
Defect reduction - DSA Inspection plan - Sample Planner
Figure 12. The key for DMOS6 in the yield ramp were to minimize risk to qualification delays and to get up the yield cur ve as fast as possible.
the barrier metal process, the TaN particles were brought under control. High resolution imaging was also the technology of choice for copper CMP monitoring during phase III (yield entitlement). A new defect signature was detected on a set of wafer maps, and was traced to particles coming from degraded CMP brushes. After the brush was replaced, the defect source was eliminated. During each of these phases, e-beam inspection with the KLA-Tencor eS20XP was used to complement the high resolution imaging, with success at each phase. TI DMOS 6 plans to use a similar high resolution imaging and e-beam inspection strategy to bring up their 100 nm process.9 AMD Fab 30, described an effective tool monitoring strategy for their copper CMP module, in which both single-wafer excursions and high nuisance rates — especially in the form of microscratches — were present. They used KLA-Tencor’s AIT, a high throughput, double-darkfield inspection system equipped with RTC and High Resolution Defect Classification (HRDC) to monitor all copper layers for their most critical defect types: residual copper, copper precipitates, copper corrosion and slurry residue, and separate these from defect types of less importance: 24
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microscratches, previous-layer defects, particles and pattern defects. RTC was able to accomplish this discrimination with no discernible impact on throughput. A new feature called “trigger sampling” directed samples of defect images from wafers flagged by RTC, to undergo HRDC. HRDC examined a number of defects on the wafer to identify defects of interest (Figure 14). Whenever the population of any of these defect types exceeded its (layer-dependent) threshold, HRDC declared the tool out of control, and appropriate corrective measures were taken.5 AMD feels this is a practical solution for their “high volume high inspec-
tion sample production facility.” They reported a cycle time improvement of 30% within the copper CMP module, a reduction in false excursions, faster time to results, and a higher capture rate of critical defect types. With this new methodology, AMD Fab 30 has been running in production since November 2001, and considers the methodology part of their process of record.5 TI KFAB was using the AIT doubledarkfield inspection system to monitor full lots of a 130 nm copper single-damascene test-chip device, post CMP, when they discovered an excursion. Further analysis showed that most defects were coming from slot 24, the first wafer going into the CMP polisher, and they were able to address the problem (Figure 15). In this case, it was essential that they were monitoring the whole lot, or they would have had much more difficulty uncovering this first-wafer effect.7 TI’s general tool monitoring strategy is to dedicate the AIT double-darkfield inspection system to the copper CMP area in the copper “wet room,” and set up simple, speedy (40 wph) scans after via and trench CMP. They use recipes optimized for CMP surface
Phase I Example: Copper Seam Defect
Typical wafer map showing the defect distribution.
Typical SEM image of the seam defect.
Figure 13. Phase I, Copper Seam defect. This systematic defect was detected on the 2350, post copper CMP1.
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defects, which together with RTC, minimize the effects of nuisance counts. They inspect full lots, correlate in-line defects to electrical data, reduce outliers, and work to understand the process variation. The main defect type at via CMP has been slurry residue, while CMP scratches have dominated at trench CMP. When excursions are understood and brought into control, TI reduces the sampling rate. This methodology has driven a dramatic yield improvement at trench, and a more modest improvement at via. The methodology has also been implemented in TI’s 300 mm fab.7
inspection as wafer sampling demands increase (requiring higher throughput inspection) has been a successful tool utilization strategy in many fabs. What’s ahead?
Copper and low-κ dielectrics are enabling technologies for future product scaling. Yet, as critical dimensions are pushed down to
100 nm and beyond, some of the current challenges in electromigration and reliability are likely to become increasingly difficult. And new issues will arise. Karen Maex, strategic research coordinator for interconnect technologies at IMEC, recently discussed concerns about the specific resistivity, porosity of the low-κ dielectrics, and the lack of an effective test for electromigration.2
Identification/Reduction of Excursion Wafers CMP Trench Defect Per Slot
100% 90%
Average Defect Count
80%
Average Defect Count (after) Percent OOC
70%
Percent OOC (after)
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While specific methodologies and tool sets throughout the copper process are determined by many factors, such as product type, layer, and dominant defect species, a few general observations can be made. Extensive sampling is recommended for adequate monitoring of single-wafer excursions. Tracking defects by type is critical for yield learning and tool monitoring in the presence of high nuisance counts. Finally, utilizing a mix of high-resolution imaging and double-darkfield inspection, migrating to predominantly double-darkfield
Figure 14. SPC charts to catch defects of interest with IMPACT High Resolution Defect Classification.
A v g . De f e c t C ou n t
TI demonstrated the value of utilizing the 23xx high resolution imaging inspector as a reference system, ensuring the capture of all defect types of interest for that module, then using the resulting Pareto chart and defect map to set up appropriate recipes on the higher throughput, double-darkfield system.3, 7 They found that the double-darkfield system was able to capture all CMP defect types that the high resolution imaging system could capture. They also found that the high-resolution imaging technology was especially sensitive and uniquely effective in capturing ECD and integration defects (seam/edge voids, pattern defects, etc.).
19% 0% 1
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Slot Figure 15. CMP trench defect per slot.
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High throughput, high sensitivity double-darkfield UV inspection
As the semiconductor industry pushes the technology from 130 nm to 90 nm and beyond, increasing process complexity has given rise to new types of defects that are harder to find and identify. Rapid detection of single-wafer excursions, and tracking by defect type will continue to be key to successful production of leading-edge devices. The AITFUSION UV™, the latest evolution of the production-proven AIT family of high throughput, high sensitivity double darkfield inspection systems, was developed to address the special needs of 300 mm inspection and excursion monitoring at 100 nm design rules and below. The combination of double-darkfield optics, Adaptive Mode™ technology, increased data rate, and UV wavelength illumination deliver dramatic cost of ownership improvements. High defect capture, even on rough, grainy surfaces and in the presence of color variation, make it an ideal tool for cost-effective copper CMP, deposited films, and patterned-layer inspection. By increasing the amount of light scattered from small defects, this tool’s UV wavelength illumination supports critical sensitivity requirements for sub-100 nm design rule production. Spot migration — enabled by the AITFUSION UV’s increased sensitivity and advanced detection algorithms — contributes to significant throughput enhancements. Three independent collectors offer selectable polarizers and programmable spatial filters for superior noise suppression and complete capture of all critical defect types. Inline automatic defect classification (IMPACT™ iADC) technology extracts information in real time during inspection to classify all defects on a wafer. This allows better nuisance filtering for improved defect capture, trending by killer-defect type for faster, more reliable recognition of excursions, and defect review sample shaping. Spot Migration: Sensitivity and Throughput Advantages
Visible versus UV graphics
Tput AIT
FusionUV 3.5 µm
AIT
FusionUV 5 µm
Std Algo
HLAT/ChFus
Counts = 3583
Counts = 4174
18.3 - 20 wph
31.1 wph
Counts = 2368
AIT XP 5 µm
12 - 14 wph
Counts = 456
Trending by Defect Type 60.000
iADC Manual classification
50.000
<
40.000
30.000
20.000
Some companies are currently experimenting with mesoporous materials as low-κ dielectrics. These materials contain interconnected pores 2 nm in diameter or greater, a means of achieving even lower κ values. The problem with high porosity materials is that they are vulnerable to penetration by any stray molecules of gas or vapor. Such contamination would raise the effective κ value, and diminish the value of the presumed low-κ dielectric. To mitigate this potential problem, the seal between the dielectric and the barrier metal layer would have to be nearly perfect.2 Chemical vapor deposition (CVD) of the barrier-seed layer should be more successful than PVD for coating the irregular sidewalls presented by the porous low-κ dielectric — but CVD of Ta/TaN has its own set of problems such as contamination. The more likely candidate for managing deposition on the porous sidewalls is a relatively new technique called atomic layer deposition (ALD).10 However, perhaps a more serious problem than coverage of irregular sidewalls is having residual polymer left in the pores after etch — this may be a difficult integration problem.11
Lot-Wafer ID
Lot 16
Lot 15
Lot 13
Lot 14
Lot 11
Lot 10
Lot 09
Lot 08
Lot 07
Lot 06
Lot 05
Lot 04
Lot 02
Lot 03
Lot 01
10.000
Lot 12
Defect Density CM -2)
70.000
The effective resistivity specification of the International Technology Roadmap for Semiconductors for 90 nm to 32 nm may not be possible to meet, primarily because specific resistivity rises as line widths shrink. At linewidths of 100 nm the specific resistivity is twice that of a 200 nm line, and at 60 nm the specific resistivity triples. This effect may be related to the fact that the line widths are becoming comparable to the length of the mean free path of electrons in copper, promoting inelastic scattering at the copperbarrier sidewalls.2
Another probable upcoming challenge as the industry reaches the
C
90 nm and 65 nm nodes is copper fill. With a barrier/seed layer of 1100 Å (field thickness), thick enough to ensure adequate continuity on the via sidewalls, the opening to a 65 nm via would be shrunk to 150 Å, making copper fill very challenging.11 Voids will likely continue to be a dominant defect mechanism as design rules shrink and high-aspect ratios remain. Finally, a new method for testing for electromigration will likely be necessary. Currently these tests require high temperatures, which can cause film stress, especially in low-κ materials. Furthermore, grain growth can occur during a high temperature test, and subsequent relaxation of film stress may be accomplished by void formation.12 Without an effective test for electromigration, the reliability of the low-κ device will be uncertain.2 In the face of these challenges, accurate and timely defect detection becomes even more critical. As the industry moves forward, with solutions driven by new materials, new architecture and new processes, defect inspection must stay one step ahead. Shorter-wavelength light sources, reaching into the UV, will enable greater sensitivity (see sidebars). At the same time, new algorithms in data processing and data management will prove critical to success. Hardware and software improvements must work to keep throughput high and manage costs.
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High resolution imaging inspection
In-house characterization studies, substantiated by similar real-world studies in fabs, have demonstrated that high-resolution imaging is the preferred technology for detection of the smallest defects in all circuit geometries, but particularly in dense logic areas and where linewidths are smallest. The 23xx family of high resolution imaging inspection systems builds on a production-proven platform and is ideally suited for line monitoring of a wide range of layers that require the highest sensitivity. These include FEOL etch, photo (ADI, PCM, and PWQ applications), critical metal-etch, and critical copper CMP. Flexible UV illumination modes combine with high NA to enable inspection of all process layers with full sensitivity to the entire range of defects. Broadband offers high resolution and color “noise” suppression for capture of critical defects, while narrowband complements broadband inspection by providing enhanced resolution and contrast for capturing defects in the absence of color noise. Improved defect capture in dense geometry and in the presence of color variation is made possible with proprietary optical edge contrast noise-suppression technology. Sensitivity-enhancement and nuisance-rejection algorithms enable robust, high sensitivity with low nuisance rates. Mature autofocus subsystems and die-to-die run-time alignment algorithms deliver high sensitivity and low nuisance rates with the stability required for production usage. Inline automatic defect classification (IMPACT iADC) technology provides immediate feedback on defect types, and enables inline nuisance filtering, trending by defect type, and sample shaping for offline SEM review. Detection of Unique Defect Types
Corrosion defect detected at copper CMP1.
iADC for Faster Time to Results Total Defect Count
Defect of Interest
Summary
Copper interconnects and low-κ dielectrics are enabling technologies for device performance; at the same time they are accompanied by some new and difficult challenges. These challenges may deepen as devices evolve past the 130 nm node. Surface and sub-surface voids, slurry and clean residues are among the
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iADC turned on
0.13µm Spacer Etch This recipe bins the defect of interest, enabling smarter SEM review
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most common kinds of defects found in the parts of the copper process that begin with barrier/seed and end with cleaning. The new defect Pareto they create is founded on the material properties of copper and low-κ dielectrics. The architecture of the damascene process also contributes strongly in determining the defect Pareto charts for the new devices. Several successful fabs have shown that defect control in the copper process can be optimized by: (1) dense sampling to quickly manage single-wafer excursions, (2) tracking by defect type to mitigate the influence of nuisance defects such as microscratches, and (3) selecting a mix of inspection systems that enables capture of all relevant defect types while maintaining adequate throughput to meet cost of ownership targets. Acknowledgements
The authors would like to thank Arun Chatterjee for critical reading of this manuscript.
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References 1. Laura Peters, “Exploring Advanced Interconnect Reliability,” Semiconductor International. 2. Peter Clarke, “Challenges mounting over low-κ, copper interconnect, says researcher,” Semiconductor Business News, October 9, 2002. 3. Judy B. Shaw, Richard L. Guldi, Jeffrey Ritchison, Steve Oestreich, Kara Davis, Robert Fiordalice, “Voids, Pits and Copper,” Yield Management Solutions, Winter 2002. 4. Arun Chatterjee, “Copper Interconnect: Process Control Solutions,” presentation January, 2000. 5. Peter Stoeckl, Barry Saville, Jim Kavanagh, Thilo Dellwig, “Advanced Cu CMP Defect Excursion Control for Leading Edge Micro-Processor Manufacturing,” Yield Management Solutions, Winter 2002. 6. Kerstin Kaemmer, Grit Bonsdorf, Martin Tuckermann, and Jim Kavanagh, “Using real-time defect classification to investigate post-CMP cleaning processes,” Micro, October 2002. 7.Richard Guldi, Vince Korthuis, Mona Elssa, Frank Cataldi, Jeffrey Ritchison, Judy Shaw, Vikas Sachan, Steve Fanelli, Michael Vunguyen, Bob Fiordalice, “Process and Tool Monitoring in Copper/Low- κ CMP,” presented at the Yield Management Seminar, SEMICON West, 2002.
Yield Management Solutions
8. Raleigh Estrada, “Common Practices in Defect Control within the Copper Module.” 9. J u s t i n A n d e r s o n , J a s o n H e i n e , Matthew Soucek, Kwame Boahen and Jon Button, “Fast Ramp of a 130nm/300mm Copper Process with a Phased Yield Enhancement Methodology.” Yield management Seminar, SEMICON West, 2002. 10. John Forster, “Copper Barrier/ Seed,” presented at the November 20, 2002 meeting of the Thin Film User Group of the American Vacuum Society. 11. Imran Hashim, “Challenges for Nextgen Copper Barrier/Seed,” presented at the November 20, 2002 meeting of the Thin Film User Group of the American Vacuum Society. 12. Paul Besser, “Microstructure of Inlaid Copper Interconnect Lines: Characterization and Implications for Reliability,” presented at the November 20, 2002 meeting of the Thin Film User Group of the American Vacuum Society.
AIT XP The production workhorse for critical copper CMP, films and etch applications.
23XX The highest sensitivity and speed for resolving pattern transfer defects.
eS20XP Ultimate sensitivity for killer electrical defect identification.
µLoop eDo Inline electrical defect monitoring for the fastest root cause analysis.
Surfscan SP1 Front and backside unpatterned wafer inspection in a single scan.
Viper 24XX Automated capture of critical macro
There used to be a time when high-yield copper interconnects only existed in your imagination. But now, they can be a reality. KLA-Tencor has the tools and strategies to help you find, analyze, and fix the defects that most greatly impact device yield – such as via voiding, opens and shorts, and copper CMP corrosion. But that’s only part of the story. We also enable you to accurately and reliably measure film uniformity, giving you what you need for inline parametric control of copper/low-k film stacks. The result? A copper interconnect yield so high, you’ll want to shout it to the world.
defects on product wafers.
eV300 The SEM root cause analysis tool for HAR structures.
SpectraFx 100 Highest measurement precision for inline control of complex dielectric stacks.
For solutions and strategies to accelerate copper yield, visit our Cu Xpress website at www.kla-tencor.com/CuXpress
Accelerating Yield ©2002 KLA-Tencor Corporation