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M Gate Dielectric Control E

Overcoming the Gating Factor Inline Characterization of Nitride Gate Dielectric Films, with Prediction of Threshold Voltage James Chapman and Terry Letourneau, Micron Technologies Kwame Eason, Torsten Kaack, Xiafang Zhang, and Michael Slessor, KLA-Tencor Corporation

Inline electrical characterization is well-suited for studying and monitoring nitride dielectric films without requiring full wafer processing. Introduction

Experiment

The semiconductor industry strongly relies on its ability to continuously scale device feature size to increase performance and reduce power consumption as well as cost. One of the many challenges in CMOS scaling is the continued increase in the gate dielectric capacitance per unit area. This is accomplished by either reducing the gate dielectric thickness or increasing the gate dielectric constant (εr). Presently, the gate dielectric is silicon dioxide (SiO2), but in the ultra-thin gate oxide regime, utilization of pure SiO2 is increasingly difficult due to high gate leakage (Ig), oxide non-uniformity, surface roughness, and boron penetration from the p+ polysilicon electrodes. The nitridation of SiO2 has been successfully shown to improved device performance and tool commercialization.1-7

In this study, nitride oxides were produced on high quality p-types both after oxide on the plasma nitride gate oxide and after nitration on Si (100) wafers. Inline electrical measurements were performed using the KLA-Tencor Quantox and KLA-Tencor UV-1280SE. The measurement sequence within dielectric formation process is illustrated in Figure 1. The measurement principles of Corona-Oxide-Si (COS) technology are highly analogous to MOS C-V.8 The Quantox system is based on combining three non-contacting technologies: charged corona, vibrating Kelvin probe and a pulsed light source, as shown in Figure 2. Charged corona ions provide biasing, and emulate the functions of the MOS electrical contact. The Quantox EOT parameter (GateTox™) is determined from measured dielectric capacitance. The capacitance is determined from dQ/dV in accumulation in the COS system.9 The capacitance is converted to thickness using εr = 3.9. In an actual application, some second order corrections can be applied to acquire data to account for semiconductor

A key device performance metric is threshold voltage matching for NMOS and PMOS transistors. The PMOS, long channel threshold voltage (long Pch Vt) is utilized to characterize the effectiveness of the boron (B) penetration resistance of the dielectric; however, a significant drawback of transistor characterization is the need for costly and time-consuming processing. This work describes the correlation of long Pch Vt to inline electric and optical parameters obtained from the KLA-Tencor Quantox™ and UV-1280SE tools, respectively.

Gate Oxidation (Base OX)

Polysilicon Deposition

Anneal

SiON

Figure 1. Steps in generating the nitrided oxide film. UV-1280SE measurements taken at “1” and “3”, Quantox measurements taken at “3”.

12 1

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Kelvin Probe, VSurf

Corona Bias, Q +8kV

Surface Photovoltage, SPV LIGHT

Mechanical Oscillator

Corona Source,

Transient Detection

Kelvin Probe Electronics

CO3-, H30+

SPV

VSurf OXIDE P SILICON

1. Apply Q Corona Bias

2. Measure V S (=V OX + ψ)

Measure each ∆ Q

Probe vibration drives AC current:

I = V S - V kp

3. Stop vibration, flash light, and measure SPV

dC dt

Figure 2. Quantox COS measurement theor y.

band-bending. The tunneling voltage (Vtunnel) parameter is used to monitor the high-field leakage properties of the oxide. All dielectrics eventually reach a point where, as more and more charge is applied, the voltage across the dielectric reaches the maximum sustainable voltage, defined as Vtunnel. Vtunnel provides a good indication of the oxide integrity and quality in a manner similar to more traditional soft-breakdown measurements. The inline electrical measurements were done on monitor wafers, with one wafer per lot, five sites per wafer. The end of line electrical data comes from two to twelve probed wafers per lot, nine sites per wafer. The lot averages are used for correlation in this study. Results and discussion

I ≈C

dψ dt

4. Repeat

[

Equation 1. Textbook calculation of Vt for MOS transistor, from SZE 10 .

The experiment is designed to have the nitridation process as the major excursion mode for the purpose of evaluating this concept. The Pchannel Vt is chosen as the end of line monitor due to its sensitivity to B penetration resulting from the poly doping and source/drain formation steps. The long Pchannel transistor is chosen because the Vt is primary controlled by the gate, unlike the short channel device, where the turn on characteristics are heavy influenced by the drain voltage (phenomena known as drain induced barrier lowering10). This concept is illustrated in Figure 3.

Y = ax1 + bx2 + cx3 ... where Y is Vt; a, b, c are coefficients; and x1, x2, and x3 are inline parameters. The fit of the predicted data to the

Poly

Gate

Si Substrate

Long Channel Gate Controlled

]

√4åsiqNAΨB Cox

The predicted Vt is a model built on linear combinations of inline parameters. This approach (the model) uses a order Taylor Series expansion of the functional responses of Vt to the inline parameters. The model is developed using SAS JMP4 software and has the form of

Qeff + 2ΨB Cox +

The inline characterization parameters are affected by the physical thickness, composition, and quality (or leakage) of the film. Table 1 highlights the impact of film characteristics that result in a positive shift in the Vt, and the corresponding response of the inline parameters. The physical interpretations of these parameters are easily related to physical thickness, dielectric quality (or resistance to gate leakage) and nitrogen content.

The equation for threshold voltage is provided in Equation 1.10 The major contributions to the Vt are film capacitance (Cox), bulk Si band bending (YB) and substrate doping (NA). The later two (YB and NA) are controlled primarily by near surface doping of channel. The inline measurements are not sensitive to variations in surface doping of channel due to absence of any Vt adjusted doping on inline samples. Vt = öms –

Si Substrate

Short Channel Drain Controlled

Figure 3. Schematic highlighting the requirement of monitoring long Pchannel devices for B penetration resistance. Variations in nitridation will impact the degree of B penetration resistance.

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Causes for PMOS V1 to increase

Physical Thickness (↑)

Dielectric Quality (↑)

↑ ↑ ↑

↑ ↑

GateTox (EOT) -Vtunnel ρox Dit Reflectivity

Nitrogen Content (↑) ↓ ↓ ↑ ↓

↓

Table 1. Parameter response table variations in gate dielectric resulting in a PMOS V t increase.

actual data is presented in Figure 4. The model is based on 12 observations, which is the lower end of establishing a statistical population. The methodology is applied to three devices, each with varying base oxides and transistor process flows. A “super-set” of parameters

models range in total inline parameters, the least being two and the most being six (i.e. the model is based on two to six inline parameters). Model Optimize 1 Adjust R2 Optimize 2 Adjust R2 General Function Adjust R2

1 0.988 0.971 0.952 0.875 0.952 0.875

Device 2 0.795 0.549 0.986 0.970 0.986 0.970

3 0.839 0.645 0.976 0.948 0.976 0.948

Table 2. Table highlighting the optimization V t models for different devices. (Note that a “General Function” is a metric which has reasonably good application to all devices). The general function has the same parameters but different coefficients from device to device.

Conclusions Vt, S91 (0058 Actual

Actual by Predicted Plot -0.5 0.55 -0.6 -0.65 -0.7 -0.75

-0.8 -0.7 -0.6 -0.5 Vt, Predicted P=0.0002 RSq=0.99 RMSE=0.0104

-0.4

Summary of Fit RSquare RSquare Adj Root Mean Square Error Mean of Response Observations (or Sum Wgts)

0.986438 0.970163 0.01045 -0.61093 12

Summary of Fit Source Model Error C. Total

DF 6 5 11

Sum of Squares 0.03971326 0.00054600 0.04025926

Mean Square 0.006619 0.000109

F Ratio 60.6119 Prob>F 0.0002

Figure 4. Predicted versus Actual V t for one device. The R 2 fit is > 0.98

In this paper, nitrided oxide films have been characterized using inline non-contact electrical and optical measurements. The correlation obtained between the EoL Long Pchannel Vt actual and predicted (based on inline parameters) has resulted in R2 > 0.97 for individually optimized models. The individually optimized models incorporate ~6 inline parameters. A two parameter model has been successfully developed for one device with R2 > 0.90 and adjusted R2 > 0.88. These results support that the inline monitoring is sensitive to process variations that impact end of line measurements, when nitridation is the primary excursion mode. The correlation obtained between Long Pchannel Vt and model-based Quantox and UV-1280SE measurements demonstrates that inline electrical characterization is well suited for studying and monitoring nitrided dielectric films without requiring full wafer processing.

and adjusted R 2 > 0.97, with 12 observations.

References

have been determined for application to all data sets. The criteria for successful model generation is R2 > 0.9, with adjusted R2 > 0.85. Table 2 highlights the application of the “general” functional model to all three data sets. The application of this model means that the inline parameters comprising the model are constant; however, the coefficients in the models are different for the various devices. The general model functional form is provided in Equation 2. The optimized VT = f(SPV,Dit,Tox,∆Ref,Vtun,ρox,Qtotal) Equation 2. Super-set of parameters used in optimized model. The “General Function” uses six parameters.

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S. Hattangady et al., SPIE Symp. Microelec. Manf. (1998). 2. D.T. Grider, et al. VLSI 1997, p. 47-8. (1997). 3. Rodder-M, et al., IEDM 1998, p. 623-6. (1998). 4. K. Eason et al., 198th ECS Toronto, p195-203 (2000). 5. F. Cubaynes. IEEE ASMC 2002, TBP. 6. K. Eason et al., AVS ICMI, p251-3 (2002). 7. H.N. Al-Shareef, et al., 198th ECS Toronto, p210-213 (2000). 8. J. Guan et al., ECS, MA 99-2 p1106 (1999). 9. T. G. Miller, Semi. International, July (1995). 10. S. M. Sze, Semiconductor Devices Physics and Technology, 1985.

Upset over 90 nm gate stack control? Take two and accelerate yield as needed. It’s time to alleviate the pain of gate stack control. Because with gate dielectrics growing more complex and measuring less than 20 Å, you’re bound to experience problems with film thickness variations, composition, capacitance and leakage. So what’s the remedy? It’s a combination of optical metrology to control thickness and composition, and electrical metrology to control capacitance and leakage. And only KLA-Tencor has both. Giving you better gate stack control. While speeding your way to higher yields at 90 nm. Now that’s relief.

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