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Yield Management

S O L U T I O N S Yield Acceleration Strategies for the Semiconductor Industry

90 nm: How to Secure Your Future 13 13 COVER COVER STORY STORY — — E ELIMINATING LIMINATING B BURIED URIED Y YIELD IELD K KILLERS ILLERS 23 23 T TAKING AKING C CONTROL ONTROL OF OF P PROCESS ROCESS AT AT 65 65 NM NM

THE THE

C COPPER OPPER

32 AND RETICLE 32 T THE HE C CRYSTAL RYSTAL G GROWTH ROWTHAND RETICLE D DEGRADATION EGRADATION E EXPOSÉ XPOSÉ

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Taking Sides to Optimize Wafer Surface Uniformity Identify yield relevant defects on the wafer backside without having to sacrifice wafers.

23 Control of the Copper Process You thought the challenges at 130 nm were hard? 65 nm changes all the rules.

32 The Crystal Growth and Reticle Degradation Exposé Molecular contaminants on reticles can result in catastrophic yield loss.

39 Implementation of High Resolution Reticle Inspection in Wafer Fabs Streamline reticle qualification and improve the feedback loop with your mask shop.

45 Techniques for Evaluating Reticle Inspection Equipment for 130 nm Lithography and Beyond Questions everyone should ask in selecting reticle defect inspection equipment for wafer lithography applications.

50 Seeing Through the Haze Evaluate process performance with new surface information.

55 Simulating the Impact of Reticle Defects Don’t wait till it’s too late. Take advantage of a quick and accurate solution to ensure better photomask quality.

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Cover image by Terry Rieckhoff, KLA-Tencor

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13 Eliminating Buried Yield Killers It’s here. A new weapon to monitor and eliminate buried electrical defects. From development through volume production, electrical line monitoring shows great results.

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62 PROLITH v8.0 Advanced Lithography Simulation Software 63 MetriX 100 High Precision Metal Film Metrology

WEB Exclusives

MX 4.0 New Haze Analysis Software on Surfscan SP1

The Fine Line Between Design Rule Violations and reticle Defects Identifying process window marginalities of reticle designs.

Novel, At-design-rule, Via-to-metal Overlay Metrology New grating-style technology demonstrates superior perormance over conventional box-in-box targets.

www.kla-tencor.com/magazine Yield Management Solutions is published by KLA-Tencor Corporation.

To receive Yield Management Solutions, subscribe online at: www.kla-tencor.com/magazine

Sections

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Editorial: New Solutions for New Challenges: Going Beyond 90 nm

11 Spotlight on Lithography

For literature requests, visit: www.kla-tencor.com/company/inquiry MG-YMSSPR-01/04

22 Got a Litho Question? Ask the Experts

For information, visit: www.kla-tencor.com

44 Yield Management Seminar Series 61 Product Awards

Š2004 KLA-Tencor Corporation.

All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation.

Products in this document are identified by trademarks of their respective companies or organizations.

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New Solutions for New Challenges: A recent article in the Financial Times on the growth of cellular phone usage in Japan featured a photograph of hundreds of Japanese teenagers flashing their cellular phones to capture an image of their prime minister delivering an impassioned speech. For these young fans, the latest in digital technology offered the chance to hoard their own slice of history, instantly.

Take a look around you, and it quickly becomes evident that digital consumer electronics have become an integral part of our everyday lives. From digital cameras and cellular phones to personal digital assistants (PDAs) and high-definition televisions (HDTVs), digital consumer products are making the world more wireless and connected.

New applications for digital consumer electronics arise nearly every day to address new needs. Whoever would have thought the need or desire to use their cellular phone as a camera to take, transmit and receive pictures, like the Japanese teenagers mentioned above?

Yet, markets for such applications are emerging, and with digital consumer electronics becoming increasingly indispensable, you need not stretch your imagination too far to see a future where color displays are embedded in appliances and furniture; where freeways are controlled by vast electronic networks to ensure smooth traffic flow and minimize accidents; where future generations of cars will probably have drive-bywire systems not unlike Boeing 777s; and, where an

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entire forensic laboratory can be built onto a microchip. In the more immediate future, Intel envisions a seamless, wireless home network that can handle music, photos, and video content available anytime, anywhere and on any device in the home.

In this increasingly digitized world, having an electronic device that is anything less than 100 percent reliable is not an option. The financial and personal loss caused by the widespread occurrence of devices that are unreliable or fail altogether in the field would be truly grim. However, while the reality of a fully connected world is still years away, the prospects of poor device reliability and product failure in the field are here today. As the semiconductor industry ramps to 90-nm production and engages in process development at the 65-nm node, reliability-related problems such as micro voids, electro-migration, stress migration, de-lamination and cracking, can no longer be contained in development, and are arising at random during production. The introduction of dozens of new and exotic materials at these design rules to augment device performance and speed, such as silicon-on-insulator (SOI), strained silicon, atomic layer deposition (ALD) barriers and new metal compounds, present their own unique process integration issues that ultimately can further impair reliability. And while these issues will not cause flying commuter vehicles to crash into the Earth today, they present very real obstacles to realizing the dream of a truly interconnected world.

Yield Management S O L U T I O N S

EDITOR-IN-CHIEF Uma Subramaniam MANAGING EDITOR Aparjot Dehal

Going beyond 90 nm

CONTRIBUTING EDITORS David Moreno Tom Salinas

This latest issue of Yield Management Solutions, explores several radically new process control methodologies that are being implemented to help chipmakers address these reliability issues. Our cover story, Eliminating Buried Yield Killers (page 13), presents a compelling argument for implementing e-beam inspection in development, ramp, and production to mitigate new sources of reliability problems.

Taking Control of the Copper Process (page 23) explores new metrology techniques— including inline copper interconnect metrology—to minimize the impact of process variations on long-term device reliability and short-term yields.

ART DIRECTOR AND PRODUCTION MANAGER Carlos Hueso D E S I G N C O N S U LTA N T Terry Rieckhoff Mike Garnica C I R C U L AT I O N E D I T O R Nancy Williams

So, while the technology visionaries out there are dreaming up a new world order, your fortune cookie indicates that there are new process control solutions you can take advantage of to bring the latest generation gizmos and gadgets to market in time to meet the demands of tech-hungry consumers.

KLA-Tencor Worldwide

Happy New Year!

C O R P O R AT E H E A D Q U A R T E R S

KLA-Tencor Corporation 160 Rio Robles San Jose, California 95134 408.875.3000 I N T E R N AT I O N A L O F F I C E S

KLA-Tencor France SARL Evry Cedex, France 33 16 936 6969 KLA-Tencor GmbH Munich, Germany 49 89 8902 170 KLA-Tencor (Israel) Corporation Migdal Ha’Emek, Israel 972 6 6449449

Uma Subramaniam Editor-in-chief

KLA-Tencor Japan Ltd. Yokohama, Japan 81 45 335 8200 KLA-Tencor Korea Inc. Seoul, Korea 822 41 50552 KLA-Tencor (Malaysia) Sdn. Bhd. Johor Bahru, Malaysia 607 557 1946 KLA-Tencor (Singapore) Pte. Ltd. Singapore 65 782 6788 KLA-Tencor Taiwan Branch Hsinchu, Taiwan 886 35 335163 KLA-Tencor Limited Wokingham, United Kingdom 44 118 936 5700

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Taking Sides to Optimize Wafer Surface Uniformity Backside Inspection Applications In Lithography Kay Lederer, Matthias Scholze, Ulrich Strohbach, Infineon Technologies Andreas Wocko, Thomas Reuter, Angela Schoenauer, KLA-Tencor Corporation

As the semiconductor industry ramps to sub-130 nm production capacity,1 the need for optimal uniformity across the wafer surface becomes a very important topic in lithography. Due to the tightening of depth of focus requirements the process window required to be able to print the required structure leaves little or no room for any localized deviation in the wafer uniformity.

For 300 mm semiconductor device manufacturing, this resulted in the use of double-side polished, sometimes called “super flat� wafers.

This paper will discuss methods to identify yield relevant defects on the wafer backside without having to sacrifice wafers.

It is based on recent studies carried out at both Infineon Semiconductor 200 and 300 mm fabs in Dresden to characterize the need and the effectiveness of wafer backside defect inspection using the backside inspection module (BSIM) on the Surfscan SP1DLS.

Introduction

In contrast to bare wafer inspection strategies, semiconductor manufacturers are still in the early learning stages of implementing backside inspections of silicon wafers. Backside defects in the form of particles or topography are highly relevant to photolithography processing. Particularly in 300 mm photolithography, where double-sided polished wafers are used, such defects reduce surface uniformity and cause undesired effects on the exposure chuck. The two most common effects are focus spots and vacuum failures.

For critical lithography layers with small process windows, focus spots have a direct impact on yield. Vacuum failures result in tool downtime, which impairs manufacturing efficiency. Moreover, backside contamination often results in time-consuming cleaning 6

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procedures of the exposure tool chuck. Experience indicates that 200 mm and 300 mm manufacturing share largely the same backside issues.

The effects that backside defects can have on the devices built on the frontside of the wafer are largely known, but have not been systematically characterized. This is mainly because traditional backside inspection methods require wafers to be manually turned upside down with a vacuum wand to conduct a thorough inspection, which damages the devices on the frontside and could contaminate the inspection tool.

Working with KLA-Tencor, Infineon Semiconductor investigated the effectiveness of a new inspection methodology for identifying yield-relevant defects on the wafer backside in an automated and non-destructive way at its 200 mm and 300 mm fabs in Dresden.

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The first step in implementing backside inspection is to analyze the surface quality of the wafer backside and determine the sensitivity required for capturing defects of interest (process tool fingerprints). We did this by depositing polystyrene latex spheres onto the backside of a test wafer and adjusting the recipe parameters to achieve at least a 3:1 signal-to-noise ratio.1

Next, we created a database of tool fingerprints from all of the process tools. This is usually done during tool qualification. Using the BSIM option reduces the number of test wafers needed, since the same wafers can be used for front (PwP) and backside contamination tests.

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Results and Discussion

Study 1: Characterization of backside properties on 300 mm wafers For this study, we created one recipe for pre- and postlithography inspections maintaining its sensitivity to typical signatures. Three lots were flagged for inspection at critical lithography steps. All wafers were measured before and after lithography on the SP1 BSIM using the same recipe. The lot results were mirrored on the tool and sent to the fab-wide defect database in KLA-Results Format (KLARF).

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The goal of our second study was to identify the root cause of systematic focus spots detected on 200 mm patterned wafers at various stages in the front end of the manufacturing process. The frontsides of the product wafers were measured inline on a KLA-Tencor AIT II double darkfield illumination system. Defect review and characterization were carried out on a CRS confocal microscope. Offline data analysis, including correlation between front- and backside defects, was done using Klarity Defect software. The backsides were measured on an SP1DLS inspection system with BSIM capability.

The SP1DLS has the same functionality as the SP1 for darkfield measurements, but provides increased overall sensitivity. For rough 200 mm wafer backsides, the best results were obtained using S polarization for both the incident light and dual (wide and narrow) collection channels. To further suppress background scatter and enhance the signal-to-noise ratio, a 20 or 40 degree aperture was employed. The defect threshold was set between 0.2 µm and 0.3 µm.

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Figure 1. Effect of defect threshold on the resolution of a wafer handler

Defect Count

For our first experiment, we investigated the backside quality of 300 mm double-sided polished process wafers before and after lithography. The backsides were inspected using a KLA-Tencor Surfscan SP1 unpatterned inspection system with a new backside inspection module (BSIM) option. BSIM employs edge-only automated wafer handling throughout the measurement process, so it enables product wafers to be flipped and measured without destroying the un-scanned side. Double-sided polished wafers can be treated the same as bare silicon wafers, with the exception that they have a higher defect threshold value. This value is dependent upon the desired resolution for detecting tool fingerprints (Figure 1) and data management limitations. For this study, the optical configuration used on the SP1 included the oblique incidence mode and P-U-U polarizations. Defect thresholds were between 0.5 µm and 1.0 µm.

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StepID Figure 2. Pre-lithography backside defect counts — defects that were present before the lithography step are shown in light red.

Data analysis revealed that the number of backside defects added to the wafers between adjacent lithography steps (Figure 2) were considerably higher than the number added during the lithography process (Figure 3).

Furthermore, we observed that the backside defect count steadily increased throughout the manufacturing process on all lots.

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We also found that defect density was affected by the wafer’s position in the lot. The first wafers tended to have the most backside defects, followed by wafers that were handled more frequently during the process flow.

This tendency (Figure 4) was seen on all lots at each inspection point. We interpreted this to be the result of the “cleaning effects” that the first wafers in a lot can exert on production tools.

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Systematic focus spots were previously identified through patterned wafer inspection and manual classification.

Since the focus spots were visible at multiple layers, the actual source was not immediately obvious. However, backside contamination was considered a possibility, since the defect signature appeared in the same position on each layer. A tool commonality study was first conducted to determine the source, but did not reveal a clear candidate. Finally, a systematic investigation of backside defects (using the SP1 with BSIM) and their correlation to the front side revealed the root cause of the problem.

In this investigation, the wafers with systematic focus spots were measured on the SP1 with BSIM in high sensitivity mode. The defect result files were then “mirrored” using software on the SP1 and transferred to the defect database for analysis. The backside wafer maps all showed distinct wafer handler signatures, which could be compared to the fab’s previously established database of process tool fingerprints (in the form of patterned wafer maps). The patterned wafer maps were then overlaid with the mirrored SP1 wafer maps. Defects common to both maps were flagged for further review to determine their size, height and type (Figure 6).

These defects — most of which were several microns in size and depth — were identified as holes caused by damage to the silicon on the backside of the wafers, as shown in Figure 7.

52665 38272 33304 22849 23672 25069 22245 27409 20541 29102 21815 33441 24785 42372 32621 23326 28494 23336 31781 27502 20716 20193 29150 28832 21115

Figure 4. Defect count by wafer position in lot.

Overlaying the backside defect maps of all measured wafers (Figure 5, left) showed a considerably higher backside defect count than the stacked defect maps of wafers that were not handled as often (Figure 5, right).

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Figure 6. a) SP1 map (chuck signatures, coordinates mirrored); b) front-side, patterned-wafer inspection; c) overlay results of common defects.

Figure 5. Typical handling wafer at left. “Normal” wafer at right.

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We concluded that this damage was the cause of the focus spots. A comparison of the inspection wafer maps with the process tool fingerprint catalogue identified the wafer handler type responsible for causing the defects. Several handlers of this particular type were later found to be damaging the wafers, which explained why the tool commonality study was not successful. By

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studying the defect mechanism, we determined that the defects were also being enlarged through subsequent process steps, thereby increasing their impact on the devices on the frontside of the wafer.

Once the source was identified and the defect mechanism understood, a simple modification to the wafer handler solved the problem. The yield impact of this defect mechanism was determined to be one to two percent for each affected wafer over a ten-week period until the root cause was fixed.

Going forward

Preventing backside contamination from creating problems in the first place is ideal. Although backside contamination is present at all layers, it is not always relevant to yield. Adding a clean to remove backside contaminants can become costly, and does not remove all defects. 2,3 In addition, scratches and pitting can sometimes be made larger by the cleaning process. Thus, it is important to know when corrective action should be taken.

A good place to begin is at the most critical lithography step, or at the step that has the most focus spots.

As with traditional pattern wafer monitoring, only a sample of wafers is inspected. A monitoring strategy should also include excursion control and baseline defectivity reduction programs.4

Prevention of focus spots Pre-lithography — Backside Inspection: The goal here is to determine whether large random backside defects exist on the wafers that could cause a problem during the lithography process, and, if so, trigger corrective

Lithography Process

Figure 8. Decision flow to initiate pre-lithography backside cleaning.

action before the wafers reach the exposure tool. A sample of five to ten wafers can be taken per lot depending on defectivity level and variability. Random defectivity should be separated from tool fingerprint signatures, and large particles should be separated from small particles.

Thus, a backside clean will only be triggered when large, random defectivity occurs in order to avoid tool aborts and random focus spots. The collected data is sent to the defect database for further analysis, since systematic focus spots cannot be removed by a clean if they are caused by damage (Figure 8).

Post-lithography — Frontside/Backside Inspection:

Here, the goal is to identify whether focus spots are generated during lithography, and, if so, trigger appropriate corrective action, such as a chuck clean on exposure tools and rework of the affected wafers. Inspection is carried out on macro-defect or micro-defect inspection tools using the same wafers as above to conduct pre- and post-comparisons. Focus spots are separated from other defect types, and will trigger a backside inspection based on the number of identified focus spots. The data is sent to the defect database to be overlaid with the mirrored backside wafer maps from the pre-lithography inspection step (Figure 9).

Wafer backside signature analysis It is clear that the particle or defect signatures on the wafer backside are key to identifying the root causes of Spring 2004

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causes process difficulties or even yield loss. This is particularly relevant to the “super flat” 300 mm wafers which have challenging specifications for wafer surface uniformity.

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Figure 9. Decision flow to initiate corrective actions based on number of focus spots.

a particular issue. The next logical step is to automate current manual steps. The difficulty in achieving this lies in being able to separate and automatically classify the individual signatures without treating them as clustered defects.6 Investigations are currently under way to determine the best methodologies in implementing spatial signal analysis in a production environment.

However, the signatures alone are not conclusive evidence of yield loss. It is the combination of knowledge gained from inline pattern wafer inspection, yield analysis and the identification of the tool signatures that determines when to take corrective action.

Automating the spatial signature analysis, frontside to backside correlation, and signature to tool correlation are the next important steps towards implementing backside inspection into a production environment.

Conclusions

Tight depth of focus requirements in high-end semiconductor manufacturing photolithography leaves little or no room for any localized deviation in the wafer uniformity. At feature sizes of 110 nm and below, any contamination or topography variation on a wafer backside

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Focusing on 300 mm “super-flat” wafer photolithography, we identified that the backside defect count steadily increases throughout the manufacturing process. There are two major sources of backside defects: defect generation by deposition or furnace processes, and backside contamination by wafer handling. A non-destructive analysis of tool or handler defect signatures on the wafer backsides was facilitated using the BSIM on the Surfscan SP1DLS. A correlation of backside defect data to front side patterned wafer inspection revealed that not all defect issues on a wafer backside are relevant to the photolithographic process.

The effect of backside defects is dependent on their position on the wafer, as well as their size, shape and orientation.

The most powerful outcome of backside defect inspection is the identification of spatial defect signatures and their correlation to tool or process fingerprints. The next step is to automate the identification, analysis and correlation of such backside defect signatures to tools and processes.

Acknowledgements

The authors wish to thank their colleagues at Infineon Technologies in Dresden and F. Rogers at KLA-Tencor Corporation for their input.

A version of this article was also presented at the 2003 ASMC Conference, March 31 – April 1, 2003, Munich, Germany.

References 1. Surfscan SP1 Online Publications, User Edition Book-onBoard for SW. Version 3.8.

2. G. Vereeke, et al., “The Influence of Hardware and Chemistry on the Removal of Nanoparticles in a Megasonic Cleaning Tank,” UCPSSS 2002, Ostende, Belgium.

3. M. Lester, “New Single Wafer Processes Offer Alternative Backside Cleans,” Semiconductor International, January 2001.

4. L. Milor, Y. Peng and J. Segal, “Reducing Baseline Defect Density Through Modeling Random Defect Limited Yield,” January 2000.

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Chris Mack Receives Prestigious SEMI Award This past December, Semiconductor Equipment and Materials International (SEMI) honored KLA-Tencor’s very own Chris Mack for his significant contributions to the advancement of semiconductor manufacturing technology at the 24th Annual SEMI Dinner and Award Ceremony, held at the Marriott Hotel in Santa Clara, California. at SEMATECH working in the areas of deep ultraviolet (UV) photoresist characterization and phase-shifting mask optimization. He helped to found FINLE Technologies in 1990, and joined full-time as president and chief technology officer in 1992. Under his stewardship, PROLITH — FINLE’s flagship product — became the de facto industry standard for lithography modeling and data analysis software, The SEMI Award for North and it continues to remain America honors individuals so to this day. When FINLE who have made significant SEMI president and CEO Stanley Meyers presents Chris was acquired by KLA-Tencor technical contributions to Mack with the 2003 SEMI Award for North America. in 2000, Mack stayed with the semiconductor industry. the organization, where Past award recipients include today he heads KLA-Tencor’s advanced lithography Walter Benzing and Mike McNealy for epitaxial silicon process control development efforts as vice president deposition; Dan Maydan, Sass Somekh and David Wang of lithography technology. for plasma etch; and KLA-Tencor’s own Kenneth Levy for automated photomask inspection.

In our next issue of Yield Management Solutions, we’ll sit down with Chris Mack for an exclusive interview In addition to his long list of academic credentials, Mack to hear about his early years in the semiconductor has had a noteworthy career in the microelectronics industry; his experiences as president of FINLE; and industry. In 1983, he joined the U.S. Department of how life for him has changed since he transitioned Defense, where he began his work in optical lithography into his current role at KLA-Tencor. research at the DOD’s Microelectronics Research Laboratory. From 1990 to 1991, Mack was on assignment Specifically, Mack was recognized for his development of software programs that have enabled process engineers to increase productivity of the lithography process.

His work over the years has driven many changes in the development, production and optimization of photomasks, lithography systems, photoresists and lithography metrology.

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Eliminating Buried Yield Killers e-Beam Inspection: Best Practices for Copper Logic and Foundry Fabs1 David W. Price, Todd Henry, and Robert Fiordalice, KLA-Tencor Corporation

Monitoring and eliminating buried electrical defects has become critical for 130 nm copper devices and below. As a result, electron-beam inspection is being widely adopted for development, ramp, and volume production monitoring. In this paper we describe current implementation of e-beam inspection technology for copper logic and foundry fabs, including specific case studies which illustrate the benefits of applying e-beam inspection technology from development through volume production. We also describe methods used to overcome common implementation hurdles. We then pair best practices with new advances in e-beam inspection technology to model the optimal implementation for a hypothetical 20,000 WSPM 300 mm fab.

Introduction

Challenges for production of 130 nm copper (Cu) devices stem from shrinking process windows, complex integration schemes, and the introduction of novel materials. A key issue in manufacturing these devices is that many of the yield-relevant defect types are not detectable using conventional optical inspection tools. Examples include buried Cu via voids, under-etched vias and trenches, and organic residue at the bottom of high aspect ratio dual damascene vias and trenches. E-beam inspection (EBI) can detect these buried electrical defects through the use of voltage contrast (VC) by detecting interruptions in the interconnect path to ground (Figure 1).2 In VC mode EBI is essentially an inline electrical test on product wafers.

EBI has been widely adopted by leading-edge fabs as an engineering analysis tool during development and ramp. For example, 30 out of 35 Cu fabs worldwide have at least one EBI tool being used in this manner. EBI engineering analysis applications have been documented in the literature by several leading chipmakers, including Toshiba,3 ST Microelectronics,4 and TSMC.5 Spring 2004

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These results are predicated on the performance of the KLA-Tencor eS30, an EBI tool which incorporates KLA-Tencor’s latest technology for development, ramp and volume production applications.

Best practices for EBI implementation

Users typically employ higher sensitivity (small pixel) recipes when building the baseline defect Paretos.

In development, when defect densities are high, accurate baseline Paretos can be developed by small area inspections (<10 percent of wafer). As systematic problems are resolved and defect densities decrease, more inspection area is needed to attain a statistically valid baseline Pareto.

It is important to note, however, that To assess best practices while the sampling requirements we conducted a survey change as a function of the defect Figure 1. EBI is the only technology that can detect buried of current EBI utilizadensity, in almost every case fabs will electrical defects inline on product wafers. Examples of these tion within the Cu fab still sample across the entire wafer to defects include buried voids, under-etch, and residue in highinstalled base.

In the obtain wafer-level defect signatures. aspect ratio contacts. back end of line (BEOL), Such “full wafer signatures” are top applications consisobtained by inspecting alternate die Recently, examples of production tently included the minimum pitch rows, using run-time swath skipping, implementation of e-beam inspecVia 1 module. At Via 1 the most or employing area-accelerated (eD0) tion for electrical line monitoring have critical defect types were voids, test structures such as those dessurfaced, including papers from under-etched, over-etched or misscribed by Weiner et al.11 A typical Motorola,6 Texas Instruments,7 ing vias, and residue.

Inspections for eS30 volume production inspection Samsung,8 and Altis.9 This trend this module are most commonly at sample plan is shown in Figure 2. appears to be driven by the recurVia 1 etch (for photo/etch dominatrence of EBI-unique defects in Table 1 summarizes the production ed defectivity) and the subsequent production, particularly at 130 nm line monitor utilization of e-beam Cu CMP step (Via 1 CMP or M2 design rules and below. FurtherCMP for single and dual more, volume production applications damascene processes, Die Layout are expected to accelerate with the respectively).

Upper introduction of a new generation of metal Cu CMP and high speed EBI tools. For example, SRAM via/trench etch inspecthe new KLA-Tencor eS30 is at least tions are also important two times faster than the previousdespite the looser design Logic generation EBI tool (eS20XP), and rule, due to film thickcan be as much as 12 times faster for ness variations and intecertain sample plans. Improvements Inspected Area gration problems. to production worthiness, defect binning, and ease-of-use have also The most common EBI Figure 2. eS30 throughput is sufficient for volume production facilitated implementation in propoint in the front end of monitoring of 300 mm wafers. Typical production sample duction implementation.10 line (FEOL) is contact, plan: 35 percent of die area (logic portion), full 300 mm whether at etch or at wafer. Total inspection time including overhead is 55 minutes.

In the following sections we will tungsten (W) CMP. describe some of the current best Driven by shallow juncCobalt/ Contact M1 M2 M3+ practices for EBI implementation in Nickel Etch or Via 1 tion development, e-beam CMP CMP CMP Silicide CMP Cu logic and foundry fabs; these will inspection of the cobalt Percentage of Fabs include a benchmarking survey and silicide (CoSi2) or nickel utilizing EBI line 33% 67% 44% 56% 100% 67% at key representative case studies. Finally, silicide (NiSi) modules monitoring inspection steps we model the ideal fab EBI impleare also rapidly becoming mentation and determine the correTable 1. Percentage of nine sur veyed fabs applying EBI line critical applications. sponding return on investment. monitoring at critical layers.

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inspection for nine Cu fabs. Line monitor wafer sampling strategies are dependent upon the size of the yield excursion that is to be detected.

Many customers who employ critical area models quickly conclude that large-sized chips require more wafer inspection area in order to find smaller excursions. Modeling and empirical fab data indicate that for most volume production monitoring applications sufficient area can be inspected on the eS30 in a one-hour inspection time.

Faster development and ramp

EBI enables users to accelerate yield learning during development and ramp by providing an inline measurement of yield-relevant defectivity.

In general, the key to successful inline yield learning cycles is a complete understanding of the distribution and frequency of killer defects.

Fabs have long used optical inspection tools to develop such understanding for physical defects. However, the transition to damascene Cu structures fundamentally increased the importance of buried electrical defects, such as Cu voids and under-etched vias.

To address this need, most Cu fabs have adopted EBI over the last five years. This technology provides rapid quantification of yield-relevant, electrical defectivity to the engineering teams conducting process window splits and integration studies. In addition, EBI provides faster localization of yield-relevant defect sites. Compared to end-of-line wafer probe and conventional failure analysis, inline EBI can reduce the average time of a learning cycle from weeks to days.

The benefits of this approach are illustrated by Mizuta and Amai.3 They describe how Toshiba used VC inspection during development and ramp of their 90 nm Cu process. In particular, the authors implemented

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Overcoming post Cu CMP queue time constraints Table 1 indicates that the some of the most frequent e-beam inspection points are following Cu CMP. However, many Cu CMP processes impose a queue time constraint to minimize the risk of corrosion. Typically, this constraint is on the order of four to 12 hours from finishing the final postpolish scrub until beginning the etch stop layer (silicon nitride or silicon oxynitride) deposition. Cu fabs employ several strategies to implement post Cu CMP EBI monitors within the imposed cycle time restrictions.

The most common strategy is to implement the post Cu CMP EBI monitor after the nitride cap has been deposited. This is frequently the fab’s preferred approach because it removes the queue time constraint altogether.

In some cases, however, this can be a more challenging inspection to perform. Imaging through the nitride cap layer requires a higher than normal landing energy, e.g. 1800eV for a 400Å cap. Furthermore, the nitride cap makes it more difficult to control surface charging; in many cases, some form of active charge control, such as the e-Control™ capability found on the eS25 and eS30, is required.

Electron Beam Nitride cap to protect Cu from corrosion

Cu M1 CMP post Cap LE=1000eV No contrast

M1 CMP post Cap LE=1800eV Good contrast

After Cu CMP, a nitride layer is deposited on top to protect Cu from corrosion. A higher landing energy is needed to penetrate the nitride cap and detect defects of interest. Active charge control (e.g., e-Control on KLA-Tencor eS30) is also required to control surface potential.

Another approach is to simply perform the inspection within the allotted queue time. Most production EBI monitors take only about one hour per wafer which, in most cases, will leave sufficient time for other inspection and metrology steps that must also be performed within the queue time.

However, the non-steady flow of material through the Cu module may periodically result in a queue at the EBI tool. It then becomes necessary to balance the risk of violating the queue time on some lots against the risk of skipping inspection and missing an excursion.

A third approach is to split inspected wafers from the lot after Cu CMP: the remainder of the lot is capped immediately, while the inspected wafers queue for inspection before being rejoined. The latter method usually requires fab automation typical of advanced 300 mm fabs.

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Getting to the defect of interest Identifying a defect of interest requires both the inspection sensitivity to detect the defect, and the ability to separate it from the many other defect types in a typical inspection result. The latter is particularly important for e-beam inspection (EBI) which, because of its inherently high sensitivity, is able to detect a wide variety of defect types.

KLA-Tencor uses a sequential defect-segregation approach on the eS30 which provides a powerful and flexible combination of imaging configurations and algorithms to quickly highlight defects of interest, suppress nuisance defects, and then bin the defects not of interest. This allows an EBI user to efficiently resolve even the tail of the defect Pareto, and to control the line based on the most relevant yield-impacting contributors.

This method consists of three elements: optimized imaging conditions; nuisance filtering and binning algorithms that take place during the inspection; and post-inspection sorting capability that allows the user to generate the most useful sample plan for high resolution review on the eS30.

Widest Range of Imaging Conditions

Real-Time Binning Algos

Review Sorting Tools

WISE-NF

best known methods to overcome two common EBI implementation challenges: throughput and defect separation. First, they optimized throughput and sampling by characterizing capture rate as a function of pixel size. They showed that an 86 percent capture rate could be achieved using a large (0.30 µm) pixel size for the primary defects of interest (VC lines, islands). As a result, they were able to implement full-wafer sampling (eight percent die area) in a 50-minute inspection on the eS20XP. The authors also demonstrate how inline automatic defect classification (iADC) can eliminate the need for manual review by binning several types of VC and physical defects with greater than 95 percent accuracy and purity. In total, Toshiba reported that EBI enabled them to achieve a faster killer-defect analysis cycle, thereby ramping their 90 nm process about 25 percent faster than their 130 nm process (Figure 3).3

iADC

• Enhance DOI signal • Suppress non-DOI

• Filter nuisance • Bin DOI’s

Rule-based sorting creates the most relevant review sample plan

0.35 um 0.25 um 0.18 um 0.13 um 0.09 um

Defect Density

BMK’s from>60 sites WW

A complete EBI defect segregation strategy requires optimized imaging conditions, real-time binning algorithms, and efficient post-inspection review capability.

Inspection imaging conditions The inspection imaging conditions play a critical role in highlighting defects of interest and suppressing noise sources. EBI imaging of defects depends on several variables. For example, the landing energy, beam current, and the field conditions imposed on the wafer surface can turn on and off certain voltage contrast signals by imposing a forward or reverse bias of the structures. Different imaging configurations may be set up as different tests to isolate specific electrical signals.

Landing energy is also important because it affects the relative secondary electron yield and, hence, material contrast of the surface. Furthermore, landing energy can affect the depth of penetration and edge contrast. This ability to tune the material contrast, depth of penetration, and edge contrast allows the user to preferentially detect certain physical defect types.

Time Figure 3. EBI provided Toshiba with the ability to detect electrical defects in-line, helping them ramp their 90 nm process about 25 percent faster than their 130 nm process ramp. 3

Baseline yield improvement and excursion control in the BEOL

Buried electrical defects are usually first found during development, but also recur in volume production. The voltage contrast mode available in EBI provides a unique capability to detect

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During ramp and early into production, TI DMOS6 noticed yield issues at final test for a DSP product.

Optical inline inspections detected defect signatures in the gate loop which were unconfirmed by inline probe, post Metal 2 CMP. When the flagged wafers were inspected using EBI in VC mode post Metal 2 CMP, open contacts were verified. Root cause was determined to be a defect type called poly pillars (Figure 4a), which occurred at a defect density below that which could be resolved by inline probe. After the process was corrected, a lower-cost optical inspection was introduced at sidewall etch to control excursions.7 During this investigation a second buried, open-via defect type was discovered using EBI on the same wafers. Via contamination (Figure 4b) was found to be blocking the sputter etch prior to barrier metal deposition, resulting in un-landed vias. This buried defect could not be detected optically, so an EBI inspection point

Figure 4. Open contacts and via defects were causing yield problems at TI DMOS6. While the poly pillar defect (a) can be monitored in production using a traditional optical inspection

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Detection can also be weighted to preferentially detect VC defects by selecting an appropriate pixel size for the inspection. Increasing pixel size reduces the capture of small physical defects while still maintaining a high capture rate for most VC defects (and at very fast inspection speeds). Finally, effective charge control is also necessary to minimize nuisance defects and to allow aggressive thresholds.

The KLA-Tencor eS30, with the widest range of possible imaging configurations, provides users with the unique capability to implement the defect detection scheme most appropriate to the problem at hand.

Run-time algorithms In some cases, the optimal imaging conditions may not completely suppress nuisance defects. Therefore, a second level of nuisance filtering has been added to the eS30 platform. This filter, known as WISE™ (Wafer Inspection Sensitivity Enhancer), allows the user to reject unwanted defects during inspection.

The remaining defects of interest (i.e., those that are not suppressed by the imaging and pass through the WISE nuisance filter) can then be separated into different bins through the application of iADC, or inline automatic defect classification. iADC operates on the as-detected, multipixel image “patches” of the wafer at each defect location. A common eS30 iADC implementation is to bin defects into dark VC, bright VC, multiple VC, and physical defects.

Review sorting algorithms The final binning operation is to sort the defects using a rules-based approach for selected manual review on the eS30. The majority of Cu fabs perform some manual review on the EBI tool due to the built-in high resolution SEM imaging, state-of-the-art VC imaging capability, and simply the convenience and time savings of not having to move the wafer to a different tool.

The review sorting tools allow the user to apply further granularity to the bins created by iADC. Unlike the run-time algorithms, these are rule-based and so no previous setup is required. This is useful for cases in which defects resemble one another, e.g., single dark VC and small dark particle.

was introduced inline to monitor for open vias. This log-point enabled TI to reduce the magnitude and frequency of openvia excursions and drove a baseline yield improvement of 15 to 20 percent (Figure 5).7

Darl VC D0

these buried defects on product wafers inline — catching excursions that otherwise would not be found until final test. Many Cu fabs use this e-beam inline electrical inspection to improve baseline yield and to monitor for excursions. For example, Texas Instruments’ 300 mm DMOS6 fab used EBI for volume production of their 130 nm devices, and for prototyping runs of 90 nm devices.

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Avg. D0 Trend

Individual Production Lots

after sidewall etch, the via contamination defect

Figure 5. Texas Instruments DMOS6 improved their baseline yield by 15 to 20 percent by using EBI

requires EBI monitoring in volume production. 7

monitoring at Metal 2 CMP. This chart shows the open-via (dark VC) defect density trend over time. 7

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Defect Density Yield

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typical 300 mm, 20,000 WSPM, sub-130 nm design rule Cu logic fab. In this implementation there are three eS30 EBI tools: one tool for FEOL monitoring (silicide and contact), one tool for BEOL monitoring (Cu CMP and via etch steps), and one tool for engineering analysis. A dedicated engineering analysis tool is necessary to drive baseline yield improvements throughout the technology life-cycle; this tool also would function as a backup for the production tools during maintenance periods.

T01B T06B T06C

Tool maintenance

Homogenization of etch chamber cleaning

Micro-masking detected as dark defects Reticle issue

6 Weeks Savings Before Final Wafer Test

Lot

Figure 6. Altis used EBI line monitoring to detect volume production excursions, enabling them to take corrective action six weeks sooner than if excursions were detected at final test. 9

Baseline yield improvement and excursion control in the FEOL

In addition to the Cu module, nonvisual defect detection is also important in the FEOL â&#x20AC;&#x201D; particularly for contacts. Altis Semiconductor describes implementation of EBI monitoring to detect excursions inline at contact (W CMP) as part of a comprehensive methodology that also includes EBI monitoring at M1, M2, M3 CMP, CoSi, and Via 1 etch.9 In one case, SRAM contact post W CMP, several excursions went undetected until final test. Using the voltage contrast capability inherent in EBI to flag open contacts, Altis was able to quickly identify contamination and photo/etch issues. These were later traced to inhomogeneous etch chamber cleaning and micro masking on reticles, respectively.

Figure 6 shows the EBI defect yield trend chart for three contact etch chambers. Numerous excursions occurred over the study period. In each case, the inline EBI monitor allowed Altis to detect the excursion and take corrective measures six weeks earlier than if they had relied on final test.

In another case, EDRAM contact post W CMP, failure rates were on 18

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20X return on investment (ROI) for a 20K WSPM, 300 mm fab

The model fab results were derived from the benchmarking survey results described in Table 1, case studies and input from KLA-Tencor EBI customers, analysis of excursion data of over 800 lots of material from EBI monitoring at multiple fabs, and performance data from the eS30 e-beam inspection system.

Similar examples of the excursion analysis methodology are described in detail by Nurani12 and Soucek.7

Figure 7 depicts the optimal implementation of EBI technology for a

The three-year ROI associated with this optimal implementation is

average 3.7 times the failure rate of a reference SRAM design. By using EBI monitoring to drive process improvement activities, the EDRAM failure rate was driven down to, on average, 1.2 times the failure rate of the reference SRAM design.

FEOL LM

EA/Backup

BEOL LM

1 wafer/lot, 33% of lots, ~1 hr/wafer

Cobalt/Nickel Silicide

Leakage Shorts

Contact Etch or CMP

Under-etched, residue, missing, or partial contacts

Via 1 or Metal 2 CMP

Under-etched, residue, missing, or partial contacts

Metal 3+ CMP

Voids; Underetched, residue, missing, or partial vias; Shorts

Figure 7. Optimal EBI implementation for a 20K WSPM, 300 mm copper fab (sub 130 nm) includes three eS30 EBI tools.

Yield Management Solutions

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• Leading edge design rule with an average selling price (ASP) of $10/die, declining by 10 percent per quarter during yield ramp.

• Nominal time for development (reach 10 percent yield) is 12 months at 1000 WSPM. • Nominal time for ramp (10 percent to 60 percent yield) is 18 months at 5000 WSPM. • EBI implementation provides faster learning cycles (inline versus final test) which, in turn, accelerate development and ramp each by six weeks. This 10 percent reduction in time to market is conservative relative to the 25 percent improvement reported by Mizuta3 (Toshiba).

• EBI monitoring in volume production is assumed to detect one unique excursion every three months at each of the four layers shown in Figure 7. These excursions are further assumed to affect only one of eight lots (one of eight chambers, hoods, etc.), in which the yield on affected wafers drops from 70 percent to 35 percent.

Detecting these electrical defects inline instead of at final test is estimated to increase yield by 8 percent. This is a conservative estimate relative to the 15 to 20 percent yield improvement reported by Soucek7 (Texas Instruments) and other sites that have implemented EBI monitoring in volume production.

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Additionally, memory process flow appears to be more susceptible to small physical defects that cannot be detected inline with technologies other than EBI. As a group, memory fabs therefore tend to monitor more for physical defects than Cu fabs and, as a result, use smaller pixel sizes.

More detail on e-beam inspection applications in memory fabs can be found in recent papers from Samsung,8 ProMOS Technologies,12 and Macronix13 for stacked-capacitor DRAM, deep-trench DRAM, and flash memory processes, respectively.

This trend will continue to be important going forward. The production ROI illustrates the increasing importance of detecting electrical defect excursions inline.

Summary

New technology requirements have led to adoption of e-beam inspection in all phases of the technology cycle — development, ramp and production. A new EBI system (eS30) has

been introduced by KLA-Tencor which combines significantly enhanced throughput and sensitivity, with the defect binning and reliability required for production.

Modeling of a 20,000 WSPM logic fab indicates that three high throughput EBI tools provide the optimum ROI for the fab. These results have been validated by several leading chipmakers and serve as a model for new fab space allocation.

100%

Excursion Control $206 Million

90% 80%

Faster ramp $84 Million

70% 60% 50% 40%

Faster Development $244 Million

30%

The large value for ROI in development is consistent with the near universal adoption of EBI for Cu development applications. EBI has been shown to provide unique capability to shorten learning cycles in development and ramp, leading to faster time to market and higher ASPs.

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E-Beam inspection in memory fabs EBI monitoring in memory fabs is undergoing adoption growth similar to that seen in Cu fabs. While memory processes do not generally employ Cu interconnects, the aspect ratios for contact and deep trench memory structures are typically much higher than those for logic devices. As a result, EBI is often necessary to monitor for high-aspect-ratio defectivity such as under-etch and residue in contacts.

Die YIield

estimated to exceed 20X (Figure 8).

Key assumptions used in the analysis include the following:

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4

6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 Months

Figure 8. Impact of optimal EBI implementation on yield cur ve and return on investment.

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This article first appeared in abbreviated form as “e-Beam Inspection: Best Practices for Copper Logic and Foundry Fabs,” David W. Price, Todd Henry, and Robert Fiordalice, Proceedings from the 2003 IEEE International Symposium on Semiconductor Manufacturing, pp. 396-399. San Jose, California, October 1, 2003.

R. Cappel and J. Rathert, “The Advantages of Inline electron-Beam Inspection,” Yield Management Solutions Magazine, Vol. 2, Issue 3, Summer, 2000.

N. Mizuta and T. Amai, “Effective Voltage Contrast Inspection Techniques for Ramping 90 nm Logic Process,” presented at Semicon Japan Yield Management Seminar, Makuhari, Japan, December 5, 2002.

B. Hinschberger, “Applications of e-beam inspection in a mixed Production and R&D Environment,” presented at SEMICON Europa Yield Management Seminar, San Francisco, CA, April 17, 2002.

H. Chen. “Applications of a Foundry Fab eS20XP to Improve FEOL to BEOL Yield,” presented at SEMICON West Yield Management Seminar, San Francisco, CA, July 18, 2001.

J. Fretwell. “Applications of E-Beam Wafer Inspection for Inline Monitoring of Advanced Logic Process Development using Inlaid Copper Te c h n o l o g y. ” P r e s e n t e d a t SEMICON West Yield Management Seminar, San Francisco, CA, July, 2000.

M. Soucek, J. Anderson, H. Chahal, D.W. Price, K. Boahen, and L. Breaux, “Electrical Line Monitoring in a 300 mm Copper Fab,” Semiconductor International, Vol. 26, No.8, pp. 80-90. July, 2003.

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J. Malik and M. Gonzalez, “eS20XP Line Monitoring Implementation at Samsung Austin Semiconductor”. Presented at Semicon Taiwan Yield Management Seminar, Hsin-Chu, Taiwan, August 20, 2002.

S. Desmercières, P. Bertin, G. Roy, S. Schön, J.L. Baltzinger, M. Bostelmann, M. Mercier, J.Y. Nots, and P. Lefebvre, “E-Beam Inspection Methodology and Line Monitoring Applications for Copper Technology,” presented at SEMICON West Yield Management Seminar, San Francisco, CA, July 15, 2003.

P. Lee, “Production Evaluation of KLA-Tencor eS30 Ebeam Inspection System”. Presented at SEMICON West Yield Management Seminar, San Francisco, CA, July 15, 2003.

K. Weiner, T. Henry, A. Satya, G. Verma, R. Wu, O. Patterson, B. Crevasse, K. Cauffman, and W. Cauffman, “Defect Management for 300mm and 130nm Technologies, Part 3: Another Day, Another Yield Learning Cycle”. Yield Management Solutions. pp 15-27. Winter 2002.

R. Nurani, et al. Inline Defect Sampling Methodology in Yield Management: An Integrated Framework, IEEE Transactions on Semiconductor Manufacturing, vol. 9, No. 4, November 1996.

W. Wang, D. Chen, C.H. Chien, C.I. Chang, T. Wang, “Implementation of eS20XP E-beam Inspection for Line Monitoring in a 300 mm Production Fab”. Presented at Taiwan Yield Management Seminar, Hsinchu, Taiwan, Nov. 7, 2003.

C.H. Hsu, S.T. Ma, Y.M. Wang, “Contact photo/etch process window optimization & yield improvement by eS20XP”. Presented at Taiwan Yield Management Seminar, Hsinchu, Taiwan, Nov. 7, 2003.

Yield Management Solutions

DAVID W. PRICE has six years’ experience as a senior applications engineer and regional product manager with KLA-Tencor. He has helped implement e-beam inspection technology at over 15 Cu fabs worldwide. He holds a Ph.D. in Mechanical Engineering from the University of Texas at Austin.

TODD HENRY has more than 18 years of experience in the product, process, integration and yield areas with AT&T, Lucent Technology, Agere Systems. He has been a product marketing director with KLA-Tencor for the last two years.

He holds a B.S. in Chemical Engineering from Carnegie Mellon University and a MBA from Saint Joseph’s University.

ROBERT FIORDALICE is a senior director in KLA Tencor’s Yield Technology Solutions Division.

Prior to joining KLA-Tencor in 2000, Bob managed the BEOL development team at Motorola Inc.’s Research and Development Laboratory in Austin, Texas. He was instrumental in helping Motorola productize Cu interconnect and low-k dielectric. Bob has over twenty patents in the area of semiconductor processing and integration.

Don’t miss the e-Line express.

Introducing

eS30 Electrical Line Monitoring.

Defects occurring within unfilled and filled contacts and vias are among the biggest barriers to production success at 130 nm and below. And the only way to detect them is with dedicated, high-speed electrical line monitoring at every key process step. Introducing the eS30—the industry’s fastest e-beam inspection system. With more than 2x throughput and sensitivity improvements, and the ability to rapidly trend by defect type, the eS30 meets the production requirements for electrical line monitoring. And it maintains the engineering analysis capabilities you need for development and ramp. All in an easy to use, single platform solution. Next stop: eS30. The fastest way to improve and protect your yield.

Learn how one fab used eLM to improve yield by 15-20% in one layer alone. Visit www.kla-tencor.com/eLM Accelerating Yield ® ©2003 KLA-Tencor Corporation

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Got a Litho Question?

Ask the Experts Q

Q

Besides airborne base contamination, can anything else cause T-toping in chemically amplifies resists?

What is Kรถhler illumination?

A T-topping in positive chemically amplified

and ten years ago for microscope illuminators by August Kรถhler, is the type of illumination used by all modern projection lithography tools (such as steppers and scanners). In technical terms, a Kรถhler illuminator is an imaging system where a source (a conventional disk, an annulus of light, or a quadrupole of four disks, for example) is imaged into the entrance pupil of the main objective lens of the stepper. In addition, the reticle is placed at the exit pupil of the illuminator lens (called the condenser lens). With this arrangement comes some very advantageous properties. Any given point on the mask is illuminated by the entire source. As a result, the uniformity of the intensity at the mask is independent of how uniform the actual source is.

In addition, each point on the mask sees the same range of angles of light illuminating it (i.e., the same partial coherence). But the most important property of this illumination is that each point on the mask sees a set of illuminating angles such that the diffraction pattern enters the objective lens at the same place. In other words, every point on the mask (every point in the field) will exhibit the same basic imaging performance.

resists is caused by a reduced level of deblocking (the post-exposure bake induced chemical reaction that enhances resist solubility) at the top of the resist. This reduced deblocking, in turn, is caused by unnaturally low levels of acid, the photochemical product of exposure. So the question is, what can cause acid loss at the top of the resist? Airborne base contaminants, which land on the resist and diffuse into the top portion, can neutralize acid during the delay time between exposure and PEB. The effects of airborne base contamination can be reduced by reducing the levels of base contaminants, reducing the delay time between exposure and PEB, and lowering the diffusivity of the contaminant within the resist. In addition, base additives in the resist can somewhat reduce the magnitude of T-topping whenever the base additive is a stronger base than the contaminant.

Besides airborne contamination, acid evaporation from the top of the resist can produce the same type of T-topping. This occurs when the acid molecule is too small so that its rate of evaporation is not negligible. Most modern resists have large enough acid molecules to avoid this problem. In addition, solvent evaporation during post-apply bake leads to a drier resist film at the top surface. Since solvent content can affect acid diffusivity and therefore the deblocking reaction rate, the result can be a reduced level of deblocking at the top of the resist. While this effect only rarely leads to T-topping, it can enhance the magnitude of T-topping coming from another source.

Chris A. Mack, KLA-Tencor

A Kรถhler illumination, developed one hundred

Do you have a lithography question?

Just e-mail lithocolumn@kla-tencor.com and have your questions answered by Chris Mack or another of our experts.

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Taking Control of the Copper Process at 65 nm Murali Narasimhan, KLA-Tencor Corporation

The move from aluminum to copper (Cu) interconnects has been driven primarily by the desire for better device performance.

However, the transition to Cu created a number of unexpected challenges that slowed the rate of Cu adoption at the 130 nm node and stalled efforts to integrate low-k dielectrics into the interconnect. The transition to the 90 and 65 nm nodes has introduced an entirely new set of challenges. This article explores each of these issues in detail and describes the best-known metrology methods currently available to help IC manufacturers bring the copper process under control at the 65 nm node.

Introduction

With several IC manufacturers now completing the development cycle for their second-generation Cu interconnects for the 90 nm node, process development engineers are now beginning to look at process issues that they are likely to face at 65 nm. What they will find are not incrementally more difficult process integration problems, but rather an entirely new set of challenges that will require the implementation of very specific metrology techniques to keep copper interconnect processing under control. Cu process control issues at the 65 nm node can be broadly classified into five categories: (1) low-k materials; (2) Cu barrier/seed advances; (3) electroplating; (4) Cu chemical mechanical planarization (CMP); and (5) interconnect reliability.

Low-k materials and their process control issues

Back-end-of-line (BEOL) inter-layer dielectrics (ILDs) are evolving into a multi-layer stack of passivation dielectric, etch-stop layers, ILD and inter-metal dielectric, and a potential cap layer in the form of harder silicon carbon nitride (SiCN) to withstand the Cu CMP process. Measuring the film thickness

of individual layers within the ILD stacks has proven challenging for some metrology techniques, which have difficulty distinguishing between layers of widely varying thicknesses made from a variety of material types.1 The presence of under-layer artifacts, especially at higher levels of metallization, also affects the accuracy of film thickness measurements. Simpler optical techniques, such as single- or multiple-angle ellipsometry or reflectometry, often do not provide enough information to separate confusing signals from variations in the multiple layers of interest. Spectroscopic ellipsometry (see sidebar) offers a solution in this case, since ellipsometric information (cos delta and tan psi) is collected simultaneously over 1024 wavelengths. Powerful algorithms then interpret this information to yield the best combination of sensitivity to excursions, robustness to normal process variation, measurement precision, and long-term instrument stability and system-to-system matching (the last two of which are required for production monitoring metrology). Advances in optics technology, modeling algorithms and computational processing have enabled fast and routine measurements of thickness and refractive index of low-k materials with non-homogenous graded compositions, plasma and/or thermal treatment to modify surface and bulk properties, porous low-k materials and multi-layer combinations of these films (Figure 1).

More attention is being placed on the mechanical properties of low-k materials, since the ability of low-k films to withstand Cu CMP processes and stress migration (SM) Spring 2004

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Multi-Layer, Multi-Parameter SE Measurement

Six Layer Low-K Film Stack Repeatability 2635.0 1.3890

513

2633.0

1.96

SiN(500 A)

497.5 1.943 490.8

1.3870

2631.0

1.931 4.18e+003

2629.0

4090

401.2

Thickness (A)

FSG (4000 A)

1.95

507

SiN(500 A)

1.945

488.3 1.937 478

FSG(4000 A)

4.31c+003

422.2

1.3830

2625.0 2623.0

1.3810

2621.0

414.7

SiN(500 A)

1.3850

2627.0

1.3790 503

1.97

2619.0 1.960

Silicon

Low k Top T Low k Top R

404.1

475.2

2617.0

1.96

T

N

1.3770

1.3750

2615.0 1

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Load/Unload

§

Measurements using spectroscopic ellipsometry with reflective optics on product wafers

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Simultaneous 16 parameter measurement of thickness and refractive indices of all six layers

§

Highly robust, precise and sensitive measurements • Thickness 0.02% - 0.1% repeatability • RI < 0.03% repeatability

SiO2 SiC Low κ SiC Low κ SiN Cu

Figure 1. Complex BEOL ILD film stacks present a significant metrology challenge, wherein a multi-layer stack has to be measured on a product wafer without any under-layer artifacts — even at higher levels of metallization.

after processing is key to achieving optimal chip reliability. Techniques such as nano-indentation and fourpoint bridge fracture toughness are currently being used for materials characterization and early process development of low-k films. Scientists are also using analytical techniques, such as porosimetric ellipsometry, positron annihilation lifetime spectroscopy (PALS) and x-ray scattering to characterize pore size and distribution — both of which indirectly affect mechanical properties.

The need for an inline, non-contact technique for production monitoring of mechanical properties is unclear at this point. However, some early results of applying the photo-acoustic metrology technique to measure Young’s Modulus of low-k films — a key mechanical property parameter — look promising.2 Another emerging process control challenge is the sensitivity of the dielectric constant in low-k materials to post-processing. Temperature cycles and environments with high mechanical, plasma and chemical stresses in post-processing steps can modify and degrade the dielectric constant. Monitoring the dielectric constant 24

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Yield Management Solutions

is therefore required in production process equipment for 65 nm Cu manufacturing lines. Conventional MOSCAP CV testing can be used for this application, but requires multiple steps to deposit and pattern metal electrodes to form the MOS capacitor on the low-k film being measured. The MOS capacitor must then be probed to obtain the CV curve measurements that must, in turn, be combined with optical film thickness measurements to yield the dielectric constant. The two to three day cycle time involved in making this measurement places significant product wafers at risk, especially given the number of possible process steps that can adversely affect the low-k material. Mercury (Hg) probes have been used to monitor the dielectric constant for many years, but cannot be used inline in an IC fab due to toxicity and contamination concerns.3 Corona oxide semiconductor measurement techniques (see sidebar) offer a solution for monitoring low-k damage by measuring capacitance and trapped charges of a low-k film. A small, precise amount of charge is deposited on the low-k film in the measurement location to form

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Spectroscopic Ellipsometry With increasing complexity of chip fabrication, spectroscopic ellipsometry (SE) has established itself as the technique of choice over the last five years for monitoring thin film processes. This technique relies on the measurement of the optical properties of materials through analysis of reflected, polarized light across a wide spectral range.

SE relies on measurement of optical properties through analysis of polarized light reflected from the sample surface (Figure 1). The incident polarized light is reflected from the sample and passes through an analyzer before striking the detector. In the rotating polarizer version of this technique used in KLA-Tencor systems, the polarization state of the incident light is continuously varied and the detector measures the integrated intensity of the reflected polarized light (for one-eighth of a rotation) at each wavelength. A broadband light source and prism are used to separate the wavelengths of the light incident on the pixels forming the detector array. The integrated intensities form the eight “Sums” corresponding to a complete rotation of the polarizer. The standard ellipsometry parameters Tan(psi) and Cos(delta) can be computed from these eight “Sums” at each wavelength. These quantities are related to the two components Rp and Rs of the reflected polarized light, by the equation:

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ε=1+

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ε = (n – ik)2

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To solve for the parameters in the dispersion model and the film thickness(t), a regression analysis is performed so that the difference between the calculated and measured tan(psi)-cos(delta) spectra is minimized. Mathematically the regression is actually performed on the Fourier coefficients (α and β) of the detector intensity as modulated by the rotating polarizer. The Fourier coefficients are related to (tan(Ψ),cos(∆) ) by:

where Rp is the electric field reflection coefficient of the component of polarization parallel to the plane of the incident and reflected beams, and Rs is the electric field reflection coefficient of the component perpendicular to that plane. From the above equation, it can then be inferred that Tan(psi) is the amplitude of the ratio of the p- and s- components and cos(delta) is the real part of the complex quantity exp(i∆), where ∆. is the phase shift between the p- and s- components.

and

Theoretical spectra can be generated based on material models defining the substrate and film stack. A mathmatical regression analysis is performed between the measured tan(psi)-cos(delta) spectra and theoretical computation.

where Α is the fixed analyzer transmission axis measured with respect to the p-direction polarization angle.

Both the “analyzer” and the rotating polarizer are linear polarizers.

a “virtual electrode.” The surface voltage that is created from this charge is then measured by a Kelvin probe that is positioned at a precise distance above the film.

By incrementally depositing more charge and repeating the voltage measurements, a Q-V (charge-voltage) curve is constructed and the relevant properties of the

low-k material are extracted. Anneal furnaces, highdensity plasma chemical vapor deposition (HDP-CVD) reactors, etch reactors, Cu CMP tools, dry/wet cleaning systems, plasma stripping tools and ashing equipment can all be monitored routinely using this technique (Figure 2).

α= tan2Ψ–tan 2A tan Ψ+tan A

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Corona oxide measurement technology KLA-Tencor’s Quantox XP dielectric measurement system improves processing capabilities by reducing the time required to gather information for monitoring critical dielectric deposition processes. Quantox employs measurement principles that are highly analogous to MOS C-V electrical testing with the advantages of fast time-to-results and non-contact inline measurement.

The Corona-Oxide-Silicon (COS) Quantox system is based on combining three technologies (charged corona, vibrating Kelvin probe, and pulsed light source) to provide comprehensive, fully automated analysis and separation of charge components for characterizing dielectric and semiconductor materials.

The charged corona ions provide biasing and emulate the functions of the MOS electrical contact. A graphical description of the components of the Quantox COS systems is shown in the following figure.

The Quantox corona generator produces ions and deposits a precise amount of charge on the surface of the dielectric film to form the “virtual electrode” of a MOS capacitor. The film serves as the dielectric of the MOS capacitor and the wafer as the second electrode. This structure replaces the capacitor structure formed by depositing and patterning a metal electrode in traditional C-V testing. The ions contact the surface with nearly zero kinetic energy, so they do not harm or penetrate the insulating surface. The vibrating Kelvin probe provides capacitive-coupled sensing of the wafer surface potential and functions as a non-intrusive voltmeter with virtually infinite input impedance. The pulsed light source, linked to the Kelvin probe, enables the creation of surface photo-voltage (SPV), and

Advances in Cu barrier seed

While Cu barrier materials at the 130 nm node were generally composed of a single layer of tantalum nitride (TaN) or tantalum (Ta), most IC manufacturers have switched to TaN/Ta bi-layer barriers at the 90 nm node. As a copper barrier material, the Ta/TaN bi-layer barrier offers a number of benefits, such as TaN’s excellent adhesion to silicon dioxide-based ILDs and Ta’s good adhesion to copper.4 For the 65 nm node, ultrathin atomic layer deposition (ALD) barriers composed of either TaN or tungsten nitride (WNx) are being considered. The main attraction with ALD is its ability to deposit highly conformal ultra-thin film layers (down to 10 Å) and provide uniform and conformal step coverage on high aspect ratio vias and trenches. Integration 26

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Corona Bias, Q

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provides measurement of silicon band bending and a direct measurement of Vfb. The capacitance of the dielectric film, C, is determined from the slope, dQ/dV in the accumulation region of a Q-V curve collected by Quantox. The capacitance is then converted to dielectric constant, k, by combining it with optical thickness, t, measured using spectroscopic ellipsometry (k=C*t/ε0). In actual application, some second order corrections can be applied to acquire data to account for semiconductor band bending. The system provides measurement results for production control (dielectric capacitance and leakage) and plasma process monitoring (density of interface traps, surface voltage, and total oxide charge) as well as electrical properties of semiconductor materials.

issues, such as adhesion, however, will likely force the industry to continue to use multi-layer barriers for the foreseeable future.

Monitoring Cu barriers poses significant challenges at the 90 nm node and below. Conventional techniques, such as four-point probe sheet resistance or photo-acoustic metrology, no longer work effectively because they are unable to separate the individual layers of the bi-layer barrier. Nor can they measure under Cu seed layers on product wafers. Promising new techniques, such as xray reflectivity (XRR), require very complex modeling algorithms and curve fitting. XRR also lacks the small spot size required for product-wafer monitoring.

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Figure 2. Production monitoring of electrical properties of low-k dielectric films is key to ensure parametric yield at 65 nm and below. KLA-Tencor’s Quantox XP utilizes Corona Oxide Semiconductor measurement technology to monitor dielectric constant and other electrical properties of low-k materials inline by measuring Q-V (charge capacitance) characteristics of a low-k film.

Barrier composition has also emerged as an important parameter that must be monitored during production.

As the barriers become thinner, their composition plays a larger role in their functionality. Changes in composition can affect diffusion properties, interfacial adhesion and film stress — all of which affect SM and electromigration (EM) resistance along with time dependent dielectric breakdown (TDDB) in Cu interconnects.

Incorrect barrier composition can also result in high via resistance due to changes in the resistivity and contact resistance of the barrier, thus degrading parametric yield. Conventional metrology techniques do not offer a way to measure composition, and, as a result, IC manufacturers are literally flying blind in production, with respect to controlling the composition of Cu barrier layers. Identifying a method that is capable of monitoring Cu barrier composition inline is therefore essential, as it offers an early warning system for potentially expensive IC reliability failures in the field.

Ultra-thin ALD barriers also lack a reliable product monitoring solution. Current techniques suffer from a number of limitations, including a poor signal-to-noise ratio for measurements on sub-50 Å ALD barrier films.

Barrier and seed layer step coverage in trenches and vias continues to be an open challenge for inline metrology techniques. Scatterometry offers a future possibility of monitoring step coverage inline, but this is an issue that currently has no solution.

A promising new technology in the form of electron stimulated x-ray (ESX) metrology (see sidebar) is now available and can be used to measure thickness and

composition of Cu barrier/seed layers on product wafers.

The technique is derived from electron probe microanalysis (EPMA), a technique that has been widely used in materials analysis. Advances in electron-beam (e-beam) columns, x-ray detectors and modeling algorithms, combined with fab automation, vacuum wafer handling and pattern recognition, have now made this technique available for fast inline production monitoring in an IC fab (Figure 3).

Electroplating process control

Electroplating will continue to be the process of choice for filling trenches and vias at the 65 nm node. Surface topography control during the electroplating process is a key issue, since the additives required to ensure filling often result in so-called “super-filling,” where the thickness of the overburden of Cu is higher on densely patterned areas. These super fillings lead to residual metal due to non-uniform removal during Cu CMP. Voiding of vias and trenches continue to remain an issue due to aging of the electroplating bath and changes in the concentration of additives. The latter is caused by degradation effects of time and temperature on the organic long-chain polymers. In addition, high plating currents can cause edge effects that result in non-uniform thickness at the electrode contact points. These, in turn, can result in residual metal and flaking after CMP. To adequately characterize Cu thickness inline after electroplating requires a non-contact metrology method that does not cause edge effects. A small spot size is Spring 2004

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Opaque film thickness and composition metrology The MetriX 100 opaque film thickness and composition metrology system is based on electron beam-stimulated X-ray (ESX) technology used in materials analysis for over 50 years. An incident electron beam stimulates x-ray emissions at "characteristic" energies in the films being measured. Beam electrons interact with atoms in a sample through three main processes: Incoming electrons knock tightly bound core electrons out of their shells, and electrons from higher energy levels relax and emit X-rays (source of the ESX signal); freed electrons radiate photons and lose energy (source of the background X-rays); electrons change direction but do not lose energy (source of backscattered electrons).

The MetriX 100 algorithm models the following effects:

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I=Io e

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For high throughput and sensitivity, MetriX 100 uses wavelength dispersive spectrometers (WDS) that are fixed in energy and measure X-ray count rate at fixed points in the spectrum. X-ray emission, absorption, and interaction volume in the film stack being measured is modeled using proprietary algorithms. In order to eliminate instrumental variation and drift, the model accepts as input "k-ratios," which are the count rate from the wafer divided by the count rate from a known standard of the same material stored in the system. The model then calculates film thicknesses and stoichiometry of compound films by iteratively converging to within a pre-set measurement error requirement.

Cu Seed TaN Barrier Low-k Cu Barrier/Seed Films Figure 3. KLA-Tencor’s MetriX 100 utilizes ESX technology to provide simultaneous Cu,

these layers. ESX metrology also has the potential to detect sub-surface partial voids, which may not have a large voltage contrast signature — offering an early warning system for reliability failures. While high-probability systematic voiding can be effectively detected with transmission electron microscopy (TEM) or focused ion beam (FIB) cross-sections with limited sampling, low-probability random voiding of trenches and vias can be effectively monitored in production by using e-beam inspection to scan a via chain array in test structures.5

TaN thickness and percentage nitrogen measurements on Cu barrier/seed layers.

also needed to achieve the high throughput required for production line monitoring. Composition metrology will also be critical, since tin (Sn) and other alloying elements are being investigated for use in the interconnect to improve EM resistance. ESX metrology is capable of monitoring both the thickness and composition of 28

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Cu CMP issues and solutions

Cu CMP compatibility has been one of the biggest challenges for low-k materials, and researchers are working to reduce the mechanical stresses generated during Cu CMP by using low down-force and slurry-less processing. Maintaining topographical flatness is a key

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Figure 4. Characterizing dishing and erosion during Cu CMP is important to maintain topographical flatness and avoid defectivity issues. Here, the line scan capability of KLA-Tencor’s MetriX 100 non-contact opaque films metrology system measures remaining Cu metal after CMP and clearly shows dishing and erosion effects.

requirement for Cu CMP and subsequent lithography steps. Therefore, ensuring uniform polishing and removal rates in order to reduce dishing and erosion — and resultant defectivity — is a significant process control challenge. Atomic force microscopy (AFM) and highresolution profilometry (HRP) offer a good way to characterize dishing and erosion during process development.

Since these techniques are slow and make quasi-contact with the wafer, IC manufacturers are looking for a faster, non-contact method to implement for product wafer monitoring. Both photo-acoustic and ESX techniques offer a way to measure Cu in wide and narrow lines, which allows for the measurement of dishing and erosion (Figure 4). The ESX technique also offers a way to check for residual metal down to 10 Å in thickness in densely patterned areas, where the polish rate can be significantly different from the average rate across the wafer. In addition, the small spot size of the electron beam has also enabled TaN barrier thickness measurement inside wide trenches and power bus line interconnect structures.

Cu reliability

Although Cu has been in use in semiconductor fabrica-

tion for several years, only now are the reliability failure mechanisms of Cu interconnects being discovered and understood. While the bulk diffusion rate of Cu within itself is low, surface and interfacial diffusion rates of Cu are very high, causing void movement at the interfaces, which in turn lead to EM and SM failure. Bi-layer barriers, which were created for better adhesion, have the additional advantage of improving EM lifetime.

However, barrier compo-sition can affect Cu diffusion rates, and thus also impact EM and SM lifetime and TDDB. The different coefficients of thermal expansion between the dielectrics and Cu metal can also lead to higher stress gradients, which exacerbate Cu SM. In addition, vacancies and micro-voids present in the Cu during electroplating fill can coalesce during anneals and chip operating conditions, causing line opens and chip failure.

At the 65 nm node, a variety of engineering solutions are being considered to improve EM and SM lifetime and TDDB of Cu interconnects. Capping layers grown selectively on the Cu surfaces by electro-less plating is one promising method. In this example, a thin layer of cobalt tungsten phosphide (CoWP) or cobalt tungsten Spring 2004

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The transition to Cu interconnects has proven to be much more difficult than first expected, and numerous challenges remain for the industry Site 1 Site 2 as it ramps up to Cu production at 90 nm and begins Cu process develCoWP opment at the 65 nm node. In addiW at% P at% Thickness Co at% (?) tion to the increasing number of film 90.1% 1.6% 8.3% 163 Process A Site 1 layers in ILD stacks that must be 89.7% 1.5% 172 8.8% Site 2 89.9% 207 1.7% 8.5% monitored, second-generation low-k Site 1 Process B 89.7% 198 1.7% 8.6% Site 2 materials are highly sensitive to postSite 1 89.8% 163 1.9% 8.3% Process C processing steps, which can degrade Site 2 89.3% 1.8% 8.9% 170 dielectric constant. Bi-layer Cu barriers, ALD barriers and other new films introduce new parameters, such Figure 5. Electro-less capping layers of CoWP require measurements during process development to as composition, which must be closely optimize process conditions. Chemical loading effects due to changes in feature size can cause monitored in production to minimize variations in film thickness and composition affecting the functionality of the capping layer through the impact of process variations on changes in the interfacial adhesion, mechanical stress and diffusivity properties of the film. The long-term device reliability as well small spot size of the electron beam in KLA-Tencor’s MetriX 100 allows the tool to measure thickness as short-term yields. Some currently and composition on two different features with var ying linewidths to optimize process conditions established monitoring methods, as across the die and wafer. well as a few emerging metrology techniques, have demonstrated the boride (CoWB) effectively encapsulates the Cu and preability to address many of these process control chalvents it from migrating across the dielectric interface and lenges, and show promise in providing the effective causing leakage and EM failure (Figure 5). Controlling the copper interconnect control needed at the 65 nm node. thickness and composition of the cap layer is critical, since both parameters impact the diffusivity, interfacial adhesion and film stress of the layer. Conventional References metrology techniques, such as photo-acoustic or x-ray 1. Semiconductor Industry Association (SIA), International reflectivity, have difficulty in detecting the interface Technology Roadmap for Semiconductors, 2001 Edition, between the cap layer and the underlying Cu interconMetrology, p. 24. nect, and thus cannot measure them effectively. The 2. S. Leary, et. al., “Successful use of low-k films requires meaESX technique, on the other hand, measures the X-ray suring Young’s Modulus,” Solid State Technology, October emissions from the elemental cobalt (Co), tungsten (W) 2003, pp. 32-34. and phosphorus (P) or boron (B), and can quantify thick3. T. Yunogami, et. al., “Development of the damage evalness and composition independently. This capability is uation technology of a low-k film by surface photo voltage,” invaluable for optimizing the capping layer process durYield Management Seminar Japan, December 2002.

4. L. Peters, “Making a better copper barrier,” Semiconducing process development. It also lends itself in the tor International, March 2003, p. 52. future for line monitoring applications in production.

5. B. Fiordalice and D. W. Price, “Via chain monitoring in The small spot size of the e-beam allows measurement copper interconnects,” Semiconductor International, July on different linewidths. This is an important benefit, 2002, p. 70. since chemical loading effects during capping layer This article has been adapted from an article originally apgrowth can result in variations in thickness and compearing in the 20th Edition of Semiconductor Fabtech. position on lines with different feature sizes.

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Yield Management Solutions

Steer clear of danger down the road.

X

Inline film composition metrology.

Introducing the only inline, non-contact, advanced films metrology tool that gives you the control you need to avoid product failures in the field.

Independent film composition and thickness measurements Ultra-thin films with high accuracy and precision Multi-layer film stacks on product wafers 90 nm production and 65 nm development ➤

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Accelerating Yield

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Crystal growth and haze formation on reticles continues to be a significant source of concern for the semiconductor industry.

Possible sources, causes, and formation mechanisms continue to be investigated. Mask making materials, process residues, reticle containers and fab and or stepper environment can contribute to reticle degradation over time. This paper provides a comprehensive evaluation of various molecular contaminants found on the backside surface of a reticle used in high-volume production. Previously, all or most of the photo-induced contaminants were detected under the pellicle. This particular contamination is a white “haze” detected by pre-exposure inspection using KLA-Tencor TeraStar STARlight™ with Un-patterned Reticle Surface Analysis, (URSA). Chemical analysis was done using time-of-flight secondary ion mass spectroscopy (ToF-SIMS) and Raman spectroscopy.

As lithographers move to shorter wavelengths, it can be assumed a priori that molecular contaminants in the path of light will be more reactive and possibly effect transmission more radically than at higher wavelengths. While reticle surface contamination has been identified as a significant issue at 157 nm, it is rapidly becoming a critical issue at 248 and 193 nm. It should be noted that the pelliclized reticle structure creates an almost perfect photochemical reaction chamber. Figure 1 shows the basic structure of a pelliclized production reticle.

Introduction

Sub-pellicle reticle contamination was first reported by Grenon et al.1 as a major concern in high volume semiconductor fabs. Bhattacharyya et al.2 identified some of the contaminants as cyanuric acid and ammonium sulfate. Since the initial report, many cases of particle or contamination formation on both 248 nm and 193 nm reticles have been reported. While reported cases of the problem have been increasing as 248 nm Aluminum frame Transparent polymer film lithography becomes more (pellicle) ubiquitous, the introduction of 193 nm lithography in Chrome or MoSi Frame adhesive pattern leading-edge fabs has Vent resulted in reports of haze and contamination formation on reticles at greater numbers and at a faster Figure 1. Pelliclized reticle structure. rate.3 32

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The intra-pellicle space can trap molecular contaminants and provide an opportunity for them to react and deposit on reticle and pellicle surfaces. Note that the inner surfaces of the pellicle have several adhesives: a film adhesive that is often cyanoacrylate, the inner frame wall adhesive (IFW), and the frame adhesive. These materials out-gas and can potentially cause crystal formation in the optical path of the reticle. Additionally, surface contaminants on the metal mask and quartz surfaces can out-gas and be trapped in this space.

Because the reticle user identified this problem, this investigation focused on identifying the chemical composition and possible cause(s) of the backside quartz haze. However, it should be noted that identical haze was detected on the inner surface of the reticle storage box, as well as in the intra-pellicle surfaces.

Defect detection and identification

Defect Inspection Method — TeraStar STARlight with URSA The reticle analyzed in this study was inspected using the above systems and software options, and was sent for chemical analysis. The URSA option first detected the haze on the backside quartz surface of the reticle.

The advantages of this technique are that it provides inspection capability for both surfaces of the pellicle and for the backside surface of the reticle. URSA

Figure 3. Defect map from STARlight URSA inspection — Reticle’s

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employs laser scattering illumination and detection technology to find particles, smudges, fingerprints and other handling defects on unpatterned reticle surfaces.

STARlight and URSA combined inspection, provides the capability to inspect all the surfaces of a reticle (patterned surface, backside quartz, chromium, and inner and outer surfaces of the pellicle). The features of this inspection technique are: 1. URSA provides a sensitivity of 4 µm (on PSLS) in about two minutes/surface.

2. Darkfield defect preview on pellicles and glass while URSA or STARlight inspections are in progress.

Figure 4. High magnification image of the haze.

backside quartz surface.

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3. Defect review order from largest to smallest.

4. Brightfield, reflected-light review microscope for live review after completion of inspection.

5. User adjustable sizing box for defect measurement.

6. Defect coordinates referenced to STARlight reference.

7. View reticle pattern under a defect on pellicle or glass.

These capabilities allowed detection of the contaminants on the reticle prior to any potentially catastrophic use of the reticle in production. Figure 2 provides a brief overview of the basic URSA defect detection system.

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A 6.0 x 6.0 x 0.25 inch pelliclized reticle was inspected on TeraStar STARlight with URSA following extensive exposure in the fab. The results of the inspection indicated a significant level of haze on the backside quartz surface of the reticle. Other defects were evident on the front side of the reticle under the pellicle. For the purposes of this investigation we focused on identifying the composition and magnitude of the haze contamination of the backside of the reticle. Figures 3 through 5 provide data generated during the reticle inspection.

Defect Identification Following defect inspection, the reticle was submitted for chemical analysis. Both Raman spectroscopy and

Figure 5. Provides high magnification images of the various types of defects detected on the backside of the reticle.

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Defect map from STARlight URSA inspection â&#x20AC;&#x201D; Reticle backside glass surface

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Figure 6. Locations on the reticle (center) where the haze analysis was done. The image on the left is the TeraStar STARlight with URSA image, and on the right is the image through the Raman microscope.

ToF-SIMS analysis were done on several defective areas of the reticle. Figure 6 provides images of the locations of the analyses.

Raman spectroscopy was accomplished on two of the haze defects that were small amorphous defects in the range of 1.0 µm. These defects were representative of all of the other haze-type defects on the reticle. The Raman spectra were collected using a Renishaw Model Raman spectrometer equipped with a 633 nm laser. The beam size was approximately 1.0 µm in diameter. Background spectra were collected on the quartz surface in order to cancel out the possibility of contamination due to transport and handling during the analysis. The results show the haze to be one compound, ammonium sulfate.4 Figures 7 and 8 show the spectra for the defects analyzed.

These spectra are consistent with the spectra previous reported for ammonium sulfate. The possible sources and mechanism of the formation of this contaminant will be discussed later.

In order to verify the elemental composition of the haze defects, we conducted ToF-SIMS analysis on the quartz

surface of the backside of the reticle. The instrument used in this work was an ION-TOF, TOF-SIMS IV™ secondary ion mass spectrometer. In this technique, due to the low primary ion fluence, only outer surface monolayers are probed (i.e. a few angstroms). The actual damage to the sample is very low, and thus the method is ‘quasi non-destructive’ or static in nature. This technique provides not only elemental information about the surface, but chemical information as well, in the form of fragmentation patterns of molecular species.

A 15 kV, pulsed 69Ga+ primary ion beam was used for analysis, by impinging upon the sample surface and creating secondary ions in a process known as sputtering. The primary gallium beam was rastered over a 500x500 µm2 area in positive secondary ion mode, and 300x300 µm2 in negative secondary ion mode. Both positive and negative secondary ions were collected and mass separated via the time-of-flight (TOF) analyser. A traditional first order mass spectrum was then produced by plotting the ion intensity at a particular mass (more specifically, mass to charge ratio, m/e; however, the vast majority of species of interest are singly charged). The Raman Spectrum of Backside Quartz “Haze” Defects

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Figure 8. Raman spectrum of ammonium sulfate defect on quartz side of reticle.

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often followed by a dilute ammonium hydroxide rinse.

While the chemistries are similar from mask facility to mask facility, the process recipes can change significantly. The recipes can even vary within a mask facility.

This is probably because not all reticles behave in the same manner when exposed. These chemistries can leave residues on all surfaces of the reticle if improperly rinsed; they also react with the quartz surfaces. Some of the more common reactions that can occur are the formation of silicic acid or hydrated silicon dioxide. The ammonium rinse can form ammonium silicate. Figure 10 provides the possible mechanism for the formation of the haze on this reticle. While this may be the most likely cause, it does not obviate other potential causes or mechanisms for haze formation on reticles.

mass range for this work was 0 - 1000 AMU with a maximum of 10,000 possible; however, acquisition time increases with increasing mass range. The nominal resolution approached 10,000 above 200 AMU. The technique has a detection limit approaching PPM levels, depending on the species of interest. As the secondary ion yields are matrix dependent, the technique is not quantitative on an absolute scale, although this may be overcome via the use of appropriate standards.

Figure 9 provides the results of the ToF-SIMS analysis.

The intensity scale indicates the relative concentrations of the various ions detected on the surface. The brighter the ToF-SIMS image, the greater the relative concentration of that ion. The figure shows the ions of interest. It is important to note that other significant contaminants were found on the surface and are not shown here. The left side of the figure provides a ToF-SIMS image of the ammonium ions that compose the haze. The remaining images show both the positive ammonium ions and the sulfate ions on the surface.

It is clear from both the Raman spectroscopy and the ToF-SIMS analysis that the haze on the reticle is ammonium sulfate.

While surface absorbed ammonium ions are the most probable source of the ammonium ions; other environmental sources of ammonium ions could cause the formation of the ammonium sulfate. However, in most fabs where chemically amplified resists are used, activated charcoal filters are used to filter out ammonia and ammonium ions; therefore, environmentally deposited

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Figure 10. Possible mechanism for the formation of ammonium sulfate haze.

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Backside glass haze can effect overall mask transmission and thus can cause a dose shift 180 on the wafer. A dose shift can be serious 160 because most low k1 processes run with a 140 very small process window and therefore a 120 small dose shift can create a serious yield 100 80 issue. The backside haze can be easily and 60 reliably detected by Starlight URSA inspec40 tion. An ideal quality control approach is 20 to detect any possible reticle degradation 0 0 25 50 75 100 125 150 prior to any catastrophic failure in the fab.

Energy kJ This can best be accomplished by re193 nm Ret1 193 nm Ret2 193 nm Ret1 inspecting reticles prior to exposure. It is DUV Ret2 Linear (DUV Ret2) Linear (DUV Ret1) Linear (193 nm Ret2) Linear (193 nm Ret1) recommended that a carefully-developed reticle inspection strategy be implemented Figure 11. Plot of the number of defects formed as a function of exposure energy on backside of reticle. to minimize mean-time to detect defect growth. This is best done by understanding ammonium ions are an unlikely source. Sulfate ions are the cumulative dose seen by the reticle and correlating not labile (likely to easily undergo chemical change), it with the first detection of reticle degradation. These therefore it is mostly probable that these ions were on values will vary as a function of wavelength and exposure the reticle as a cleaning process residue. Other possible dose in the fab. As a result, each fab should develop sources of sulfate ions could be environmental, however specific inspection and re-qualification plans for reticle. unlikely this is. Unpublished results have shown high concentrations of sulfate ions on all mask surfaces folThe rate of contamination formation on these reticles was lowing mask cleaning. significantly faster at 193 nm exposure than at 248 nm, hence a greater inspection or re-qualification frequency Exposure Conditions for Haze Formation would be recommended for 193 nm lithography.

While exposure conditions for particle and haze formation can vary significantly from fab to fab and from reticle to Reference reticle, exposure conditions under which the haze formed on the reticles in this paper are well understood. Figure 11 1. B. J. Grenon, Peters, C., Battacharyya, K. and Volk, W., provides data for several reticles that have shown haze Formation and Detection of Sub-pellicle Defects by Exposure to DUV System Illumination, 19th Annual BACUS Symposium formation on both the backside, as well as the chromium on Photomask Technology, Proceedings of SPIE, Vol. 3873, side of the reticles.

Backside Contamination

# URSA Defects

200

The above chart indicates that the formation of contamination defects is linear for 248 nm exposure and almost exponential with dose for 193 nm. For this reason reticles exposed at 193 nm provide a greater risk for catastrophic failure in the fab; hence, they should be inspected at a greater frequency.

Conclusions

Crystal growth and haze formation on reticles continues to be a significant source of concern for the semiconductor industry. Possible sources, causes and formation mechanisms continue to be investigated. Mask making materials, process residues, reticle containers and fab and or stepper environment can contribute to reticle degradation over time. In the case of this study, we feel that the most probable source of the haze formation was residues left on the reticle during the fabrication process.

pp. 162-76, September 1999.

2. K. Battacharyya, Volk, W., Brown, D., Ayala, J. and Grenon, B.J., Investigation of Reticle Defect Formation at DUV Lithography, 22nd Annual BACUS Symposium on Photomask Technology, Proceedings of SPIE, Vol. 4889, pp.478-87, October 2002.

3. E.V. Johnstone, L. Dieu, C. Chovino, J. Reyes, D. Hong, P. Krishnan, D. Coburn and C. Capella, 193nm Haze Contamination: A close Relationship between Mask and its Environment, 23rd Annual BACUS Symposium on Photomask Technology, Vol. 5256, (this volume), September 2003.

4. Y-H. Zhang and C.K. Chan, Understanding the Hygroscopic Properties of Supersaturated Droplets of Metal and Ammonium Sulfate Solutions Using Raman Spectroscopy, J. Phys. Chem. A, 106, pp.285-292, 2002.

A version of this article was presented at the 23rd Annual BACUS Symposium on Photomask Technology, September 2003, Monterey, California, USA. Published in the 2003 BACUS Symposium proceedings Vol. 5256, pp.

1103-1110.

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Because any defect can matter.

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Implementation of High Resolution Reticle Inspection in Wafer Fabs Aditya Dayal, KLA-Tencor Corporation Nathan Bergmann, Peter Sanchez, Intel Corporation

Many advanced wafer fabs are currently fabricating devices with 130 nm or smaller design rules. To meet the challenges at these sub-wavelength technology nodes, fabs are using a variety of resolution enhancement techniques (RETs) in lithography and exploring new methods of processing, inspecting and requalifying photomasks. The acceleration of the lithography roadmap imposes more stringent requirements on mask qualification and requalification to ensure that device yields are not compromised: mask inspection tools of today need to find smaller defects on reticles against considerably more complicated patterns or tighter critical dimensions (CDs). In this paper we describe the early stages of implementation and proliferation of advanced reticle inspection tools at high volume manufacturing wafer fabs. We describe the tools and procedure used to streamline reticle requalification at the fabs and improve the feedback loop between the fabs and the mask shop.

Introduction

This paper describes an SL3UV inspection tool-based infrastructure for contamination inspection of reticles in wafer fabs. This tool scans the patterned surface of the reticle using a 364 nm laser in simultaneous transmitted and reflected (STARlight™) mode to detect defects. Such defects include particle contaminants, stains, scratches, crystal growth or also certain kinds of pattern defects/irregularities.1 Central to the defect detection methodology of these requalification tools is the procedure of STARlight calibration.

During this procedure, the tool acquires images by sampling various geometries on the reticle and constructs a database of their transmitted and reflected (T/R) light properties. Then, during inspection, the tool scans the reticle, one swath at a time, and the algorithms compare the digitized T/R measurements at each point on the reticle against the previously constructed T/R database to identify outliers or defects.

Unlike pattern defect tools, which use a die-to-die or die-to-database comparison,

the SL3UV tool does not require a reference comparison image to identify defects.

The STARlight tools have a sensitivity limit of ~0.18 µm at the 0.25 µm pixel (P250), as measured on polystyrene latex spheres (PSLs). The tools can also be equipped with the unpatterned reticle surface analysis (URSA) option, which allows quick inspection of the chrome-side pellicle, the back glass surface and, if present, a back glass pellicle. URSA is a darkfield (off-axis illumination) inspection system which uses 690 nm laser light to look for particles, scratches or pellicle tears down to a resolution limit of ~4 µm. Figure 1 on the following page shows a schematic of an SL3UV system with STARlight and URSA. In the following sections we describe the early stages of implementation of the SL3UV inspection tools at high volume manufacturing wafer fabs. First, we discuss the reticle qualification and requalification methodology, followed by a section which compares the differences and improvements of using the SL3UV tool in a wafer fab, as compared with previous methods of reticle verification. Then, we present some data illustrating the success of these tools for reticle requalification.

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Reticle Inspection Methodology

The SL3UV reticle inspection tools in the fabs as well as at Intel Mask Operations (IMO) are connected to a central data server via Ethernet as shown in Figure 2. The data servers (KLA 9Xi) function as the central repository

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for inspection reports and also communicate with various reticle repair tools. The primary data server is where inspection reports and recipes for outgoing reticles are stored. Each tool in the fab can download the inspection report and/or recipe from the primary data server. The connectivity of multiple inspection tools to the primary data server facilitates the process of reticle IQC (incoming quality control) and reticle evaluation.

The reticle management flow is illustrated in Figure 3.

All reticles are inspected at the mask house in a final/outgoing contamination inspection, and the recipes and inspection reports are stored on the primary data server. Upon receipt at the fab, when a reticle is loaded into the tool for inspection, the tool automatically identifies and reads the barcode on the reticle and retrieves the outgoing inspection report from the primary data server. The fab engineer then reviews the outgoing inspection report and uses the inspection report (recipe) to perform an incoming inspection on the reticle, to identify any new defects added since the final inspection. Defect-free plates are sent to the exposure tools for printing wafers. If any new defects are found that fail the defect specifications, the reticle is shipped back to IMO for cleaning and re-pelliclization.

In the case of questionable defects, images of the defects are stored in the inspection report during defect review and classification. The inspection reports are then saved on the primary data server, and can be accessed for evaluation by an engineer at IMO. The decision of whether to return the reticle to IMO, or not, can thus be made quickly and more efficiently.

Primary Data

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No

Yes

Save inspection report locally

Fab engineer reviews defect

Pass?

Send mask to stepper

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SL3UV

Fab B

SL3UV

Fab C

Figure 2. Connectivity between the reticle inspection tools and the data ser ver.

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Not sure

Save defect image online for IMO review

IMO engineer reviews defects

Yes Pass?

No

Figure 3. Flowchart illustrating reticle management between IMO and the fabs.

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Generally, for each reticle loaded into the tool for incoming inspection, three surfaces are inspected: the patterned chrome surface, the chrome pellicle and the back glass surface. Depending on the process layer, the reticles are inspected at the 0.25 µm pixel (P250) or the 0.375 µm pixel (P375). The average inspection process at P375 pixel takes about 65 minutes: 45 minutes for the chrome surface STARlight inspection, five minutes for the URSA glass and pellicle inspections and 15 minutes for setup and review. At P250, the complete inspection takes about two hours. For each pixel size, the inspection times can be reduced by about 40 percent by using the Fastscan mode albeit at the cost of somewhat reduced sensitivity. Requalification is done after some pre-determined number of reticle loads and, like the incoming inspection, also includes an inspection of all three surfaces. Depending on device layer and associated defect specification, the operator identifies all defects that violate the given defect spec for the surface that is being inspected. These defects are dispositioned appropriately following the flow defined in Figure 3.

Reticle inspection versus print test

Before implementation of the UV inspection tool, legacy inspection tools with lower defect sensitivity were used to qualify all reticles for the current process. To reduce the number of false defects on the tightest layers of the processes, the previous tools were desensitized to catch only defects larger than 3 µm. This was necessary because diffraction of the blue light on the fine lines of the critical layers caused false positive signals. The pellicle can prevent most of the sub-micron sized particles/contaminants from getting on the chrome surface, keeping the probability of a repeating bad die event low. However, if such an event were to happen, the risk to wafer yield would be extremely high. Therefore, to further curb the risk of repeating bad die events, the fabs implemented print tests. First, a test wafer was printed with the reticle that needed inspection. Then the wafer was inspected on a brightfield inspection tool for repeating bad die defects. The tests consumed stepper and metrology tool time as well as engineer time for writing the recipes. Additionally, the print test was only possible to do on multi-die reticles.

The introduction of the higher resolution reticle inspection tools in the fabs has provided a number of improvements over the previous reticle qualification process (lower resolution inspection, followed by a wafer print test) and eliminated the need for print test

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verification. Some of the improvements/advantages with the new qualification methodology are: • Lower cost of reticle inspection: A wafer print test consumes about 15 minutes of scanner and track time as well as operator time. Such tools are kept fully loaded, therefore 15 minutes worth of opportunity cost from product that is not produced, is lost as well.

The wafer is inspected on a die-to-die inspection tool with high sensitivity settings. This consumes about an hour of tool time and a half an hour of operator time. Assuming a wafer average selling price of $2800, a throughput of 40 wafers per hour and 10 layers per device yields a lost opportunity cost of $2800 per mask per 15 minutes of scanner time.a Further, assuming a depreciation rate of 20 percent per year for litho equipment, the total cost associated with performing a single print test verification is about $3000.b, 2 On the other hand a full plate reticle inspection of the patterned surface, as well as the backside glass and pellicle takes about 65 minutes at the P375 inspection pixel and about two hours at the P250 pixel. If all inspections are done at the smaller pixel size (about 1.5 hours of machine time and about 30 minutes of dedicated operator time for setting up the plate and reviewing the defects), and we use similar numbers as before for the rate of depreciation of the tool and hourly operator costs, the cost of a single reticle inspection is about $150. Considerable cost savings are, therefore, realized if reticle inspection can eliminate or reduce the need for print test verification.

• Increased inspection automation: The STARlight tool inspections can be completed with little user intervention. The tool will load, align, calibrate, inspect, and unload automatically. When the inspection is completed, the technician can go back to review and disposition the inspection. In the previous methodology of reticle qualification, every reticle was run through a two step process upon initial receipt: A coarse reticle inspection, sensitivity about 3 µm, followed by a print test. This two-step process involved significantly different tools as well as required multiple engineer support. The print tests were especially demanding because they required expensive lithography tool time. An engineer was required to write a first a

b

These numbers are conservative averages taken from the literature. They do not represent specific Intel products.

Representative cost of a state-of-the-art litho cluster (scanner + track) is assumed to be $14M, approx. 4x the cost of an SL3UV inspection tool.

The costs associated with the wafer inspection tool required for the print test are ignored here.

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level job for the tools. After a wafer was exposed, a second engineer was required to write a job for the die-to-die wafer inspection tool. With the SL3UVs this process has been streamlined to a single inspection requiring a single engineer/operator.

• Standardized defect classification and memory: One inherent disadvantage of conventional reticle inspection tools over a print test methodology is the fact that reticle inspection tools may detect some fraction of defects that are unlikely to print on the wafer3 (or are smaller than the defect spec for a given layer/node). To save time reviewing defects that have previously been reviewed and passed, the SL3UV’s have a “Display New Defects” option. This option allows the operator to define a particular inspection as the baseline inspection. Generally this baseline inspection is one where the operator has carefully reviewed all of the relevant defects. Thereafter, every subsequent inspection of the reticle in the New Defects mode compares each defect found in the current inspection with the defect list in the baseline inspection, and reports only new defects. Using this feature enables the operators to ignore defects that have already been reviewed and for which a decision has already been taken, and dramatically reduces redundancy in the defect disposition process. Reviewing new defects on the pattern surface typically takes a couple of minutes. The chart in Figure 4 illustrates the effect of using the New Defects option on five product reticles. The fractional decrease in defect count, directly translates into an equivalent decrease in review time for each inspection.

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• Batch processing: The SL3UV tools can also be configured with autoloader capability to handle multiple reticles. The software allows the operator to queue up multiple inspections with different recipes, cycling through one or more of the ten slots. When the autoloader queue is completed, the operator can review all the inspections together at once. This feature increases the efficiency when a large reticle throughput is required and facilitates operator multitasking, i.e. handling of multiple tools.

• Increased sensitivity on tighter layers: The STARlight tools have a PSL sensitivity of approximately 180 nm at P250 and 269 nm at P375.

Defects of this size can be reliably detected on the patterned chrome surface without being overwhelmed by “false” defects due to scattering or diffraction effects.

• Imaging microscope integration and enhanced features: The integrated on-the-tool review capabilities of the SL3UV allow for rapid review and dispositioning of all the defects within a few minutes following an inspection. The default review screen uses a 150 nm pixel size for live image review and offers the option to apply an additional 4x zoom (electronic), as well as a user-defined bounding box to size the defect.

Total, New Defect Counts (normalized)

The use of the SL3UV tool has been especially useful in the introduction of new products to the factory and in the rush to bring them to the market. The introduction of these new products to the factory can continue without extra delays. Previously, the arrival and qualification The total defect count, which can include some of reticles would be the gating factor for delivery of nuisance or sub-spec defects, can vary considerably new products. The first lots of the product would be depending upon the reticle. However in almost every delayed by the inspection and qualification times of the case there is a significant decrease in review time in reticles that were received “just in time.” New reticles the New Defects mode. would first need to be inspected on the legacy reticle inspection tool, wait for an engineer to write a scanner job, and make a first Normalized Defect Count by Reticle level print on a test wafer. The wafer 1.2 would then be sent to the die-to-die Normalized 1 inspection tool where a second engineer Total Count 0.8 would create a recipe and inspect the Normalized 0.6 New Defect wafer. If the entire process went smooth0.4 Count ly the reticle would be qualified about 0.2 12-18 hours after it was received at the 0 factory. By using the SL3UV tool, new 1 2 3 4 5 reticles are qualified immediately upon Reticle receipt (i.e. within about two hours) and sent into production right away.

Figure 4. New Defect counts normalized by the total defect counts for five product reticles.

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attributed to a variety of factors, the trend does show a gradual improvement (decrease) in the percentage of invalid returns. We attribute this improvement in part to the improved communication/flow between the mask shop and the fabs.

0.6

Finally, we present an example where a potential killer defect was identified and caught by 0.2 the SL3UV, and the mask was appropriately handled with minimal disruption to the fab or 0 IMO. Figure 6 shows the example of a “damQ101 Q201 Q301 Q401 Q102 Q302 Q302 Q402 aged upon use” mask site that was caught Quarter using the SL3UV. This defect was initially Figure 5. Fraction of total reticles shipped that were invalid returns to the mask house missed during the reticle inspection with the from 2001-2002, normalized to Q101. Solid line is a linear fit to the data.

0.375 µm pixel, but was detected by the wafer inspection tool (KLA-Tencor 2135) during print test, as shown in Figure 6(b). However, identiReticle requalification results fication of the layer containing the defect from the As illustrated earlier (Figure 3) the SL3UV tools at wafer images was found to be very difficult due to the IMO and the fabs are connected to a central data server. defect geometry and its location.

The decision of whether to return the reticle to IMO, or not, can thus be made quickly and more efficiently.

Once the suspect mask layer was identified, the reticle Figure 5 shows the proportion of total reticles shipped was re-inspected at tighter sensitivity on the SL3UV that were returned to the mask shop for “invalid” reasons (with the 0.25 µm pixel) and the defect was detected over the period 2001-2002. This period also coincides with a 100 percent capture rate. A saved image of the with the introduction and proliferation of SL3UV tools defect was then reviewed electronically with IMO into the fabs. The solid line in the figure is a linear fit to engineers, and the mask was removed from the producthe data over the two-year period. Though fluctuations tion line. This entire problem was resolved without in the return rate from one quarter to another can be shipping the reticle back to IMO. 0.4

Figure 6. (a) Reflected light image of defect on horizontal line pattern taken on the SL3UV at 0.25 µm pixel. (b) Image of the same site from the wafer inspection tool. The defect area is marked.

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Whereas the above event illustrates the value of having an effective reticle management system, it also points out the importance of selection of the inspection pixel on the SL3UV system. As with any inspection system, defect sensitivity of the tool depends upon the feature size and half pitch on the reticle. For optimal performance the pixel size should be selected such that the background pattern is well sampled. This is specified as

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steady decline of reticle returns for nuisance/invalid reasons from the wafer fabs to the mask shop, have resulted in increased productivity at both ends of the line.

Acknowledgements

For the SL3UV the required minimum primary feature linewidth is 750 nm for the P375 inspection pixel and 500 nm for the P250 inspection pixel.

From Intel we would like to thank Rajesh Nagpal for detailed comments on the paper, and Kraig Kottenstette and Barbara Greenebaum for their help with the wafer inspection tool. From KLA-Tencor we wish to thank Jim Wiley, Christian Desplat, Bill Volk and Gary Peacock for their ideas and suggestions, and Charika Becker, Bar Houston and Chris Aquino for applications assistance during the early stages of this project.

Conclusions

References

The SL3UV tools, connected to a central data server at Intel Mask Operations, are being used to provide an integrated solution for reticle management at Intel fabs.

Use of these tools not only provides a significant relief from the high opportunity cost of using steppers for print test verification, but also streamlines the communication between the fabs and the mask shop. The automation and “new defects” features on these tools enable faster incoming qualification (IQC), particularly for new product reticles. Shorter IQC and requalification times, and a

1. Dayal, A., Sanchez, P., Eschbach, F., Vargas, A. & Kim, J., Proc. SPIE Vol 4689 (2002), pp 45-52.

2. Muzio, E “Optical Lithography Cost of Ownership- final st report for LITG501” International Sematech, Oct 31 2000.

3. Bald, D., Munir, S., Lieberman, B., Howard, W.H. & Mack, C.A, Proc. SPIE, Vol 4889 (2002), pp 263-270.

1 Inspection Pixel Size ≤ * Primary Feature Linewidth 2

This article was presented at SPIE Microlithography Conference, February 2003, Santa Clara, California, USA. Proceedings 2003 SPIE Microlithography Conference, Vol. 5038, pp. 1153-1160.

To register online for the upcoming YMS, please visit us at: http://www.kla-tencor.com/seminar Date: Time: Location:

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Munich, Germany San Francisco, California Singapore Hsinchu, Taiwan

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Techniques for Evaluating Reticle Inspection Equipment for 130 nm Lithography and Beyond James A. Reynolds, Reynolds Consulting

The cost of losing a lot of 300 mm wafers is enormous and the impact of an undetected reticle defect that damages hundreds or even thousands of wafers can run into the millions of dollars. The most effective way to prevent this loss is to perform a reticle inspection at regular intervals as the reticle is used. Effective reticle qualification requires the selection of reticle inspection equipment which will perform fast, accurate screening of current product reticles and will remain viable for several generations of products into the future. This article provides a comprehensive methodology for selecting reticle defect inspection equipment for wafer lithography applications.

Introduction

Shrinking design rules and low k1 lithography bring an increased sensitivity to reticle defects during the wafer printing process.1 A single, printable reticle defect that destroys the chip in which it resides can reduce the yield of a fab area by 25 percent in the case of a four die reticle, and up to 100 percent in the case of a single die reticle. The increase in wafer cost, particularly at 300 mm, intensifies the adverse financial impact of such yield losses. Great care is taken by wafer lithographers to interact with reticle suppliers to generate defect specifications which will prevent this occurrence. Indeed, much of the expertise of a modern mask shop centers on the prevention, detection and repair of these defects.

The task of inspection, however, does not end when a reticle is delivered to the lithographer and placed production. In the first place, many wafer lithographers prefer to do an incoming quality control (IQC) on the reticle to assure the reticle manufacturer has met the specifications. Second, a large body of evidence exists2 showing that

defects can actually grow under the pellicle of a once defect-free reticle, causing a printable, and in some unfortunate cases, a killer defect. The defects are particles, crystal growth, and electrostatic damage (ESD) to name a few (Figure 1). The ultimate cost of such defects has been known to run into the hundreds of millions of dollars per incident. In cases where the proper reticle inspection equipment and a rigorous procedure for its use are in place, the incidence of catastrophic reticle defects has been reduced, effectively, to zero.

Clearly, wafer lithographers must enter the world of reticle defect inspection.

The purpose of this article is to assist the user in selecting the best reticle inspection tool for IQC and reticle qualification at each wafer fab site. First, it is important to establish the goals of the inspection program with respect to application, defect size and design rule. Some goal setting considerations will be presented. Second, and most important, it is essential to select a suite of test reticles that will thoroughly evaluate the tools under consideration with respect to sensitivity and inspectability, but also from the standpoint of ease and speed of operation. Some commonly available test reticles will be described. Next the actual evaluation process will be discussed, emphasizing hands-on operation of Spring 2004

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Appearance

Cause Caused by handling reticle and inducing electrostatic charge which breaks down quartz at corners and small gaps. These defects grow over time and must be detected before they become printable.

ESD Defects

Caused by photochemical reaction between pellicle adhesive and other chemical compounds with chrome/quartz surface.

Crystal Growth

Caused by contamination at pelliclization station at reticle vendor, or particle movement under pellicle.

Particles

Figure 1. Photographs of reticle defects which have been created under pellicles after reticle manufacture and may cause wafer damage.

the system and witnessing of the running of the test plates. Finally, there will be a section on how to assemble the evaluation data and make a final equipment choice.

Goals

The first goal to follow is to look beyond the specification sheet provided by the inspection system vendor.

These specifications are provided to set a predetermined performance level for inspection system acceptance.

The only way to determine actual performance is to allow for a thorough system capability evaluation.

One of the best sources of information on setting goals for an inspection program is the reticle manufacturer.

Reticle inspection engineers spend much of their time evaluating reticle inspection equipment and deciding which is best for each inspection challenge. Most are willing to share this wisdom with good customers.

Node

Minimum 4X Geometry (line space)

Minimum 4X OPC feature

Printable defect @ 4X

130 nm

360 nm

180 nm

104 nm

115 nm

300 nm

150 nm

90 nm

90 nm

260 nm

130 nm

80 nm

Table 1. Defect detection requirements according to the ITRS Roadmap.

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Because of the high cost of the reticle inspection equipment, the program goals should be based on at least the next two generations of product introductions. If 130 nm is in current wafer production, the reticle inspection equipment typically desired would be capable of also doing pilot reticles at 90 nm. Once this decision is made, the International Technology Roadmap for Semiconductors (ITRS) will yield a fairly simple table of requirements for defect size sensitivity, pattern inspect-ability (i.e. the minimum pattern size which can be inspected without too many false defects). See Table 1.

It is important to decide on the specific applications intended so the correct equipment can be determined. Table 2 shows several such choices.

If IQC is intended, the inspection system suite should match that of the reticle manufacturer, providing full die-to-die and/or die-to-database capabilities for detection of hard pattern defects. For reticle re-qualification, simultaneous transmitted and reflected light systems are recommended. They are fast and highly sensitive.

These strategies are outlined in Table 1.

In addition to these plans, a rigorous operational regime must be implemented to make most effective use of the equip-ment. In addition to operating procedures for the equip-ment, such a plan should include frequency of inspection and defect size requirements for each type of reticle.

Part of the equipment selection plan should include time and resources to travel to the inspection system manufacturer and do hands on demonstrations of the equipment. Only then is it possible to observe the ease

Application

Type of defect to be found

Inspection technology

Specific system Names (KLA-Tencor products)

IQC

Pattern defects and contamination

Die to database + die to die

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Reticle Re-qualification

Contamination only

Transmitted & reflected light

TeraSTAR with STARlight inspection

Table 2. Recommended equipment for different inspection applications.

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of system operation, the ease of defect classification and the absence of small sensitivity-improving adjustments during the inspection of test reticles. Resources for test reticle acquisition should also be anticipated.

Selecting the test reticle

A common mistake in the selection of a test reticle is to present to the equipment vendor a single reticle, frequently the very one which has a printable defect that caused a recent yield loss. Most probably, this defect will be easily found by all types of reticle inspection equipment. Finding this single large defect is no guarantee that the system will also find much smaller and more subtle defects which will also cause killer defects on wafers. It is far better to use a suite of reticles (including the problem reticle) which will exercise all areas of equipment performance.

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demonstrate sensitivity and false defect performance with the same system settings.

No special sensitivity options activated — Some inspection systems have so called “cell to cell” mode which is automatically activated when repeating identical cells are detected. Sensitivity is increased in these areas. Since uniform sensitivity over the entire reticle is the real life requirement, a test reticle should be used that prohibits “cell to cell” mode.

This is accomplished by randomly varying the cell size in which a programmed defect appears.

Many such reticles have been developed and used by reticle and equipment manufacturers for inspection system purchase decisions. Table 3 shows some of these designs and states their advantages and disadvantages.

Highest quality manufacturing — It is vital that the test reticles be made by the most exacting reticle manufacturing techniques. Common reticle errors such as stripe butting errors and CD variations will be detected by the most advanced inspection systems causing the system to be less sensitive to the programmed defects. Under these conditions, the comparative results will be clouded. The system manufacturer should either have plates which are satisfactory or provide information on where they can be purchased.

Selection criteria for test reticles

An ideal reticle suite might consist of the following:

Defects in “real life” geometries — It is beneficial for test reticles to simulate actual device geometries where possible. This forces the system to find defects in environments similar to those it will encounter in a actual product reticle. Naturally, the test reticle may not exactly match the designs being inspected but they should present a typical situation.

Redundant defects — For assessing sensitivity, it is important to have multiple identical defects. This will allow rapid assessment of sensitivity and easy location of problem defects. At least three identical defects in identical surroundings for each defect type and size increment is recommended.

Small defect incrementing — Most inspection systems will find a 300 nm defect and will not find a 30 nm defect. The way to truly differentiate between systems is to use a test reticle with small defect increments so the true sensitivity differences can be demonstrated. A 15 nm increment is recommended.

Testing false defect detection capability — The layout of a test reticle is very important. Newer test reticle designs allow the comparison of two non-defective die for the purpose of determining the occurrence of false defect detections. System vendors are then forced to

REYCON 2 — for defects in random geometry and testing of false defect detection capability REYCON 3 — for defects in contacts and testing of false defect detection capability CETUS — for defects in contacts measured by transmitted flux UIS — for inspectability of simulated patterns which cause problems for reticle inspection Running the evaluation

As stated earlier, it is imperative to conduct a defect inspection equipment evaluation in person and to observe, first hand, the operation of the inspection system.

Most inspection system vendors will accommodate this requirement. This is the best way to observe not only the system operation but to determine the capability of the manufacturer to manufacture systems reliably and to support them in the field. Typically three to five days will be required for this activity.

Items to accomplish during visit System overview — The reticle inspection system Spring 2004

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SPICA KLA-Tencor

Defects in simulated device geometry at 15 nm increments

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CETUS KLA-Tencor

Defects in contacts from 1% to 30% flux increment

Excellent for difficult contact defects.

Good incrementing

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Orion KLA-Tencor

PSL spheres down to 80 nm

Only true contamination standard

Defect location not known without first inspecting reticle

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Programmed defect test masks for lines and spaces, and contact holes

Universal, Impartial

Available for larger features

Reycons 2 KLA-Tencor

Defects in simulated device geometry down to 600 nm size and 30 nm increment

Excellent for “Real Life” test.

Good incrementing

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Reycons 3 KLA-Tencor

Defects in simulated contacts down to 600 nm and 30 nm increment

Excellent for difficult contact defects

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UIS DuPont

Many different feature types

Good for inspectability tests

None

Verimask DuPont

Many defect types with defect sizes down to 54 nm at 54 nm increment

Universally used

Equipment can be tuned to detect these defects only

Table 3. Available test reticles for inspection equipment evaluation in order of technology.

vendor should present information on how the system works and how it is operated. This should include information on the number of systems in the field, percentage uptime achieved, field service strength, upgrade paths and roadmaps for future technology improvements.

System setup — The steps required to set up the system to run the test plates should be thoroughly explained. This should include a discussion on all of the sensitivity and inspectability options available and the way these options are stated on the inspection report.

Classification — This very critical step can only be evaluated first hand. The system optics must be good enough to do accurate and fast classification of the defect sites established during scanning. If it is hard to see the defects, an operator might either misclassify a defect or ignore it altogether. This misclassification could cause a real defect to be classified as a false defect, resulting in a defective reticle being used on wafers.

System operation

Reporting — The system should be capable of manipulating data and generating useful accurate reports which contain all of the system parameters used in the inspection.

Scanning — The plates should be set up and scanned by the system. It is useful to note the time required to start and complete this operation as a guide to what throughput can be achieved. Typically 10 scans should be made to accurately demonstrate the system’s capability.

The evaluation event should leave the prospective user with the feeling that the system will do the job and that the company behind the system can keep it running and upgrade it as required by future technology improvements.

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Data reduction

A typical defect inspection event, such as the evaluation of a test reticle, produces a large amount of data consisting of system set up information followed by a complete listing of all of the defects found. To create useful information from this report, the defect coordinates must be compared with the known locations of programmed defects on the test reticle. Looking up the size of the programmed defect at that location makes it possible to determine the detection sensitivity of the system (i.e. what was the smallest defect of each type that was found).

This can involve a massive amount of work unless the process is automated by the equipment vendor. It is important to establish that this capability exists before beginning the evaluation.

Finally, for the data to be useful, it must be plotted on a chart similar to Figure 2. Here the detection requirement for the planned nodes is compared with the detection capability of the system for each of the defect types on the test reticle. Note in the example shown

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that, while there were variations in the sensitivity of the system to different kinds of defects, all were detected 100 percent of the time (10 inspections were made) down to the 100 nm level. This indicates that the system is satisfactory for the 130 nm node. Testing of this type on multiple test reticles will guarantee that the inspection system will satisfy the requirements for IQC and reticle qualification.

Final decision

When the testing is finished and all the reports are complete, a decision about system purchase can be made.

The overriding concern is to pick a system which has sufficient defect detection capability to find printable defects that will cause the loss of wafers and to give early warning to degradation of reticle quality due to progressive defects like particles, crystal growth, and ESD. All other criteria are secondary to this. The cost of a wafer yield mysteriously dropping to 75 percent or 33 percent, or even 0 percent, is just too high to compromise on this vital parameter. Defect detection capability must be sufficient for the generation of product being run now as well as for one or two planned future generations.

When two systems compare favorably from this standpoint, the other points such as company stability, system extendability, and ease of system operation should be compared.

Reticle defects generated after pelliclization which affect more than ten lots are being reported at higher rates each year. The financial impact of these events is huge. Wafer manufacturers who have taken the time to select the proper reticle inspection equipment have reduced their losses from post fabrication reticle defects to near zero.

References 1. A. Nhiev, J. Hickethier, H. Zhou, T. Hutchinson, A Study of Defect Measurement Techniques and Corresponding Affects on the Lithographic Process Window for 193nm EPSM Photomask, Proc. BACUS 2003.

2. B. Grenon, K. Bhattacharyya, W. Volk, A. Poock, Reticle Surface Contaminants and Their Relationship to Sub-pellicle Particle Formation, Proc. BACUS SPIE 2003.

K. Bhattacharyya, W. Volk, B. Grenon, C. Peters, Formation and Detection of Sub-Pellicle Defects by Exposure to DUV System Illumination, Proc. BACUS SPIE 1999.

Figure 2. Plot of detected defect level versus size for defects on a test reticle â&#x20AC;&#x201D; with a line showing requirements for that specific node.

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Seeing Through the Haze Process Monitoring and Qualification Using Comprehensive Surface Data Frank Holsteyns, Jan Roels, Quoc Toan Le, Karine Kenis, Paul W. Mertens, IMEC

Haze, the low frequency signal of light scattering on unpatterned wafer, is already accessible on the Surfscan SP1 in most fabs and contains very useful surface information. It can be used as a proxy for other metrology tools to measure thickness, reflectivity, roughness, defects, and can be integrated in SPC tests for equipment monitoring. When combined with defect measurements, it provides additional wafer surface information unrevealed by defect monitoring alone.

Introduction Max LPD

Area

LPD

Min LPD Noise

Haze, the low frequency signal of light scattering on unpatterned wafers is a common technique used in semiconductor production fabs to monitor and qualify a variety of process steps. The information distilled out of the captured scattering light is two-fold: 1) scattering events (light point defects) used to count and size particles, and 2) haze, or the background scattering signal (Figure 1). This study shows that haze, collected as the low frequency signal from a darkfield inspection tool, is a very effective way to gather surface information. The analysis of the haze data can be used as a powerful tool to evaluate process performance concerning defectivity, uniformity, roughness, sealing, etc.

{ Actual Haze

Figure 1. The captured scattered light consists of light point defects (LPD) and the haze signal.

Light scattering tools

In this study, we focus on the use of the KLA-Tencor Surfscan SP1DLS unpatterned wafer inspection tool to extract the haze signal from the toolâ&#x20AC;&#x2122;s scattered signal. The wafer is illuminated by a laser, with a beam either normal to the wafer surface or oblique (70° to the normal). The scattered light, coming from different defects as well as the background of the wafer surface, is collected 50

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by two separate channels. The low frequency component of the signal of these channels is given as the haze signal, expressed as scattering power fraction per area of detector to the total incident power (ppm/Star radial).

Haze reference wafers To validate the haze signal, a set of standard calibration wafers was developed on a SEZ spin processor. These wafers, which remained stable over time and were

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Technical Intervention 4 Haze wafer 1 Haze wafer 2 Haze wafer 3 Haze wafer 4

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Monitoring with haze The haze signal monitoring capability on KLA-Tencorâ&#x20AC;&#x2122;s Surfscan SP1DLS unpatterned wafer inspection tool can be used in many ways: as a measure of nano-sized particles (<50 nm) density, surface roughness of metallic layers, grain size variations, and to inspect small process defects induced in CMP and deposition processes The new MX 4.0 haze normalization option further allows normalized haze data to be used for thorough monitoring of process excursions in wafer and IC fabs as the tool inspects wafers and captures defects.

Fluctuations in process parameters, such as temperature and pressure, often cause deviations in poly grain size during the poly gate process, one of the most critical steps in DRAM device production. These deviations can lead to lower-binning products or device failures.

One example of haze monitoring of grain size variation for a rugged poly process is shown below:

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0 Bi-weekly Monitoring Figure 2. Bi-weekly monitoring of the SP1 with different haze wafers.

Haze Monitor

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cleanable, allowed us to evaluate tool stability and to perform tool-to-tool comparisons for different light scattering tools. As shown in Figure 2, a set of different standard haze wafers is used as a reference to monitor the haze signal over time for the different channels of the SP1 (in this case the darkfield wide oblique channel). A good reference is necessary, since a shift in haze value was observed after a technical intervention with the inspection tool.

Normalized haze measurement can be used for poly furnace pro-

Avg. Haze [ppm/Sr]

duction monitoring.

The creation of these different haze standards, using varying surface roughnesses, allows us to link AFM measurements (RMS (nm)) with haze (ppm/Sr). Figure 3 demonstrates that most of the SP1 channels are very sensitive for changes in roughness, especially for wafers with a particular frequency diagram.

0.1

DWO DNO DWN DNN

0.01

0.2

RMS [nm]

0.3

Figure 3. Relation between AFM (RMS) and SP1 (Haze) measurements for five different wafers.

The creation of these standard haze wafers provided the opportunity to integrate the haze data as an evaluation tool in the statistical process control (SPC) methods, enabling process excursions to be flagged.

Process monitoring and qualification

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it is important that, in addition to light point defects (LPDs), the haze data in defect detection is taken into account to understand and monitor a broader spectrum of process-induced variations.

tool), absolute reflectivity (using the FT-700 tool), and sheet resistance (using the RS75 resistivity measurement tool). From an earlier study,1 the relation between reflectivity and haze was shown. This makes it possible to replace the 49-point reflectivity measurement (Figure 4), of the FT-700 and replace it with a full wafer plot from the SP1. By doing so, this measurement â&#x20AC;&#x201D; using oblique incident beam and s-s-s polarization (for beam and two detectors) â&#x20AC;&#x201D; can be combined with the particle measurement. An upper spec limit for haze can be determined (using the maximum reflectivity laid down by the tool manufacturer) and set for the process (Figure 5). A sequence of variations observed in the final haze value (but still in spec) of the W could be related to the use of reclaim wafers of lesser quality. The excursion was due to a variation in the process conditions: a fluctuation in temperature).

CVD and PVD processes

Ta/TaN Layer

A

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79refl/Si% 80ppm/sr

Figure 4. Output file haze measurement (A) and a reflectivity measurement (B).

For CVD and PVD processes, the surface roughness and spatial frequency of metallic layers like tungsten (W) and tantalum/tantalum nitride (Ta/TaN), and the thickness uniformity and roughness for transparent layers like silicon oxynitride (SiO2), low-k and photoresist (typically spin-on processes), can be evaluated using haze data. Thickness information can be extracted because the standing waves in the metallic layer cause different laser light intensities at the top layer. The haze signal can be related to other metrology data such as reflectivity, thickness and sheet resistance. The benefits of using the haze signal as a proxy for other metrology steps are that it can be combined with particle measurements, it has a very short process time that reduces overall inspection time, and a full wafer map is provided.

Tungsten CVD process

Avg. Haze [ppm/Sr]

Tungsten CVD processes are evaluated in SPC tests on particles (using the SP1 unpatterned wafer inspection 90 80 70 60 50 40 30 20 10 0

Temperature out of spec

Upper spec limit

Reclaim wafers

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Figure 5. Weekly monitoring of the W-CVD process in the prototyping line.

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The study of the Ta/TaN layers2 focuses more on the sensitivity of the detectors (varying sensitivities for different scattering angles) for different spatial frequencies (see the power spectral density diagram) of the wafer surface. The higher the spatial frequency, the more light will be scattered to the wide detector. The ratio of the detectors to the frequency of the wafer surfaces provides information about the overall morphology of the surface under consideration. Therefore, we could conclude that a deposition process with a higher bias provides smoother surfaces (Figure 6). AFM images confirm these findings,for the 50-50 and the 128-128 bias setting (biasTaN-biasTa). Similarly, the copper-seed layer can be evaluated, and the self-anneal process for the different stacks can be monitored by the haze channel of the SP1. Control of this self anneal process plays a role in the suppression of defects like void formation during plating. Haze information for the barrier and copper-seed layers allows us to select the optimum material for the process, as well as to set specs for equipment SPC tests.

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Oxide deposition Oxide deposition processes can be monitored for uniformity or roughness by the haze channel. Both measurements are determined by polarizing the light in different ways. The uniformity can be evaluated by the S-polarization. The SP1 haze plot can be compared with the thickness plot of the KLA-Tencor SpectraFx thin film metrology tool (Figure 7). Any surface uniformity problem can be detected by the SP1, but not quantified. The surface roughness and also possible defect regions can be evaluated by C-polarization. The

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Daily Monitoring Figure 8. SPC tests for 200 nm oxide using haze and the LPD channel.

Cooling problems are monitored with haze in five cases, and with the 0.10

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Figure 6. HF/LF ratio for different Ta/TaN barriers and AFM measurements. Higher bias provides a smoother surface.

SPC tests for particles can be extended to the measurement of haze and particles. As shown in Figure 8, the role of haze can play an important role in identifying tool defects; in this particular case, wafer cooling problems. It is interesting to note that, in all cases, haze data indicates process problems, unlike the LPD channel.

Nano-particles The industry is facing new challenges concerning particle removal beyond the resolution of the state of the art light scattering tools (φLSE <50 nm). The limitations of

A

being able to measure wafers with small particles and/or in high densities can be overcome at the full-wafer level by using haze. This method3 can be used to evaluate performance and uniformity for cleaning tools like megasonic cleaners (Figure 9). A lot of 30 nm particles are not removed by megasonics due to the shadowing effect of the wafer carrier. Based on the Raleigh approximation, a simple model is developed to describe the added haze of a wafer ηadd due to a higher density of particles σ.

ηadd = Ωtool • Πpart • σ In this equation, Ωtool stands for the tool constant (influenced by laser-light-wavelength and optical characteristics) and Πpart for the particle constant (influenced by parameters like diameter and refractive index). The added haze increases proportionally to the particle

B 3 x 1014 #/cm3

228nm zone

PRE (%) 55 - 90 25 - 55 0 - 25

251nm zone +

Low-mass carrier

Below Calculated Mean Above Calculated Mean

Transduce array

Figure 7. Output file of (A) a haze measurement and (B) a thickness

Figure 9. An evaluation of a megasonic cleaning tool for 30 nm SiO 2

measurement.

particles. The SEM review tool is used to count particles.

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2500 2000 1500 1000 500 0 -500 25 Figure 11. On the left, a haze plot after toluene treatment; on the

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Presence of crystals

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Figure 10. SPC tests for a batch stripper, haze and LPDs are given, in

right, a decorated defect which caused the sealing problem.

dielectrics, after CMP, treated with toluene and measured with the SP1. This haze data is analysed using the MX4.0 haze analysis capability of the SP1. The results reveal the easily-neglected condition that a clear sealing is lacking at the edge of the wafer and at certain points on the wafer surface, due to the presence of big particles.

some cases only haze is measured.

density. Using SEM review, a clear relationship can be then established between haze and particle density.

Cleaning performance A spray acid tool (batch stripper) is used for chemical cleaning, stripping and etching. For the daily SPC tests, a blank silicon wafer is processed with H2SO4/H2O2 (10:1 ratio) for 10 minutes at 95 degrees C. In addition to detecting traditional particle defects, haze is useful for identifying other process problems. For example, when the rinse step following the acid step is not performing well, sulfuric residues will remain on the wafer surface and form ammonium sulfate crystals.4 The haze signal will be high because of the presence of these crystals. Figure 10 illustrates that the haze signal is too high with respect to the target value set for the Si wafers (0.05 ppm). To detect these problems and test the effectiveness of the cleaning process, the haze data is necessary, and can be simultaneously used with the LPD data.

Sealing defects The combination of solvent adsorption and haze allows sealing defects at the surface (BEOL) to be localized and quantified. Results on different hardmasks (HM)/dielectric stacks, such as CVD HM on CVD dielectric, CVD HM on spin-on dielectric, and spin-on HM on spin-on dielectric, can be easily evaluated.

Figure 11 provides an example of a CVD HM on CVD

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Aknowledgemens

The author would like to thank the Surfscan Division of KLA-Tencor for the fruitful and interesting cooperation in this study, and SEZ for the creation of the haze reference wafers.

This article was originally presented at the 2003 ISSM Conference. Proceedings of the 2003 IEEE International Symposium on Semiconductor Manufacturing, September 30 to October 2, San Jose, California, USA. Refernces 1. F. Holsteyns et al., “Process Monitoring and qualification of CVD/PVD tools using comprehensive surface haze information,” presented at the KLA-Tencor Yield Management Seminar, Japan, 2002.

2. L. Carbonell et al., “Defectivity study of Cu Metallization Process by Dark- and Bright-Field inspection,” Solid State Phenomena, vol. 92, pp 281-286, 2003.

3. K. Xu et al., “Relation between Particle Density and Haze on a Wafer: a new approach to measuring Nano-Sized Particles,” Solid State Phenomena, vol. 92, pp 161-164, 2003.

4. A.L.P. Rotondaro et al., “Interaction of Sulphuric Acid Hydrogen Peroxide Mixture with Silicon Surfaces,” Proceedings of the 2nd international symposium on ultraclean processing of silicon surfaces, pp 301-304, 1994.

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Simulating the Impact of Reticle Defects A Study of Defect Measurement Techniques and Corresponding Effects on the Lithographic Process for a 193 nm EPSM Photomask Anthony Nhiev, Jason Hickethier, DuPont Photomasks Haiqing Zhou, Texas Instruments Trent Hutchinson, William Howard, Mohsen Ahmadian, KLA-Tencor Corporation

Photomasks with small dense features and high mask error enhancement factor (MEEF) lithography processes require stringent reticle quality control. The ability to quickly and accurately measure reticle defects on a high-resolution inspection system and to simulate their impact on wafer printing are key components in ensuring photomask quality. Tests show that the inspection system can quickly and accurately determine sizes of most defects. The study also indicates that the simulation techniques can accurately tract the lithographic results, and can be used to reduce or eliminate the use of test wafers and expensive lithography and wafer metrology time. The outcome of this study leads to better defect dispositioning by providing techniques to determine the size and printability of reticle defects.

Introduction

Photomask manufacturers typically repair masks when any visible defect is found during reticle inspection. This repair adds extra steps to the manufacturing process and increases the risk of damage to the mask. With a comprehensive analysis of defect sizing techniques, and modeling the impact to the wafer of various defect types and sizes, a better decision can be made concerning whether an individual defect will have an effect on the lithographic process. This is also beneficial to device manufacturers who periodically re-inspect photomasks between production lots and must decide when a mask needs to be replaced due to increasing number of defects. This paper will look at size measurements made by UV and DUV reticle inspection systems compared to SEM measurements on the mask. It will then model individual defects through hardware-based and software-based aerial imaging simulation to determine the impact of the defect

at nominal focus/exposure. The modeling will be compared to SEM measurements on the wafer.

Test vehicle

The programmed defect mask selected for this analysis is the DuPont Photomask VT491â&#x201E;˘ Verithoro design.

The mask is an embedded phase shift mask (EPSM) designed for 193 nm lithography. The photomask is fabricated with six percent transmission molybdenum silicide (MoSi) on quartz blank. The VT491 mask has a nominal design circuit of 400 nm space (reticle scale) with a 1:2 ratio pitch. The nominal contact design is 900 nm at reticle scale with a pitch of two microns. There are 20 defect types, each ranging in design size of 0 to 450 nm in 50 nm steps (reticle scale). The mask is designed to run in die-to-die inspection mode, with the programmed defect die in the middle of a seven by one die array. Figure 1 shows the defect types, design, and SEM sizes, as well as the 100 percent capture rate (shown by the darkened cells) and review measurement size found in each of two UV and one DUV inspection systems.

Columns 5-9 have been omitted from this chart, as these larger defects are found by the inspection 100 percent of the time and would always be transferred to the wafer.

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Figure 1. Defect types, design, SEM, review sizes, and capture rate (shaded). All sizes are reticle scale in nanometers. For the design images shown in the table, black represents a space in the EPSM material. A “*” indicates the features did not resolve on the photomask. A “**” indicates that the features were found during inspection but cannot be measured with review linewidth measurement software.

Photomask CDSEM analysis

Each of the 200 defects were manually measured on the mask with a KLA-Tencor 8250-XPR™ low voltage CDSEM at 1000eV. The system was calibrated using a 1000 nm pitch standard supplied with the system. The measurements were taken at the appropriate scan rotation to reflect accurate measurements of defects on corners and angled lines. High-resolution images of each defect were captured at 100,000 magnification. The 56

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defect size recorded is the maximum extent of the defect relative to the “0” column, where no defect is present.

Typical repeatability of a CDSEM measurement is better than 2 nm (3 sigma).

Photomask inspection and review

Three KLA-Tencor inspection systems (two TeraStar SLF-77™ UV and one TeraScan DUV 525™ model) were used to inspect the test mask in die-to-die mode.

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For each system, four inspections were conducted to complete the repeatability and sensitivity analysis.

Each of the captured defects was measured using the review linewidth measurement software included with the systems. The defect sizes were graphed as a function of SEM measurements. Sensitivity analysis was performed and is shown in Figure 1. The pin-hole and pin-dot defects were detected as shown by the shading in the table. However, the linewidth, measurement review software failed to measure their size. Figures 2-4 show some of the typical defect types.

Row A - Clear Extension on 30 Degree Space 0.600 0.500 0.400 0.300

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Figure 2. Row A, inspection system size as a function of SEM measurement. SEM image of mask, and SLF review image.

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Figure 3. Row E, inspection system size as a function of SEM measurement. SEM image of mask, and SLF review image.

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Nikon model-S305™. The standard 100 nm node DUV moat resist process was used to print the wafers. The two bare silicon wafers were first coated with DUV BARC of 0.043 µm, and then coated with DUV resist of 0.23 µm. For rows A-L, Q, and R, best exposure was determined to be 46 mJ/cm2 at a focus offset of - 0.25 microns. For the contact rows M-P, S, and T, the best exposure was 38 mJ/cm2 at a focus offset of - 0.25 microns. Wafers were analyzed using the KLA-Tencor 8250-XPR CDSEM at 800eV. All 200 programmed defects were measured at best focus and exposure.

Measurements were performed at a scan rotation perpendicular to the defect and reflect the maximum CD change from the reference (0) column. Figure 5 displays the design defect size along with the change in CD (absolute value) using three methods: wafer SEM measurement, AIMS, and TeraSim. AIMS simulation and analysis

AIMS simulation was conducted and compared for accuracy and ease-of-use with the wafer printing results. This optical lithography simulation consisted of AIMS (aerial image measurement system) Fab 193™ from Carl Zeiss, the most common system used for final qualification and dispositioning of reticle defects.

It is a hardware-based simulator that requires the mask to be loaded to obtain high-resolution images that approximate the aerial image when exposed with a DUV lithographic scanner. The illumination condition was set to match the scanner’s settings. AIMS results were measured using five-pixel averaging over the reference and defect area. Intensity values were measured and recorded for both clear and dark geometry. Using the AIMS software linewidth versus threshold plot, reference regions were used to set an intensity threshold that resulted in a printed CD corresponding to the non-defective nominal space and pitch of the reticle scale. This intensity threshold was then applied to each defect region to measure CD impact on the wafer. Clear reference calibrations for image normalization was acquired approximately every hour to reduce the error attributed to laser instability.

Figures 6 and 7 show typical defects, AIMSFab simulation and actual mask measurements versus wafer SEM measurements. The mask values were divided by four to account for the scanner reduction. All three inspection systems match the mask SEM measurements very well. The AIMS results have a good correlation to the printed wafer results.

Figure 4. Row Q, inspection system size as a function of SEM measurement. SEM images (reference and test) of mask, and SLF review image.

Wafer printing and analysis

Two focus exposure matrix wafers were printed with the test mask using a 193 nm DUV lithographic scanner,

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Figure 5. Defect type, design size, SEM, AIMS, and TeraSim measured sizes. All sizes are wafer scale in nanometers. A “*” indicates that the defect did not resolve on the wafer or the AIMS-FAB and TeraSim modeling suggested the programmed defects would not have resolved. A “**” indicates that the main feature did not print or was not predicted to print by simulation.

Simulation and analysis

A new prototype version of TeraSim™, KLA-Tencor’s reticle defect printability software, was used to simulate the lithographic impact of the programmed defects. The simulation settings were adjusted to match the hardware simulations made with the 193 AIMS Fab system for scanner wavelength, NA, and illumination condition.

Defect and reference transmitted light images were stored after the TeraScan inspection and were converted to bitmapped images. These bitmapped images are 58

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converted into a pair of defect and reference simulation masks used to predict the aerial image at best focus. The lithographic impact was evaluated using two methods.

First, the intensity difference metric (IDM) was calculated as described below. Consultations with various AIMS users have shown that most use a single-value intensity metric to judge the printability of reticle defects. Further, it is common to use a standard of ten percent for determining whether a defect should or

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Figure 6. Row M, inspection review, reticle SEM CD, and AIMS CD versus wafer SEM CD measurements (units in microns).

Figure 8a. A simulation mask with chrome extension (left) and the resulting aerial image intensity along a horizontal slice centered on the defect (right). The nominal peak and trough intensities of the aerial images are shown with dashed horizontal lines and the drop in inten-

Inspection Review, Reticle SEM CD, and AIM CD Measurements

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sity of the peak is shown with a solid line.

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| .62-.58 | /(.62-.20)

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Figure 7. Row Q, inspection review, reticle SEM CD, and AIMS CD

-500

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Figure 8b. A simulation mask with quartz extension (left) and the resulting aerial image intensity along a horizontal slice centered on

versus wafer SEM CD measurements (units in microns).

the defect (right). The nominal peak and trough intensities of the aerial

should not be repaired. That is, if the intensity metric is less than 10 percent, the defect is not repaired. As part of this study, we used such a metric to determine how it can be used to better understand and quantify the printability issue. The IDM is defined by equation 1: IDM =100%x

IRef – ITest MaxRange

(1)

The values in the numerator are taken at the location where the test and reference aerial images differ by the largest amount. Using the absolute value ensures that the IDM is always a positive number expressed as a percent. The denominator is the normalization factor, which is calculated from the maximum range of the aerial images in the vicinity of the defect location. For the results presented here, the IDM was calculated using the prototype version of TeraSim, which can read AIMS data. The AIMS test and reference data were processed using the same software used to process the simulated aerial images from TeraSim.

images are shown with dashed horizontal lines and the increase in intensity of the trough is shown with a solid line.

IDM = 100% x

| .25-.20 | /(.62-.20)

= 11.9%.

An example of a comparison between AIMS and TeraSim based on IDM is shown in Figure 9. The R-series defect is an over-sized clear horizontal line shown in black near the bottom of the cell. The IDM increases monotonically with defect size, as one would expect, and the match between TeraSim and AIMS is good.

A second comparison was made by matching the predicted change in critical dimension (CD) from AIMS and TeraSim to the actual wafer CD change measured on the CDSEM. The AIMS data was processed by the AIMS operator at DPI, and the TeraSim data was processed using the new prototype version. Both AIMS and TeraSim results are contour plots of simulated aerial image intensity. To extract CD values from these data, the edges must first be located by selecting a particular threshold contour. This is done by calibrating to several non-defective Spring 2004

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features on the wafer. This calibration step is done independently for the AIMS and TeraSim data. After this calibration, the CD difference values were calculated at each of the defective sites. The simulated CD change from TeraSim and AIMS can then be compared to each other and the wafer print results. When one makes such a comparison, caution must be exercised, because the AIMS and TeraSim data are simulations of the aerial image which do not take into account the resist processing effects. For example, previous research has shown that line end shortening (LES) is caused by multiple effects and that a portion of LES is caused by resist processing.4 Therefore, the amount of LES predicted by simulating an aerial image will normally be less than that seen on the wafer.

An example of this comparison is shown in Figure 10.

The K-series defect is a misshapen EPSM feature shown in white on the left side of the cell. The change in CD increases monotonically with defect size, as one would expect, and the match between TeraSim, AIMS and wafer print data is good.

In this paper we demonstrated that the inspection station review tool is capable of predicting the size of defects Predicted/Measured Wafer CD Change [nm}

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within ± 50 nm for a normal line/space geometry and over/undersize contact. However, pinhole and pin dot defect types are less predictable. This study showed that both UV-based and DUV inspection systems are capable of detecting these defect types well below 200 nm, but AIMS and wafer printing correlation revealed they have no significant impact on printability. To produce highly accurate prediction beyond the inspection review tool, AIMS and TeraSim simulations can be used to estimate defects on complex design circuitry. AIMS system is well known within the industry for accuracy in simulating the lithographic process, and this data shows that the AIMS results correlate well with wafer printing. It requires the extra step of loading the mask, changing hardware settings, and capturing image for simulation.

TeraSim software-based simulation achieves results comparable to AIMS system with inspection captured images as input. TeraSim is PC based software, and must use KLA-Tencor X-link™ software package to import review images. TeraSim has the advantage that its use does not require any additional handling of the reticle.

Acknowledgement

The authors would like to acknowledge Kevin Rentzsch (DuPont Photomasks, Inc.) for his assistance in setup of KLA-Tencor CD SEM file of all 200-defect on the mask; and Carl Siniard (DuPont Photomasks, Inc.) for his support in collecting AIMS data.

A version of this article was presented at the 23rd Annual BACUS Symposium on Photomask Technology, September 2003, Monterey, California, USA. Published in the 2003 BACUS Symposium proceedings Vol. 5256, pp. 1120-1129.

References

Conclusion

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1. L. Pang, B. Volk, J. X. Chen, et. al. “Simulation-based Defect Printability Analysis on Alternating Phase Shifting Masks for 193nm Lithography” Proc. SPIE Vol. 4889, pp. 947-954.

2. W. D. Kim, S. Akima, C. Aquino, and et. al. “Mask Inspection Challenges for 90nm and 130nm Device Technology Nodes: Inspection Sensitivity and Printability Study using SEMI Standard Programmed Defect Mask” Proc. SPIE Vol. 4889, pp. 972-983.

3. L. Zurbrick, J. Lee, and et. al. “Reticle programmed defect size measurement using low voltage SEM and pattern recognition techniques” Proc. SPIE Vol. 3996, pp. 64-70.

4. V. Wiaux, V. Philipsen, R. Jonckheere, G. Vandenberghe, S. Verhaegen, T. Hoffmann, K. Ronse, W. Howard, W. Maurer, and M. Preil, “Assessment of OPC Effectiveness Using Two-Dimensional Metrics,” Optical Microlithography XV, Proc., SPIE 4691.

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WestWorld Attendees’ Choice Award KLA-Tencor’s eS30 receives SST’s WestWorld Attendees’ Choice Award for Best Solution to a eS30 overcomes Problem. The electrical defects in the producXXtion process, providingXXXX XXXchipmakers with electrical defect monitoring strategiesX for high-volume production,XXXXX XXXXXwhich increases yields and ROI.XXXX Best Solution To A Problem: KLA-Tencor’s e-beam inspection system combines speed and sensitivity

KLA-Tencor won the “best solution to a problem” award at the wafer-processing portion of Semicon West for its eS30 e-beam inspection system. From left to right: Todd Henry, senior director of marketing, E-beam Inspection Div.; Bob Haavind, editor in chief, SST; Stan Yarbro, group VP of worldwide operations, Customer Group; and Ken Schroeder, CEO. Solid State Technology, September, 2003 Copyright © 2003 — PennWell Corporation

The eS30 e-beam inspection system provides the throughput and production worthiness required for electrical line monitoring. The eS30 combines speed, sensitivity, and ease-of-use into a single platform for all phases of the IC technology lifecycle, enabling chipmakers to reap gains in yield and fab ROI. Significant reductions in tool overhead, including wafer loading and set-up time, coupled with faster scanning speed and easeof-use enhancements, effectively triple the throughput of the eS30 compared to the manufacturer’s eS20XP system to enable whole-wafer, high sensitivity inspection in under an hour for many applications.

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Product News PROLITH v8.0

With PROLITH v8.0’s new multi-measurement capability, lithographers can determine best overall process settings.

PROLITH v8.0 can easily identify outof-spec features.

PROLITH v8.0 can create an overlapping process window in one step that simultaneously accounts for all critical dimensions and measurements.

PROLITH v8.0 Benefits • Helps determine best overall process settings • Optimizes total feature performance on the most advanced device layouts • Provides critical feature data from the exact location required • Enables investigation of process and technology tradeoffs including LIL • Provides faster analyses and decisions with multi-measurement capability

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As feature sizes continue to shrink, lithography processes are being pushed to their limits. Lithography simulation essentially must solve complex problems in both reticle and wafer manufacturing as lithographers push existing 248-nm and 193-nm technologies to smaller and smaller feature sizes through the use of increasingly complex techniques, such as off axis illumination, phase-shifted reticles, and double exposure processes. This level of sophistication demands that simulation tools be accurate, versatile, easy to use, and fast in order to support decision making across a wide range of technologies, processes, and materials.

Leading the way in this critical emerging area of lithography management is KLA-Tencor’s PROLITH software, the industry’s leading lithography simulation tool. PROLITH’s optical lithography modeling capabilities enable customers to maximize yield, more rapidly implement new processes and technologies, and increase their lithography equipment utilization.

The newest PROLITH release, version 8.0, allows lithographers to be even more efficient in resolving lithography simulation problems. With a new multi-measurement capability, lithographers can determine the best overall process settings, enabling creation of an overlapping process window that simultaneously accounts for all critical dimensions and measurements.

PROLITH v8.0 enables measurement of up to 11 different locations on a cross-section and up to 22 additional, top-down dimensions with the PROLITH 3D option. These additional measurements take no additional simulation time. Additionally, metrology planes can be added or moved using a table or by drawing or dragging on a graph. Whether measuring aerial images, resist profiles, or anything in between, additional measurement information significantly helps shrink decision time. PROLITH v8.0 also includes a simulation capability for liquid immersion lithography (LIL), enabling determination of the potential performance advantages of this new process technology in meeting specific device and technology requirements.

Other new features/benefits: • Quick viewing of full-chip GDSII or MEBES design files • Evaluation of the impact of using a different polarization setting for each pass on the exposure tool, which helps determine which exposure process gives the best lithography process results • Measurement of features on diagonals or on any angle, optimizing total feature performance on today’s most advanced device layouts • Metrology data along planes that do not start or stop at a simulation grid point. New flexibility assures necessary information from the exact location desired • Wider range of template files allows designation of default PROLITH input values so they correspond to common technology nodes, making starting point closer to actual process • Improved PROLITH Programming Interface (PPI) documentation. PPI now includes low-level commands for working with multiple metrology planes Yield Management Solutions

MetriX 100™

MetriX 100 is the industry’s first inline, non-contact metal films metrology system to provide independent measurements of film composition and thickness on product wafers. Controlling film composition and stoichiometry of new materials introduced in production of 90-nm and below devices is as important as controlling film thickness. With its versatile electron-beam technology, MetriX 100 leapfrogs current techniques, bringing a well understood and proven technology to the production floor that, for the first time, enables chipmakers to address this new challenge. This system offers advanced capabilities that meet thin film process control requirements for the 90-nm and below nodes, including SiON gate dielectric, bi-layer TaN/Ta barrier seed, and ultra-thin atomic layer deposition (ALD) barrier films.

MetriX 100

Utilizing electron beam stimulated x-ray technology (ESX), MetriX 100’s electron beam stimulates characteristic x-rays and quantifies the x-ray intensity into composition and film thickness data. MetriX 100 also reduces the use of monitor wafers to lower manufacturing costs through small-spot measurements in the scribe line of product wafers. An easy-touse UI enables fast, highly reliable measurements, while remote diagnostics and support capabilities ensure high in-fab productivity. Providing highly precise non-contact films measurement on product wafers, MetriX 100 incorporates the latest 300-mm advanced automation requirements, remote diagnostics, and the same user interface as the production-proven SpectraFx 100 dielectric films metrology system.

MX 4.0 (Monitor eXpert)

MX 4.0 software for KLA-Tencor’s Surfscan SP1 unpatterned wafer inspection system enables the Surfscan SP1 tool to conduct defect detection and process monitoring in a single scan — providing a fast and cost-effective alternative to many time-consuming and manual process-monitoring steps with little additional overhead. MX 4.0 enhances existing software features and introduces three new major software options that provide the SP1 with new inspection and process monitoring capabilities.

Haze normalization introduces the ability to match haze measurements between SP1 systems. Haze analysis, a powerful software analysis feature, models and detects haze defects in the SP1 haze map. Brightfield sizing enables the SP1 to provide consistent brightfield inspection results from tool to tool, taking this capability beyond engineering analysis to production worthy inspection. MX 4.0 also provides valuable new defect analysis and process monitoring capabilities for wafer and IC production that improve the SP1’s data reporting for backside inspection, haze measurements, and analysis and brightfield inspection.

Spring 2004

MX 4.0 brightfield scans allow Surfscan SP1 to detect large-area defects such as slurr y burns during wafer IQC.

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LITHOGRAPHY

Sunday, February 22, 2004 6:00 - 9:00 pm USERS FORUM

Register online at www.kla-tencor.com/spie > FREE EVENT <

Join us at KLA-Tencor’s 5 th annual

Lithography Users Forum .

Featuring technical papers on advanced solutions for CD and overlay control, photocell monitoring, simulation techniques for immersion lithography ...and more.

Keynote address by: Dr. Frank Schellenberg, Mentor Graphics “What DFM Really Means”

Location: Techmart Silicon Valley Room 5201 Great America Pkwy Santa Clara, CA 95054