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The Fine Line Between Design Rule Violations and Reticle Defects Identifying Process Window Marginalities of Reticle Designs

S. C. Lo, L. K. Hsieh, J. B. Yeh, Y. C. Pai, Will Tseng, United Microelectronics Corporation Mahatma Lin, Ingrid Peterson KLA-Tencor Corporation

The complexity of resolution enhancements techniques (RETs) will increase dramatically over the next four generations of optical lithography, requiring careful qualification of new reticle designs when they arrive at the wafer fab and before commiting them to printing product. Low k1 and high MEF lithography increase the printability and frequency of yield impacting repeating defects from reticle defects and RET layout errors. Therefore, reticle qualification must encompass mask processing errors as well as RET design rule violations. Identification of mask processing errors is performed on a reticle inspection tool; RET design rule violations are identified by a wafer inspection tool after printing wafers with a specific layout using the reticles of interest. The output from the wafer inspection tool, followed by detailed analysis, provides information on the regions of marginality within the reticle field or features within the die which have smaller process windows than expected. We call this the process window qualification output (PWQ output), and it can be applied to single and multi-die reticle designs. In this paper we describe how we used the PWQ methodology to identify RET design errors for three different reticle designs.

Introduction

With the continued delay in the introduction of next-generation lithography, the semiconductor industry has been compelled to adopt increasingly complex RETs in order to extend optical lithography below the 100-nm node. Currently, design rule check (DRC) and optical rule check (ORC) software models are used to verify that the design and RETs are done correctly on reticles designs at the physical design level. These models, however, are only approximations based on optimal focus and exposure conditions, and are not designed to simulate the entire lithography process window. As a result, even if a reticle is manufactured to specification and is defect free, RET features can still fall outside the process window

and cause significant yield loss. Since these pattern anomalies are marginalities in the reticle design rather than defects on the reticle, they cannot be detected using reticle inspection.

In addition, some defect types, including repair-induced QZ damage and OPC-induced CD errors, could easily pass incoming reticle qualification inspections.1 At low-k1 lithography, it is increasingly more difficult and risky to judge if a reticle defect will print based on reticle inspection results alone and fix specifications without verifying the process window through focus.

The capability of the mask shops to confirm whether the reticles perform as expected is also very difficult, and not currently possible to the satisfaction of many integrated device manufacturers. Although reticle defect printability by simulation was reported to have some promising results,2, 3 it is not yet widely used by Spring 2004

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both mask shops and wafer fabs. The demand for developing a reliable and precise methodology to evaluate mask defect acceptability between mask shop and wafer fab is increasing.

To address this challenge, new approaches and ideas must be explored and implemented to qualify the image produced by the cumulative effect of various configurations of illumination sources, optical proximity correction (OPC) artifacts, phase shifted imaging, and various photo chemical processes used at the imaging plane. In this paper, an effective methodology, PWQ (process window qualification) on a high resolution imaging wafer inspection system is introduced. This methodology is used in conjunction with reticle inspection to evaluate the impact of reticle manufacturing as well as RET design rule violations for 0.13 µm and 0.15 µm design rules on 300 mm wafers using KrF photoresist processes. The narrowing process window (primarily reduced depth of focus) is used to intentionally amplify any unexpected patterning behavior. The method described increases the capture rate of so-called “marginal features” or “transient” features that sometimes depend on the coincidental confluence of exposure, focus, illumination, and RET patterning at the wafer plane. Furthermore, this paper will discuss the experimental results on capture capability and efficiency of phase error defects and OPC-induced defects, which were not detected by standard reticle inspection tools.

It will suggest that the combination of PWQ and mask inspection tools is the optimal solution to effectively detect all intolerable defects on a mask.

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Methodology

Wafer Preparation and Inspection Bare wafers were processed through coat and developing steps in a TEL ACT12 track using KrF photoresists.

The wafers were exposed on an iASML AT750 Scanner with 0.13/0.15 µm reticles. Similar to conventional focus and exposure matrix used in fabs, the stepping array of exposure was modified to modulate focus/energy every two columns in the same row as shown in Figure 1.

The modulated focus/energy is only on the “B” columns, where “A” columns are at constant focus and exposure.

This procedure may also be adapted to optimize sigma (partial coherence), numerical aperture (NA) and various illumination modes. Focus and energy are used in this study because these parameters are the most likely to vary from day-to-day and tool-to-tool on the production floor. Optimizing other lithographic parameters will depend on the exposure tool’s ability to actively modulate the desired parameter shot by shot. Wafers were inspected using KLA-Tencor’s 2351 high-resolution imaging patterned wafer defect inspector. By applying a double detection algorithm enabled by the layout strategy, any anomalies due to the narrowing process of the”B” column on the wafers can be easily detected when compared with its neighbor, the “A” column. 300 mm wafers allow three or four iterations of “AAB” columns, enabling double detection and subsequent determination of the die where an event is located. Previous experimentation revealed that inspecting the wafers after etch and resist strip could increase the sensitivity of the defect detection.

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Figure 1. PWQ exposure array.

Figure 2. PWQ Analysis sequence.

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These “marginal” features appear as bridged narrow spaces when viewed on the printed wafer (see Figure 4).

Reticle images of the same area are also shown in Figure 4. Reticle inspection did not flag any defects when inspecting in die-to-die or die-to-database.

Subsequent verification of the reticle design revealed the root cause of the failed features to be the extremely narrow process window of gaps between gate pattern blocks. This was not detected during OPC rule check.

The original spacing of 0.664 µm (reticle dimension) for the gate pattern blocks was too small to be resolved; a revised spacing of 0.776 µm was necessary to achieve a feasible process window. PWQ supplemented insufficient OPC rule check capabilities and provided feedback to reticle design engineering personnel. This case study demonstrates that sizing errors occurring during OPC reduced the process window, resulting in “marginal” features-the trench between gate blocks. Correct sizing resulted in a wide process window for both semidense and the trench pattern as illustrated in Figure 5.

Analysis The results of the inspections were analyzed using KLA-Tencor’s Klarity Defect, defect analysis software.

The purpose of the analysis is to find the potential “transient” repeating features associated with the reticle designs on wafers. These repeating transient features are reviewed on the wafer and on the reticle after the appropriate coordinate translation. Once the “transient” repeating features are identified, the lithography engineering staff needs to determine how to overcome the narrow process window of these features. The complete analysis sequence is illustrated in Figure 2.

A = Exposed at best exposure/focus (40.5 mj/-0.1 µm) B = Exposed at various exposure/focus offset

0.15 µm Contact Attenuated PSM Reticle Defect map of Exposure offset (a) Exposure modulation

This 0.15-µm logic device attenuated PSM reticle had one known OPC error. PWQ detected the known OPC error and found additional OPC errors as well as phase errors (see Figures 6 and 7). A smaller focus process window (-0.05 ± 0.15 µm)

Defect map of Focus offset (b) Focus modulation

Figure 3. Wafer inspection results for the PWQ exposure arrays; gate reticle.

Results and Discussion of Case Studies

0.13 µm Gate Reticle The PWQ exposure arrays of a 0.13 µm design rule logic device (binary OPC) reticle are shown in Figure 3. The “transient” or “marginal” features detected by the wafer inspection tool are shown in blue in Figure 5. The overlap in the process windows of the “marginal” features and other critical features in this reticle design was determined to be less than 0.07 µm focus process window; therefore, reducing the feasible focus window considerably for this reticle design.

The expected focus window for this reticle design was previously determined to be 0.4 µm.

Reticle Image

Wafer Image

Reticle Image

Wafer Image

Figure 4. Reticle inspection (left) and wafer inspection camera (right) images of the “marginal” features.

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Sizing error

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Usable Process Window: 40.5± 1.5 mj/-0.1± -0.2 µm Figure 5. Process window results for the “marginal” features compared with the process window for the other features in the device. The blue line represents the “semi-dense” process window, whereas the red line represents the process window for the “marginal” features.

associated with these marginal features was observed by over-lapping the process window of the “marginal” features with the optimal process window (0.1 ± 0.25 µm) of other critical features in the device. Analysis revealed that the OPC sizing and phase errors were neither flagged by optical rule check nor detected by reticle inspection (die-to-die). Since CDs are measured in the scribe-line and not in the die, CD metrology also failed to detect this issue during production.

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Rule-based OPC was used in the design of this reticle. The errors detected by PWQ would have had a significant impact on the electrical properties of the device; therefore, it was necessary to revise the reticle. In order to avoid interruption of the production line, an interim strategy was implemented, which allowed the utilization of the original reticle until a new one was delivered. A few hot lots were printed with a different illumination mode in order to verify the feasibility of this approach. Approximately 10 lots were printed before the new reticle was received.

It took approximately four working days to re-tool and manufacture a new reticle. Had the problem on this reticle not been detected before production lots were processed, it could have potentially cost approximately $1.0 million in yield loss since, in all probability, the wafers would have reached electrical test before the problem was detected.

In order to increase the wafer inspection sensitivity, wafers were etched and the resist was stripped. A more aggressive inspection was implemented after etch and the results are shown in Figure 8 [this excludes high defect count and defocus rows in previous after develop inspection (ADI)]. No extra OPC or phase errors were found during the after etch inspection; however, it was noted that, after reviewing some of the new repeating defects, many small CD variations ranging from 0.01 to 0.02 µm were detected, especially for focus A = Exposed at best focus (60 mj/0.1 µm) B = Exposed at various exposure/focus offset exceeding 0.25 µm. An example of this small CD variation is shown in Figure 9. The impact of these small CD variations on this particular product’s reliability should be negligible since they are within processing specification. The exact root cause of the small CD variation was not identified; one possible explanation could be the effect of the convolution of small lithography (e.g., focus) and etch process variations (e.g., chamber conditions) of these experimental wafers. As 193 nm lithography evolves and even more Defect map of Focus offset Defect map of Exposure offset aggressive RET is implemented, this approach may be implemented to gain (a) Exposure modulation (b) Focus modulation additional inspection sensitivity.

Figure 6. Wafer defect map and PWQ exposure arrays for the contact reticle.

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were used in this reticle design. Design rule check (DRC) and optical rule check (ORC) failed to “flag” that the gap between the scattering bars for several patterns in the design was below specifications. As expected, reticle inspection in die-to-database and die-to-die failed to detect this RET design rule error since it compares the reticle image with the design or adjacent die with the same error. PWQ quickly confirmed that the scattering bars did not print within the focus and exposure process window. Figure 11 shows SEM images of the features at the edges of the exposure process window. These results allowed a quick decision to be made; production lots were run while further CD process window characterization was carried out, and a new reticle was designed and manufactured.

Figure 7. Reticle inspection (bottom) and wafer inspection camera (top) images of the “marginal” features detected by PWQ.

Conclusions

In summary, PWQ successfully demonstrates the capability to detect “marginal” features that can further reduce the already narrow process window for current 0.13/0.15 µm technologies.

Next generation 0.11/0.09 µm lithography processes will be much more challenging, adding greater complexity to the reticle design and manufacturing. Even with the most sophisticated OPC models, however, you still need to verify the reticle design by printing wafers for each tool set once the new reticle design reaches the wafer fab.

Defect map of Exposure offset

Defect map of Focus offset

Figure 8. Wafer inspection results of after etch inspection of the contact reticle.

These results above showed no significant differences in the results of the ADI and after etch inspections. There are however, two advantages of implementing PWQ at ADI. The first one is faster time to results since all “marginal” features can be detected at ADI; and, the other is the cost effectiveness due to the flexibility of recycling wafers after developing (wafers cannot be recycled after etch).

A combination of PWQ and conventional reticle inspections (die-to-die/die-to-database)

A shot with best focus (0.1 µm)

B shot with focus (0.25 µm)

0.13 µm Assist Bar Gate Reticle In this case study, PWQ was used to verify the printability of scattering or assist bars “flagged” to be dangerously close to the gate pattern, by the reticle inspection system (see Figure 10). Model and rule-based OPC as well as scattering or assist bars

CD difference = 0.0226 µm Figure 9. Example of small CD variation.

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Figure 10. Reticle inspection image (right) and CAD design image showing the small gap between the scattering bar and gate feature.

References

Figure 11. SEM images of the feature at the edges of the process window.

constitute the ideal solution for production and mask engineering control.

Acknowledgements

The authors would like to acknowledge Tony DiBiase and Sagar Kekare of KLA-Tencor’s yield technology solutions division for their valuable advice and suggestions.

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1. William Chou et al., “Characterization of Repairs to KrF 300mm Wafer Printability for 0.13 (m Design Rule with Attenuated Phase Shafting Mask”, 22nd Annual BACUS Symposium on Photomask Technology, Vol. 4889, pp. 498-508, 2002.

2. J. Kim et al., “Alternating PSM Phase Defect Printability for 100nm KrF Lithography, SPIE Vol.3998, pp308-320, 2000.

3. Khoi Phan et al., “Comparison of Binary Mask Defect Printability Analysis Using Virtual Stepper and Aerial Image Microscope System”, 19th Annual Symposium on Photomask Technology, pp. 681-692, 1999.