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The Fine Line Between Design Rule Violations and Reticle Defects Identifying Process Window Marginalities of Reticle Designs

S. C. Lo, L. K. Hsieh, J. B. Yeh, Y. C. Pai, Will Tseng, United Microelectronics Corporation Mahatma Lin, Ingrid Peterson KLA-Tencor Corporation

The complexity of resolution enhancements techniques (RETs) will increase dramatically over the next four generations of optical lithography, requiring careful qualification of new reticle designs when they arrive at the wafer fab and before commiting them to printing product. Low k1 and high MEF lithography increase the printability and frequency of yield impacting repeating defects from reticle defects and RET layout errors. Therefore, reticle qualification must encompass mask processing errors as well as RET design rule violations. Identification of mask processing errors is performed on a reticle inspection tool; RET design rule violations are identified by a wafer inspection tool after printing wafers with a specific layout using the reticles of interest. The output from the wafer inspection tool, followed by detailed analysis, provides information on the regions of marginality within the reticle field or features within the die which have smaller process windows than expected. We call this the process window qualification output (PWQ output), and it can be applied to single and multi-die reticle designs. In this paper we describe how we used the PWQ methodology to identify RET design errors for three different reticle designs.

Introduction

With the continued delay in the introduction of next-generation lithography, the semiconductor industry has been compelled to adopt increasingly complex RETs in order to extend optical lithography below the 100-nm node. Currently, design rule check (DRC) and optical rule check (ORC) software models are used to verify that the design and RETs are done correctly on reticles designs at the physical design level. These models, however, are only approximations based on optimal focus and exposure conditions, and are not designed to simulate the entire lithography process window. As a result, even if a reticle is manufactured to specification and is defect free, RET features can still fall outside the process window

and cause significant yield loss. Since these pattern anomalies are marginalities in the reticle design rather than defects on the reticle, they cannot be detected using reticle inspection. In addition, some defect types, including repair-induced QZ damage and OPC-induced CD errors, could easily pass incoming reticle qualification inspections.1 At low-k1 lithography, it is increasingly more difficult and risky to judge if a reticle defect will print based on reticle inspection results alone and fix specifications without verifying the process window through focus. The capability of the mask shops to confirm whether the reticles perform as expected is also very difficult, and not currently possible to the satisfaction of many integrated device manufacturers. Although reticle defect printability by simulation was reported to have some promising results,2, 3 it is not yet widely used by Spring 2004

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