Spring06 automating investigation

Lithography M

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Automating Investigation of Line Width Roughness Full Spectral Analysis Enables Benchmarking of New Resists L.H.A. Leunissen, M. Ercken and J. A. Croon, IMEC

G.F. Lorusso, H. Yang, A. Azordegan and T. DiBiase, KLA-Tencor Corporation

One of the most commonly used estimators of line width roughness (LWR) is the standard deviation. However, this approach is incomplete and ignores a substantial amount of information. As an alternative, full spectral analysis can be used to investigate and monitor LWR. A variety of estimators—including standard deviation, peak-to-valley, average, correlation length, and Fourier analysis—have been implemented online on CD SEM. The algorithms were successfully tested against e-beam written LWR patterns, both deterministic and random. This methodology, which allows a fully automated investigation of LWR, was used to monitor LWR over a long period of time, benchmark new resists, and to investigate the effect of LWR on device performance and yield.

Introduction The importance of LWR for future technology nodes has been demonstrated in various experimental and theoretical investigations.

However, although it is clear that LWR will influence device performances and production yield, not to mention metrology strategies, the quantitative details are still

controversial. This information is crucial in order to define specific guidelines and monitoring criteria. Furthermore, it has been recently pointed out that a measurement of LWR alone does not guarantee the full characterization of the physical phenomenon under investigation. A full spectral analysis is needed. In the case of self-affine edges, for example, it has been demonstrated that a set of three parameters is required to define the physical system: the LWR standard deviation s, the correlation length x, containing spectral information on the edges, and the fractal exponent a, related to the kind of diffusion process involved in the physical creation of the edges.

In this study, we use full spectral analysis of LWR to investigate the effect of LWR on yield, precision, and resist characterization. All of the algorithms used in this investigation are now implemented online on the eCD series of KLA-Tencor CD SEMs. The availability of these algorithms on the monitoring tool is essential in order to allow LWR characterization in a production environment. A purposely designed LWR standard, created by means of direct e-beam writing, has tested the performance of the measurement algorithms in terms of accuracy and precision.

In order to experimentally evaluate the effect of LWR on yield, direct e-beam writing was used to create devices with varying degrees of LWR. This allowed us to estimate the experimental parameters in the proposed LWR model, so we could specify the requirements needed to set up a monitoring procedure. This article reports LWR monitoring data over a period of about four months.

The experimental results of the monitoring confirmed various assumptions of the model, such as the normal distribution of the LWR population and the validity of the self-affine hypothesis. The procedure reported here is intended to describe the various steps needed to design LWR monitoring in a production environment.

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Although the influence of LWR on yield attracts much attention, the relationship between line edge roughness (LER) and precision is critical and often underestimated.

This investigation compares the functional dependence of critical dimension (CD) precision on LWR, correlation length and gate placement error, and compares the theoretical predictions with experimental measurements.

Finally, an online LWR algorithm is used to quantify the difference in performances of resists and topcoats for immersion lithography. These results indicate that LWR measurement algorithms are a critical metrology tool in a variety of applications not strictly related to process monitoring.

Experimental conditions

The measurement algorithms used to characterize LWR in this work are now fully available on the KLA-Tencor CD SEMs in the eCD family. They are capable of measuring various LWR estimators, such as sigma, peakto-valley, and average delta, as well as correlation length and power spectrum. They allow exporting of all of the edge information for further analysis. The accuracy and reliability of the algorithms were tested by means of e-beam written LER standards. Figure 1 shows an image of a deterministic LER standard. The use of these standards allowed fine-tuning and characterization of the performances of the algorithms. The LWR precision for two consecutive measurements in the same site was estimated to be 0.2 nm.

Figure 1: SEM image of a LWR standard written by e-beam lithography (Leica VB6-HR). These standards were used to tune and characterize the online algorithms, as well as to create devices with various degrees of LWR.

In order to test the yield model, and estimate its parameters, transistors with additional LWR were created.

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The resist line patterns were generated with additional programmed LER using e-beam lithography. On both sides of the original line, small rectangles were taken, of which the dose was altered. The dose was randomly varied between all of the small rectangles, thus resulting in a varying linewidth. The nominal linewidth was close to 62 nm. The rectangles presented here have a length of 60 or 120 nm, resulting in a range of correlation lengths. The dose range was chosen to have various LWR. After the e-beam lithography step, the processing was continued with etching of the poly-Si, resist strip, and SiON removal.

In order to determine the effect of gate placement error on precision for a sample with known roughness characteristics, we simulated the effect of gate misplacement on a set of experimental results on a sample with well characterized LWR and correlation. The experimental results were then compared with the analytical prediction.

For the experimental LWR monitoring, IMEC’s current standard C013 gate process monitor (130 nm node design rules) was chosen. Litho target CD was 110 nm.

Targeted gate etch CD was 70 nm. To achieve this 40 nm CD loss during etch, resist and hardmask trim was applied during the etch process. This monitor was run bi-weekly. In each monitor batch, two wafers were selected for measuring the LWR (only after etch). Per wafer, five dies were measured (center, north, east, south, and west) and for each die, the LWR measurement was averaged over 20 sites along a long line. This procedure was applied seven times.

Currently, IMEC is screening several dedicated ‘wet’ resists and topcoats for the start-up of the immersion program on their ASML XT:1250Di. Results shown in this article were still performed on the ASML PAS5500/1100 ‘dry’ system. All resists were exposed on ARC29A (Brewer/Nissan Chemical) as organic bottom anti-reflective coating. Resist thickness applied was 150 nm. Vendor-recommended process conditions were applied. All resist coating was done manually (pipets). Target pitch resolution (150 nm) was achieved using dipole illumination, 0.89/0.65s @ 0.75 NA. The topcoats investigated also needed to be applied manually. An optimal thickness was chosen for reflection control.

LWR description

Many factors contribute to LWR, including resist composition1, aerial image contrast1,2,3,4 development1,4 and

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process conditions3, 4, 5. The LWR is usually characterized by the 3s value, where the standard deviation (s) is defined as:

(1)

where dW(zi) is the deviation from the average linewidth dW and N is the number of measurement points.

It is not sufficient to measure only the 3s variation5, 6, 7.

A more complete description of the LWR can be obtained by measuring the full spatial frequency dependence of the roughness. All this makes the comparison and quantification of line edge roughness more difficult.

Besides s, the spatial frequency components can be resolved using a power spectral density (PSD) function, height-height correlation function, or by assuming a first-order autoregressive process. The spatial frequency dependence can be described by two additional parameters that quantify the spatial aspects of LWR: the roughness exponent (a) and the correlation length (x).

The roughness exponent is associated with the fractal dimension D (a=2-D)8 and its physical meaning is that it gives the relative contribution of high frequency fluctuations to LWR. Large values of a signify less high frequency fluctuations. On the other hand, the correlation length denotes the distance after which the edge points can be considered uncorrelated.

Impact of LWR on yield

Poly gates of devices exhibit a certain linewidth roughness. Generally, parameters that describe the operation of the MOS device are a function of its gate length (L) (Note that the gate length of a MOSFET is equal to the width of the poly line). Roughness causes this length to locally vary over the width (W) of the device. This roughness causes an increase in parameter fluctuations and off-state current. It can also give rise to yield loss.

In this section we will calculate the impact of LWR on yield for devices. The CD distribution as found experimentally in Figure 4 and Figure 8 shows that the population is normally distributed, which results in the following probability density function

(2)

with <L> the average linewidth and sLWR the local CD variation. We take the following variable DL=L-<L>/sLWR

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having dDL=dL/sLWR. We assume that a segment causes the whole device to fail if its length is smaller than a certain critical length (Lcrit). Therefore, we need the cumulative distribution function, which gives the probability that L<Lcrit. The chance that this happens for one segment (pseg ) is:

(3)

The device contains W/x segments depending on the width. When W<x, the chance that one device is failed is equal to pseg (min{1,W/x]=1). To calculate the chance that a device is not working (pdev), the device is divided into segments with width x. Each segment is considered to have a constant gate length that varies with sLWR. This yields:

(4)

Finally, the yield of a circuit with Ndev identical devices can be calculated to be:

(5)

It is assumed that the circuit only functions when all of its devices are working. Transistors with different line edge roughness were used to test this yield model. A rather arbitrary failure criterion was chosen, namely the appearance of punch-through, which will demonstrate the mode nicely. Punch-through reduces the control of the gate on the off-state current, which causes it to bend upwards. Mathematically, this translates into: the device fails when d2lnID/dVGS2 > 0 at VGS=0 V10. Figure 2 shows the fraction of working transistors as a function of the gate width for smooth transistors and the two cases where extra roughness was introduced. The correlation length x and LWR s are indicated in the plot, as determined by SEM pictures. The induced correlation length is increased with respect to the initial values because they are convoluted with the intrinsic correlation length of the resist (about 40 nm). It is seen that Equation (5) gives a reasonably good fit to the experimental data with Lcrit@50 nm (the accuracy is somewhat limited due to a sample size of only ~60 devices per point). It follows that Lcrit= Lnominal - 16.5 nm.

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LWR monitoring

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In Figure 4, we show the LWR distribution obtained during our monitoring for about 600 measurements.

The population is clearly normal, as evidenced by the Gaussian fit. We estimated an average LWR of 2.3 nm, with a standard deviation for the individual measurement of 0.34 nm. As a consequence, the precision of the estimated LWR is 0.04 nm. These results confirm the assumption on normality of the LWR stochastic process, used earlier to calculate the effect on the yield. Besides LWR, we also monitored correlation length and fractal exponent. The correlation length resulted in 34.5 nm, with a precision of 1.2 nm on this estimate, while the fractal a was 0.55, with a precision of 0.009.

punch-through, as a function of the number of devices for three gate patterning

processes with intrinsically different LER characteristics.

Technology Node

22 nm 35 nm 45 nm 65 nm 90 nm 130 nm

Transistor 3sLWR (<L> - Lcrit)/3 Gate Length per Chip (ITRS) [nm] (calc.) [nm] [nm] 8.85E+09 4.42E+09 2.21E+09 1.11E+09 5.53E+08 2.76E+08

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Using the simple model, we want to determine the impact on a large-scale design. Therefore, we consider a digital circuit with a large number of devices and assume W=x =L using the numbers as given in Table 1.

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Figure 4: Experiments found distribution of the LWR (solid line) and a fitted Gaussian (dashed line).

Inserting the numbers in Equations (3)-(5), we calculate the yield for a given sLWR. Figure 3 displays the yield for the applied parameters for the 130 nm node down to the 22 nm node, respectively. We consider here a device failed when more than 0.1% of its components do not satisfy the requirement for critical length.

Figure 5 shows the combined results for the first four different monitoring days, 100 measurements each.

The information on the LWR can be extracted by using three different characterization functions: (a) structure function, (b) power spectrum, and (c) dependence of the &

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Figure 3: Yield as a function of different technology nodes as calculated using Eq.(5). The parameters as defined in Table 1 are used.

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Figure 5: Typical behavior of the three different characterization functions: (a) structure function, (b) power spectrum, and (c) dependence of the LWR on gate length.

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LWR on gate length. The plot shows the average functions measured in each monitoring. The repeatability of the four estimators is evident: the different monitoring yields essentially the same curve, since the stochastic process is essentially the same. There are, however, differences in between the three approaches. The structure function is definitively a better estimator for the correlation length and the fractal dimension as compared to the power spectrum or the s(L), and it contains information on each of the three parameters.

The results in Figure 5 demonstrate experimentally that the LWR is indeed a self-affine process, as previously assumed. The three curves are essentially identical to the simulations by Constantoudis et al. in13, thus confirming that the full description is achieved with a three-parameter model, where the descriptors are s, a, and x. The results also validate the hypothesis that the knee in the power spectrum is indeed related to the correlation length.

We notice also that the estimate of the sigma from the edges appears to be slightly smaller as compared to the one from the three estimator functions (2.3 nm versus 2.5 nm). This is indeed accounted by the autoregressive model of s(L). The monitored sinf=2.5 nm after correcting for the limited field of view.

By using our estimate of s and x, we define the yield criteria from an earlier section of this article for a CD=75.8 nm (Figure 6).

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for distances smaller than the correlation length (x) there exists a dependency of the data. We assume a first-order autoregressive process R(x) as defined by

(6)

with sinf representing the sigma at the low frequency limit (long box length). Then, the following two-parameter equation can be derived that fits the sigma variation with increasing box length L12, 14:

(7)

Therefore, if the smeas(L) measured for a given length is smaller than sinf, the portion of the LWR that is not measured is the CD variation (sCDU) contribution of the resist that can be calculated using

(8)

In the next section of this article, we discuss the effect of LWR, correlation length, box length, and positioning error on CD precision. Suppose that the box length of the measured line is large such that s(L)~sinf. The consequence is that repetitive measurements yield the same results. Repeating measurements for shorter lengths result in a spread of the determined smeas.

For example, we re-measure the CD of a line, but the line is shifted with respect to the original measurement position. The error with respect to the original measurement position has the same form as Equation (7), but L is replaced by the positioning error (Dxpos) and sinf is replaced by sCDU. The correlation length is related to the resist and is unaltered.

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Figure 6: The dots indicate the monitoring data with error bars. The different dashed lines represent the yield criteria for 50%, 95%, and 99%, respectively.

LWR and precision

It is demonstrated that the measured LWR (smeas) changes when the box length is increased. Investigation of points along the edge shows that for larger distance (x) between two measurements, the data is independent. However,

If Dxpos=0, additional CD measurement yields identical results. For Dxpos>>x the measurements are independent and the spread is sCDU. We take a measurement box of L=200 nm and measure the LWR to verify the model experimentally. Figure 7 shows the experimental findings and the theoretical results from Equation (9). The parameters in Equation (9) are x =44.3 nm and sinf=5.5 nm as found from earlier experiments using this resist.

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IMEC (exposures are performed on the ASML /1100 â&#x20AC;&#x2DC;dryâ&#x20AC;&#x2122;). The Gaussian behavior is again evident. Each measurement is performed over 340 sites, and the precision of the estimated average is less than 0.1 nm, thus allowing clear, rigorous discrimination between resist type. The measurements were fully automated, and they took less than one hour per resist. The mean LWR for the five resists is given in Table 2:

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Table 2: Mean s for five resists as evaluated on the ASML /1100 â&#x20AC;&#x2DC;dryâ&#x20AC;&#x2122;.

Figure 7: CD repeatability as a function of the positioning error along the edge of the line.

The theoretical results match the experimental data.

These findings show that for a given box length the precision of a CD measurement is limited due to the positioning accuracy of the CD-SEM. If better LWR reproducibility is required, then the box length should be increased or the repositioning at the exact same position needs to be improved.

Besides average information on the roughness across the wafer, it is possible to obtain wafer mapping of the LWR. Radial LWR maps for different resists are shown as an example in figure 9. The data clearly indicate a spike in LWR of the resist L4 close to the center of the wafer, most probably related to problems in the coating procedure.

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The algorithms used to characterize roughness are being applied to a variety of use cases, in addition to process control. In particular, we reported recently9,15 on LWR measurement characterizing LER transfer to etch and roughness variation caused by 193 nm shrinkage. We discuss here the use of the LER algorithm applied to benchmarking of resist and topcoats. The results in Figure 8 show the LWR measured on five different resists, being screened to define the candidate of choice for immersion lithography on the ASML XT 1250i at

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Figure 8: Measured distribution of the sLWR for 5 different resists.

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The effects of line edge roughness on the intrinsic MOS transistor performance and yield have been investigated in a 130 nm CMOS technology with gate lengths ranging down to 50 nm. From the experiment, it follows that L crit ~ L nominal - 16.5 nm. This margin can be increased by: reducing sLWR or increasing x. However, the latter â&#x20AC;&#x2DC;solutionâ&#x20AC;&#x2122; will also give rise to increased

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parameter fluctuations. A better approach might be to actually try to decrease x so far that further processing more efficiently smoothens out the roughness, which, in its turn, leads to a lower value of sLWR. The experiment for a large-scale digital design shows that the devices have to be able to cope with acceptable device deviations for a given sLWR. It also has been demonstrated that the online metrology can be applied with high accuracy for the screening of new resist materials.

Acknowledgements

The authors would like to thank Christie Delvaux, Nadia Vandenbroeck, and Frieda Van Roey for all the practical work and assistance in the many measurements. The authors are indebted to the European Commission and the Medea+ organization, for the funding of the European project IST-1-507754-IP (More Moore). The authors would also like to thank the IMEC lithography department, including the industrial affiliates based at IMEC and the IIAP partners of the 193-immersion program.

L.H.A. Leunissen, G.F. Lorusso, M. Ercken, J. A. Croon, H. Yang, A. Azordegan, T. DiBiase, Full Spectral Analysis of Line Width Roughness in SPIE 2005 Metrology, Inspection, and Process Control for Microlithography XIX, Proceedings of SPIE Vol. 5752, pgs. 578-590 (2005) References 1. W.G. Lawrence, “Spatial Frequency Analysis of Line Edge Roughness in Nine Chemically Related Photoresists”, Proc.

SPIE 5039, 713 (2003) 2. J. Shin, G. Han, Y. Ma, K. Moloni and F. Cerrina, “Resist Line Edge Roughness and Aerial Image Contrast”, J. Vac. Sci. Technol. B19, 2890 (2001) 3. H.P. Koh, Q.Y. Lin, X. Hu and L. Chan, “Effect of Process Parameters on Edge Roughness of Chemically Amplified Resists”, Proc. SPIE 3999, 240 (2000) 4. S. Masuda, X. Ma, G. Noya and G. Pawlowski, “Lithography and Line Edge Roughness of High Activation Energy Resists”, Proc. SPIE 3999, 252 (2000) 5. M. Ercken, G. Storms, C. Delvaux, N. Vandenbroeck, P. Leunissen and I. Pollentier, “Line Edge Roughness and its Increasing Importance”, Proceedings of Interface (2002)

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6. G.P. Patsis, V. Constantoudis, A. Tserepi and E. Gogolides, “Quantification of Line Edge Roughness of Photoresists. Part I: A Comparison Between Off-line and On-line Analysis of Top-down SEM Images”, J. Vac. Sci. Technol. B21, 1008 (2003) 7. G. P. Patsis, V. Constantoudis, A. Tserepi, and E. Gogolides, Grozdan Grozev, and T. Hoffmann, “Roughness Analysis of Lithographically Produced Nanostructures: Off-line Measurement and Scaling Analysis”, Microelectronic Engineering 678: 319-25 (2003) 8. A.-L. Barabasi and H.E. Stanley, “Fractal Concepts in Surface Growth”, Cambridge University Press, Cambridge, England, 1995 9. L.H.A. Leunissen, G. F. Lorusso, T. DiBiase, H. Yang, A. Azordegan, “On-line Spectral Analysis of Line Edge Roughness: Algorithms Qualification and Transfer to Etch”, Semiconductor Fabtech (to be published) 10. J.A. Croon, L.H.A. Leunissen, M. Jurczak, M. Benndorf, R. Rooyackers, K. Ronse, S. Decoutere, W. Sansen and H.E. Maes, “Experimental Investigation of the Impact of Line-edge Roughness on MOSFET Performance and Yield,” Proc. ESSDERC, 227 (2003) 11. V. Constantoudis, G. P. Patsis, L. H. A. Leunissen, and E. Gogolides, “Line Edge Roughness and Critical Dimension Variation: Fractal Characterization and Comparison using Model Functions”, J. Vac. Sci. Technol. B 22, 1974 (2004) 12. L.H.A. Leunissen, W.G. Lawrence and M. Ercken, “Line edge roughness: Experimental Results Related to a Two-parameter Model” Microelectron. Eng. 73-74, 265 (2004).

13. V. Constantoudis, G. P. Patsis, L. H. A. Leunissen, and E. Gogolides, “Toward a Complete Description of Line Width Roughness: a Comparison of Different Methods for Vertical and Spatial LER and LWR Analysis and CD Variation”, Proc.

SPIE 5375, 967 (2004) 14. J.A. Croon, W. Sansen, and H.E. Maes, “Matching Properties of Deep Sub-micron MOS Transistor” Springer (to be published) 15. L.H.A. Leunissen, M. Ercken, M. Goethals, S. Locorotondo, K. Ronse, G.B. Derksen, D. Nijkerk, G.F. Lorusso, “Transfer of Line Edge Roughness During Gate Patterning Process” Proceedings of International Symposium on Dry Process (ISBN 4-9900915-7-4), 1 (2004)

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