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Bridging the Gap Between Design and Mask Physics-based Model for OPC Verification Yung Feng Cheng, Yueh lin Chou, Chuen Huei Yang and CL Lin, UMC Corporation Bo Su, Gaurav Verma, William Volk, Mohsen Ahmadian, Hong Du, Abhishek Vikram, Scott Andrews, KLA-Tencor Corporation

Disparate inspection strategies have given way to various approaches for verifying post-OPC designs for manufacturing.

However, a new paradigm has emerged in design verification that moves OPC verification from the design plane to the wafer plane, where it really matters. KLA-Tencor’s DesignScan system inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure calibration window. Building on this paradigm is a new methodology on process window monitoring for OPC databases using DesignScan and report results for a chip. This methodology will be explored in this article, along with new applications in areas such as reticle target CD specification.

Introduction

As technology progresses towards 65 nm and beyond, optical lithography faces increased difficulties, and reticle enhancement techniques (RET) become imperative for multiple process layers. With RET implementation, especially the optical proximity correction (OPC) technique, the mask layout deviates further from the design-intended layout. Thus, the need for linking design space with process space to ensure designintended device integrity is even greater.

For the OPC decorated design database, it is important to verify the OPC before the mask-making step. This verification step can help ensure that there are no design-related defects, and it can provide a reasonable process window for a given process. Design rule or optical rule checkers have typically been used successfully to find design-related defects at best focus and exposure conditions. However, for full chip process window verification, there was no such system available until now. The main requirements for process window monitoring are good resist modeling and inspection speed.

We previously reported an integrated approach using DesignScan. In the article, we detail DesignScan’s defect detection capabil-

ity, model accuracy by comparison to wafer scanning electron microscopy (SEM) images, and simulation speed1. We also propose new use cases for DesignScan for design-based process monitoring and control, as well as process window impact-based mask specifications.

Uncovering pattern-dependent systematic defects

DesignScan 290 is a new inspection system from KLATencor that detects pattern-dependent (feature-based) systematic defects in the lithography process window of the post-RET design. The inspection is accomplished by simulating the transfer of the design to the reticle plane and subsequently projecting the reticle image onto the photoresist. The simulations are conducted at nominal condition and at user-defined off focus-exposure conditions through the process window and beyond. The normal DesignScan inspection is a two-step process. First comes the best focus and exposure (F0E0) inspection (the simulated image to database inspection), in which the simulated resist images at the best focus and exposure condition are compared to the pre-OPC design database (design intent) to detect possible defects due to OPC decoration. Second is the process window inspection (the simulated image to simulated image inspection), which uses the best focus and exposure condition resist images as the reference. In this phase, each simulation within the process window is compared to the one at nominal conditions to detect any unacceptable variation in pattern fidelity.

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The DesignScan system consists of hardware and software components, many of which are based on the KLA-Tencor TeraScan die-to-database reticle inspection system and the KLA-Tencor PROLITH simulation software. The system is configurable for a selected throughput target.

Prior to the DesignScan inspection, the post-RET/OPC designs are converted to a proprietary KLA-Tencor format optimized for inspection throughput. During inspection, the converted design is segmented into patches and fed to the proprietary image computer, which is used for both the simulation of the design patches and the detection of defects. The image computer is a multiple processorbased supercomputer capable of simulating multiple jobs simultaneously. Design patches that fail within the process window are noted as defective not only within the process window, but anywhere in the FE space which is simulated. Defect reports are sent to the operator consol, which is also used for inspection setup and review.

The simulation models three distinct steps in the lithography process: the transfer of the pattern to the reticle, the formation of the aerial image, and the formation of the resist image. The models for the reticle manufacturing process and aerial image formation, which uses vector imaging, are based on mature TeraScan technology used for die-to-database reticle inspection. The resist image formation and development are based on a proprietary fast resist model and PROLITH technology, also well developed and tested.

Each of the three models is calibrated or specified separately and could be decoupled, due to the physics-based nature of those models. Physics-based models are used to simulate reticle images from the design. The aerial image model is specified by providing the following basic illumination parameters: illumination wavelength, parametric or measured source shape, and objective lens NA. The resist model is calibrated by matching physical parameters to tuning data. The tuning data consists of focus-exposure matrix (FEM) critical dimension (CD) data from one-dimensional lines and spaces at various pitches and sizes. Due to physics-based resist modeling, any FE condition can be selected for simulation within the calibration space (tested up to 2x process window).

By contrast, empirical models have to be calibrated at each FE condition at which the simulation has to be done. Also, physics-based models require recalibration only if the physics of the process is changed, the polygons can be changed arbitrarily, and no recalibration is required. For empirical models used by other OPC verification tools, a recalibration is required if the physics or the polygons are changed. This leads to a significantly 34

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reduced calibration burden for physics-based models as compared to the burden required for maintaining empirical models.

Creating the right recipe

At runtime, the user creates an inspection recipe through a menu-driven graphical user interface (GUI) shown in Figure 1. It is at this point that the design database to be inspected and the previously calibrated or specified models are recalled. The user also selects the range of focus and exposure conditions to be used in the inspection during this step. Each focus and exposure condition to be simulated can be defined individually and need not be a regular array of points. Any segment of the design that has been converted to the DesignScan format can be inspected. The system supports the definition of multiple inspection areas, each of which can have independent defect sensitivity settings. The sensitivity setting can be changed for each detector and each area independently. The runtime setup process typically takes less than 10 minutes.

Once the recipe is defined, the inspection process begins and each patch of the design is processed through the simulation and defect detection models. It is at this stage that the various simulations for each design patch are compared to the simulation at nominal conditions.

The defect detection algorithm checks for the following types of defects: bridges, breaks, extra and missing printed features, minimum resist width and minimum space width (CD variation defects), line-end shortening

Figure 1: The DesignScan setup GUI. The recipe is created in a series of steps that begin by selecting the design to be inspected.

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ables correction of those defects which have the biggest process window impact first, since they are the process window limiters. Without such a guide, one may correct those defects which are not the process window limiters; as a result, no process window improvements will be seen.

Experiments: SRAM test database and Metal 1 layer

multiple configurations can be saved as templates.

(LES), and interlayer overlap (ILO) defects. The defect detection is based on any topographical change between a test resist profile and the reference resist profile A proprietary defect binning model is used to group all lithographically identical defects. This greatly improves review efficiency. During inspection, DesignScan applies lithography hierarchy to perform binning, i.e., patterns are compared within the lithographically significant distance for matching and binning. The efficiencies gained by the defect binning system will be dependent on how the pattern repeats in the design, among other factors.

The binning is particularly useful when certain defective pattern is repeating, like in memory devices. In the example shown below, using the SRAM design database, a reduction in the number of unique defects by a factor of one and half order of magnitude has been observed.

Review can occur after or concurrent with the inspection. The defect review application shown in Figure 2 can be used to display a wide range of defect-related information, such as database images, mask images, aerial images, and resist images. The display is userconfigurable and a configuration can be saved as a template and recalled later. The defects can be sorted by process window impact, as well as defect type or defect ID. It is very useful for process window monitoring to sort defects based on the process window impact. Such capability is only possible by DesignScan because one can select any FE grid for simulation within the calibration window. By knowing where a defect appears in FE space and its relative location to the nominal condition, DesignScan can easily obtain the process window impact separation and sort defects based on the process window impact. Such sorting provides a powerful guide for prioritizing the structures for corrections. It also en-

The SMP database is 3.9 x 8.6 mm2 in size on a wafer scale. A typical DesignScan inspection with 9 FE conditions takes about 62 minutes for this database. The system specifies that, for an 8 mm x 8 mm database, FEM data: space 100p 190.data 160

observation model prediction

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Figure 2: The DesignScan review GUI. This interface is configurable and

An SRAM test database, called SMP, was chosen for the test. This SMP database is designed using the 65 nm design rule, with a minimum half pitch of 90 nm. The database is decorated using model-based OPC, and the Metal 1 layer serves as the test layer. Two FEM wafers were printed using UMC’s Metal 1 process with resist calibration patterns and the SMP test database patterns.

The focus and exposure range extends beyond the process window. Four line/space patterns are used for model calibration. While the model accuracy was 4.1 nm when this work was originally completed, we have made significant improvements on model accuracy and recently demonstrated 2.5 nm for a poly-silicon layer. We expect to achieve better than 2 nm model accuracy. A Bossung plot of the measured CDs from the FEM wafers and the DesignScan model-predicted CDs for a dense line is shown in Figure 3.

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Figure 3: The Bossung plot of the measured CD data and DesignScan simulated CD data from the model calibration for a dense line.

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simulation with 9 FE conditions finishes within 2.5 hours. Nine FE conditions are a minimum requirement to adequately monitor the design’s performance across the process window by varying focus, dose, and both (diagonally) around the nominal condition.

Design RET application DesignScan 9 FE inline inspection.

Defect found?

Fix Yes

In OPC database process window inspection, the following process flow is proposed (see Figure DesignScan PW inspection.

4): after OPC decoration, perform a DesignHot spot found.

Scan inline inspection at 9 FE conditions (3x3).

If there are defects found within the process Mask tape out Pass on hot spot Local fix few hot window, then either the RET has to be modified information to wafer spots to extend to fix the defects or the process has to be re-cenprocess monitoring process window tered for the design, until no defects are present in the process window. Subsequent to the design Figure 4: The process flow chart in design process window monitoring for DesignScan. being clean in the process window, DesignScan process monitoring inspection—pushing FE defocus 100 nm and dose 2 mJ/cm2 further out uncovconditions for simulation beyond the edge of the ered no defects [see Figure 5 (b)]. process window and to find hot spots (weak spots) in the chip—should be run. Depending on the FE conditions In order to find weak spots, the FE conditions are (distance from the process window) and the number and extended even further outside the process window. Gap nature of hot spots found, one of the following actions defects start to appear on the high dose side, and bridge can be selected: send to mask tape out since it passed defects appear on the low dose side [see Figure 5 (c)]. inline inspection or perform local fixes to a few hot spots 1332 thin line and gap defects were found at a dose to extend the process window further (optimization); 14.3% higher than the nominal dose and at 180 nm deat the end, pass the hot spot information downstream focus. The proprietary advanced defect binning (ADB) to monitor those hot spots in mask making and wafer capability reduced the total defects to 21 unique groups, processing (helping wafer process control), since these due to the repeating pattern nature of the memory patterns are the most sensitive and first to fail in the device. Similarly, 2374 thin trench and bridge defects design due to process window drift or change. were found at a dose 21.4% lower than the nominal dose and at 180 nm defocus. DesignScan ADB reduces Results and analysis the total defects to 27 unique groups. Since gap defects appear closer (14.3% vs. 21.4% relative to the nominal 1. Process window monitoring dose) to the optimal condition, they are the weakest The SMP test database was already well debugged using wafers before it was inspected on DesignScan. However, the process could be improved and completed faster with a simulation-based system like DesignScan. DesignScan inline inspection found no defects within the process window, as shown in Figure 5 (a). The FE conditions to be simulated are selected at the edge of the process window and to match the wafer FE conditions (for verification purpose only). DesignScan color codes the defect map based on defect types (green Figure 5: The standard DesignScan inline inspection on SMP. No defects were found (represented by green dots) means no defects found), and the size within process window (a). Pushing FE points out further in focus and dose still uncovered no defects (b). In order of the circle is proportional to the to find weak spots, the FE points need to be extended by nearly 2x the process window (c). number of defects found. Extending 36

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nal dose a little further, the thin line defects become gaps as shown in Figure 6 (e). The gap defects appear at the exact locations and FE conditions as predicted by DesignScan. The SEM results confirm the weakness in those defective locations and the simulated resist images match wafer SEM images as well. DesignScan predicts the gap defect onset at 180 nm defocus, while the SEM image shows that the gap defects occur between 180 nm to 230 nm defocus (granularity limited due to the focus stepping distance for the FEM wafers).

Figure 6: DesignScan simulated resist images at nominal condition (a) and at defective condition (b). Corresponding SEM images from a FEM wafer at nominal condition (c) and at defective condition. Increase the dose further (e), and the predicted thin line defects become gaps, confirming the weakness of those locations.

Figure 7 shows another example of thin line/gap defect, indicated by a red dot in the DesignScan simulated resist image. The corresponding wafer SEM image confirms the defect. DesignScan predicts the gap defect onset at 180 nm defocus, while the SEM image shows the gap defects occuring between 180 nm to 230 nm defocus.

Those thin line defects become gap defects when the FE point is pushed further away from the nominal focus and exposure (F0E0). Given the fact that CD curves in a Bossung plot for a given feature do not cross, the weakest features will have the largest CD changes and become breaks/bridges first when moving FE away from F0E0. The onset of breaks/bridges is relatively easy to determine from SEM images. Thus, the predicated FE condition in which a break/bridge defect occurs can be directly compared to the FE condition where such a defect occurs on a FEM wafer through SEM review (subject to the increFigure 7: Another example of thin line/gap defect (left) and its corresponding wafer image (right). mental changes of focus and dose of FEM). Due The thin line breaks at the exact place that DesignScan predicted would be a weak point. to systematic and random errors in mask making, in optical imaging systems, and in resist image structures and also the process window limiter. Figure formation, there is FE offset between the simu6 shows an example comparing a group of thin line lated resist images from design database to the actual defects predicted by DesignScan and the corresponding resist images at defective locations. We have established wafer SEM images. In Figure 6 (a) and (b), the resist the DesignScan prediction offset specification on FE images from DesignScan at nominal condition (a) and conditions where a defect will occur based on internal defective condition (b) are shown, where the white areas tests: within the process window, the dose offset should indicate areas without photoresist (spaces) and the dark be within 2.5% and the focus offset should be within areas represent the areas covered with photoresist (lines).

30 nm; outside the process window, the dose offset At high dose defective condition, DesignScan found should be within 5% and the focus offset should be multiple defects (indicated by red dots) due to the thinwithin 50 nm due to increased line/space changes as a ning of certain resist lines as shown in Figure 6 (b). To function of dose and/or focus change. The confirmed compare DesignScan simulation results, the corresponddefects found by DesignScan on the SMP database are ing wafer SEM images are shown in Figure 6 (c) and (d) all within the offset specifications. for the nominal condition and the defective condition, respectively. By pushing the dose away from the nomiSince DesignScan can simulate whole or part of the Spring 2006

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and dose changes is indicated. There are four defects within the field of view (FOV), labeled from the top to the bottom as d1 to d4 (see the lower left corner resist image). The upper right corner image is the closest to the nominal conditions, and the lower left image is the farthest from the nominal conditions. It is clear from Figure 8 (a) that d2 is the weakest and d3 is the strongest among the four. By knowing the relative weakness of those defects, a designer can then prioritize the structures for corrections. Fixing the weakest structures will help extend the process window until the next weakest becomes the weakest. Fixing the second weakest structures first will not extend the process window, since the process window is dictated by the weakest structures.

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Figure 8: In order to better match the simulation result and the wafer SEM image, DesignScan simulated near the onset of a group of defects in finer 3x4 FE grid: every 0.5 mJ/cm2 in dose in vertical direction and every 10 nm in defocus in horizontal direction as shown in (a). A corresponding SEM image matches the bottom simulated image in 180 nm defocus column, which is enlarged in (c).

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SMP database anywhere within the resist model calibration conditions (FE range), it is quite useful in certain cases to separate defects by their weakness (where in FE space a defect occurs relative to the nominal condition). Figure 8 shows an example of a group of bridge defects near the onset at much finer FE grid. Again, the fast simulation speed allows us to do such a fine FE grid (18 FE points) in 67 minutes for the SMP test database.

The fine grid FE simulation pinpoints where a defect starts to appear; thus, in the case of Figure 8, the relative weakness of several defects as a function of focus 38

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Figure 9: Another bridge defect example. DesignScan correctly predicted the weak points. Fine FE grid simulation tells relative weakness of two defective locations.

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The fine FE grid inspection can also help system developers to gauge the accuracy of the model prediction.

By matching the catastrophic defective condition of predicted defect onset to that of a FEM wafer, the defect prediction offset can be established. For this particular group of defects, the dose offset is 3.6% of nominal dose and the focus offset is 10 nm [see Figure 8 (b) and (c)].

Figure 9 shows another example for bridge defects. The fine FE grid simulation clearly distinguishes the relative weakness of two defects within the FOV, and helps to match the simulated resist image to the wafer SEM image [see Figure 9 (b) and (c)].

Table 1 summarizes the confirmation results for all gap defects and bridge defects. 20 out of 21 groups of gap defects and 27 out of 27 groups of bridge defects are confirmed by the wafer SEM images. &% RANGE $EFECT TYPE !$" #ONFIRMED /FFSET NM

.!

NM GAPS

NM

BRIDGES

NM

Table 1: The defect confirmation summary.

All of the defect information can be used in a subsequent mask-making process (pattern-dependent CD control) and in wafer processing monitoring (patterndependent yield loss). Since we know that the gap defects are the weakest and are the process window limiters, it is critical to achieve tight CD control in a mask-making process in the regions that contain those gap defects. The CD control in other regions is less critical; thus, the CD control specifications can be loosened. In wafer processing (lithography and etch), these gap defectivity locations (structures) will be the first to fail if the process condition deviates away from the nominal condition, which can cause yield loss. Such information will greatly increase the efficiency of wafer processing monitoring.

2. New DesignScan detectors-LES and ILO

We tested the newly developed line-end shortening (LES) detector on the SMP database. The detector can be enabled and disabled in recipe setup. DesignScan found no LES defects within the process window for SMP. 490 LES defects were detected outside the process window at 21.4% lower than nominal dose and 180 nm defocus using a detection threshold of 60 nm—an adjustable parameter. When a line-end shortening exceeds 60 nm relative to the reference line end, the simulated resist image at nominal condition, or for the nominal condi-

One group of gap defects (31 total instances) predicted

by DesignScan cannot be conclusively confirmed by SEM images as shown in Figure 10. Thus, 3675 out of 3706 (99.16%) defects have been confirmed by wafer SEM images. In the simulation model calibration process, we intentionally tune the data so that we over-predict defects. By doing so, we increase the alpha risk (false alarm, detecting more nuisance defects), but minimize the beta risk (failure to detect, not miss a real defect), since missing a real defect is more costly than a false alarm.

Figure 11: An example of an LES defect detected by DesignScan. The DesignFigure 10: DesignScan predicted a defect (left) and its corresponding SEM image (right). The SEM image cannot conclusively confirm the defect in this case.

Scan simulated resist images at defective (left) and reference (right) conditions are shown on top. The green lines represent the design feature edges and the purple lines indicate resist edges. The corresponding wafer SEM images are shown below at the defective (left) and the reference (right) conditions.

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tion compared to the drawn/decorated database, the line end will be agged as defective. More LES defects can be detected by lowering the LES detection threshold.

ADB reduces the defects into 21 groups. SEM review images have confirmed all 21 group LES defects, and Figure 11 shows an example of an LES defect in a zoomin view. DesignScan predicated images match the wafer SEM images well. In all detected LES defect cases, no or inadequate OPC for the line ends are identified. Based on the DesignScan LES findings, the OPC at those line ends can be significantly improved to avoid severe LES. Another newly developed 2D DesignScan defect detection capability is interlayer overlap (ILO) detector. The interlayer overlap detector can be activated and the detection parameter adjusted independently for the layer below and the layer above.

For the SMP database, we will focus on contact to Metal 1 layer overlap testing. Metal 1 is the layer of interest and the overlap error between the contact and Metal 1 is caused by line-end shortening of metal lines. DesignScan found 60 ILO defects with the default parameter setting at 17.8% lower than nominal dose and 180 nm defocus, and 343 ILO defects at 21.4% lower than nominal dose and 180 nm defocus, along with other defects. Figure 12 shows an example of an ILO defect (red circle at right) detected by DesignScan with SMP. The simulated resist image at nominal condition is at left and the resist image at defective condition is at right.

The green lines represent the metal database and the blue squares are contacts.

be implemented is determination of the reticle target CD specification through process window simulation.

This can be achieved by simply biasing the polygons of the post-OPC database in both directions (+/-) during the data conversion phase and re-inspecting the database. By evaluating the process window impact of the biased database, the CD tolerance specifications for different regions of the database can be determined.

The SMP test database in our study was biased+/-5 nm, +/- 10 nm, and +/- 15nm. Inline 9 FE condition DesignScan inspection still yields zero catastrophic defects. However, the gap defects (Figure 6 shows some of the examples) appear early on the high dose side for positive biases (white space increases) as shown in Figure 13. No bridge defects appear in the FE range inspected on the low dose side for negative biases (white space decreases) up to 15 nm. For concept demonstration purposes, we stopped at 15 nm bias, since higher bias may require the re-adjustment of the nominal condition and resist model recalibration.

Figure 13: Defect map of SMP with 5 nm, 10 nm, and 15 nm biases (increase white area). Thin line (blue) and gap (orange) defects appear closer to the nominal condition as the bias increases, which means the process window gets smaller.

Figure 12: An example of an interlayer overlap defect (indicated by the red circle) of SMP between the contact layer (blue squares) and the Metal1 layer (green lines). The resist edges are enhanced with purple lines for the nominal condition (left) and defective condition (right).

3. Mask CD target specification

One of the new applications for which DesignScan can 40

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Not only are those gap defects the weakest in the SMP database and the process window limiters, they also dictate the reticle CD specifications. Maintaining good CD control in the gap defective locations is much more critical than in other regions, the foundation for pattern-dependent reticle CD specifications. We can also conclude that for the SMP database, the reticle CD control is asymmetric: for the tested metal layer case, maintaining tighter CD control is required on the positive bias side rather than on the negative bias side.

To avoid such CD control asymmetry and also extend the process window, re-centering the process is recommended. For the SMP test database, lowering the nominal dose from 28 mJ/cm2 to 27 mJ/cm2 will help to reduce defect-related yield loss, assuming no other negative effect to the device functionality. Typically, the process window center, which is the center of the

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process window used for all designs, is determined using test structures. This is inadequate because the test structures do not always adequately represent the full database and also because the behavior of all designs is not identical through a process window. Using DesignScan, the process center can be determined and optimized for each individual design, providing the largest possible process window and, hence, yield.

In this article, we have demonstrated additional use cases for DesignScan. The solution can be used for design-based mask CD specification determination and design-based process centering. Users can fit the process to the design or vice versa. We have also demonstrated the methodology for using DesignScan for design-based process control and monitoring.

In this illustration we have discussed the mask CD specification use case through open and bridge defects. Similar analysis can be performed for CD variations through the use of DesignScan CD simulation capability.

Acknowledgements

Summary

We have demonstrated a methodology for monitoring the performance of a post-OPC design database across and beyond the process window using DesignScan. The ability of simulating resist images at any arbitrary FE location (within model calibration range) using one calibrated model and fast inspection speed allows DesignScan to perform full process window monitoring and optimization. The methodology in this paper has been demonstrated using a 90 nm half pitch SRAM Metal 1 database. In this database, no defects were found within the process window. Gap defects were found and confirmed on the wafer 14.3% away from the nominal dose and at 180 nm defocus. Bridge defects were confirmed on the wafer 21.4% away from the nominal dose and at 180 nm defocus. These patterns are the weakest across the FE conditions. If there is a change in the process, these locations will fail first; hence, these locations should be used for inline monitoring of the lithography process for systematic changes. This database has a fairly robust process window; however, the process window can also be further improved by fixing these potentially yield-limiting locations that have been identified by DesignScan.

The authors would like to thank the UMC lithography and OPC team and KLA-Tencor DesignScan engineering team for their support.

Yung Feng Cheng, Yueh lin Chou, Chuen Huei Yang and CL Lin, Bo Su, Gaurav Verma, William Volk, Mohsen Ahmadian, Hong Du, Abhishek Vikram, Scott Andrews,Reducing Design Respins, in 25th Annual BACUS Symposium on Photomask Technology, edited

by J. Tracy Weed, Patrick M. Martin, Proc. of SPIE Vol. 5992, 59921X, (2005) CID# 599244 Reference 1. W. Howard, et al, “Inspection of integrated circuit databases through reticle and wafer simulation: An integrated approach to Design for Manufacturing (DFM)�, Proc. SPIE vol. 5756, pp 61-72 (2005).

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