Lithography D F M
Bridging the Gap Between Design and Mask Physics-based Model for OPC Verification Yung Feng Cheng, Yueh lin Chou, Chuen Huei Yang and CL Lin, UMC Corporation Bo Su, Gaurav Verma, William Volk, Mohsen Ahmadian, Hong Du, Abhishek Vikram, Scott Andrews, KLA-Tencor Corporation
Disparate inspection strategies have given way to various approaches for verifying post-OPC designs for manufacturing. However, a new paradigm has emerged in design verification that moves OPC verification from the design plane to the wafer plane, where it really matters. KLA-Tencor’s DesignScan system inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure calibration window. Building on this paradigm is a new methodology on process window monitoring for OPC databases using DesignScan and report results for a chip. This methodology will be explored in this article, along with new applications in areas such as reticle target CD specification. Introduction
As technology progresses towards 65 nm and beyond, optical lithography faces increased difficulties, and reticle enhancement techniques (RET) become imperative for multiple process layers. With RET implementation, especially the optical proximity correction (OPC) technique, the mask layout deviates further from the design-intended layout. Thus, the need for linking design space with process space to ensure designintended device integrity is even greater. For the OPC decorated design database, it is important to verify the OPC before the mask-making step. This verification step can help ensure that there are no design-related defects, and it can provide a reasonable process window for a given process. Design rule or optical rule checkers have typically been used successfully to find design-related defects at best focus and exposure conditions. However, for full chip process window verification, there was no such system available until now. The main requirements for process window monitoring are good resist modeling and inspection speed. We previously reported an integrated approach using DesignScan. In the article, we detail DesignScan’s defect detection capabil-
ity, model accuracy by comparison to wafer scanning electron microscopy (SEM) images, and simulation speed1. We also propose new use cases for DesignScan for design-based process monitoring and control, as well as process window impact-based mask specifications. Uncovering pattern-dependent systematic defects
DesignScan 290 is a new inspection system from KLATencor that detects pattern-dependent (feature-based) systematic defects in the lithography process window of the post-RET design. The inspection is accomplished by simulating the transfer of the design to the reticle plane and subsequently projecting the reticle image onto the photoresist. The simulations are conducted at nominal condition and at user-defined off focus-exposure conditions through the process window and beyond. The normal DesignScan inspection is a two-step process. First comes the best focus and exposure (F0E0) inspection (the simulated image to database inspection), in which the simulated resist images at the best focus and exposure condition are compared to the pre-OPC design database (design intent) to detect possible defects due to OPC decoration. Second is the process window inspection (the simulated image to simulated image inspection), which uses the best focus and exposure condition resist images as the reference. In this phase, each simulation within the process window is compared to the one at nominal conditions to detect any unacceptable variation in pattern fidelity. Spring 2006
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