Spring06 in chip overlay

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In-chip Overlay Metrology in 90-nm Production Bernd Schulz, Rolf Seltmann, and Joerg Paufler, AMD Philippe Leray, IMEC Aviv Frommer, Pavel Izikson, Elyakim Kassel, and Mike Adel, KLA-Tencor Corporation © 2005 IEEE. Bernd Schulz, Rolf Seltmann , Joerg Paufler, Philippe Leray, Aviv Frommer, Pavel Izikson, Elyakim Kassel & Mike Adel, In-chip overlay metrology in 90nm production. Reprinted, with permission, from International Symposium on Semiconductor Manufacturing (ISSM) 2005 Conference.

While scanner aberration-induced pattern placement errors (PPE) can be measured, simulated, and validated by scanning electron microscope (SEM), the magnitude of the effect on late-generation scanners is small — of the order of ~1.5 nm in one line peak to peak across the slit. In-die overlay data contains additional sources of variation beyond PPE, and the results have been verified by SEM. Current practices based on linear models do not capture in-die variations as large as 5 nm, which significantly impacts model residuals. Currently, in-die target insertion is an insurance policy which enables in-die troubleshooting when process issues are suspected, and will potentially improve lot dispositioning in the future. Introduction

Overlay is traditionally measured with metrology structures located in the four corners of a reticle field, consistent with the assumption of an overlay model with linear field dependence. This assumption dictates that the four corner measurements represent the extremes of overlay of all structures inside the reticle field. A number of recent studies have indicated that the discrepancies from field linearity may no longer be negligible when considering overlay control requirements at 65 nm. In order to be able to characterize and monitor overlay at multiple field locations, it has become necessary to insert metrology structures into locations other than the field edge scribe lines. Standard size overlay structures are difficult to insert in-chip and represent a barrier to verification of the above assumption. This study reports on results of in-chip overlay metrology on product wafers using microAIM targets of 13x13 µm2.

on real product reticles. The size of the mark under test is about 13x13 µm2, compared with the standard size of 27x27 µm2. The design of the reference layer has a NS (non-segmented) outer and segmented inner. As will be described later, this mark can be used as a PPE monitor prior to the subsequent processing and lithographic steps. The current layer design consists of a NS inner, so the complete mark behaves as a NS AIM overlay mark. This is shown in the SEM images in Figures 3 and 4. Insertion locations were selected in areas of the device without electrical functionality. These areas are typically tiled with dummy areas. Some of the dummy tiles are removed to place the overlay

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Metrology target insertion into product dies

This section describes the methods used for designing and laying out micro-AIM marks 60

Spring 2006

Yield Management Solutions

Figure 1: Alternative micro-AIM layout strategies: in-die method on the left and internal scribe method on the right.


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