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Overlay M

In-chip Overlay Metrology in 90-nm Production Bernd Schulz, Rolf Seltmann, and Joerg Paufler, AMD Philippe Leray, IMEC Aviv Frommer, Pavel Izikson, Elyakim Kassel, and Mike Adel, KLA-Tencor Corporation © 2005 IEEE. Bernd Schulz, Rolf Seltmann , Joerg Paufler, Philippe Leray, Aviv Frommer, Pavel Izikson, Elyakim Kassel & Mike Adel, In-chip overlay metrology in 90nm production. Reprinted, with permission, from International Symposium on Semiconductor Manufacturing (ISSM) 2005 Conference.

While scanner aberration-induced pattern placement errors (PPE) can be measured, simulated, and validated by scanning electron microscope (SEM), the magnitude of the effect on late-generation scanners is small — of the order of ~1.5 nm in one line peak to peak across the slit. In-die overlay data contains additional sources of variation beyond PPE, and the results have been verified by SEM. Current practices based on linear models do not capture in-die variations as large as 5 nm, which significantly impacts model residuals. Currently, in-die target insertion is an insurance policy which enables in-die troubleshooting when process issues are suspected, and will potentially improve lot dispositioning in the future. Introduction

Overlay is traditionally measured with metrology structures located in the four corners of a reticle field, consistent with the assumption of an overlay model with linear field dependence. This assumption dictates that the four corner measurements represent the extremes of overlay of all structures inside the reticle field. A number of recent studies have indicated that the discrepancies from field linearity may no longer be negligible when considering overlay control requirements at 65 nm. In order to be able to characterize and monitor overlay at multiple field locations, it has become necessary to insert metrology structures into locations other than the field edge scribe lines. Standard size overlay structures are difficult to insert in-chip and represent a barrier to verification of the above assumption. This study reports on results of in-chip overlay metrology on product wafers using microAIM targets of 13x13 µm2.

on real product reticles. The size of the mark under test is about 13x13 µm2, compared with the standard size of 27x27 µm2. The design of the reference layer has a NS (non-segmented) outer and segmented inner. As will be described later, this mark can be used as a PPE monitor prior to the subsequent processing and lithographic steps. The current layer design consists of a NS inner, so the complete mark behaves as a NS AIM overlay mark. This is shown in the SEM images in Figures 3 and 4. Insertion locations were selected in areas of the device without electrical functionality. These areas are typically tiled with dummy areas. Some of the dummy tiles are removed to place the overlay

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Metrology target insertion into product dies

This section describes the methods used for designing and laying out micro-AIM marks 60

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Figure 1: Alternative micro-AIM layout strategies: in-die method on the left and internal scribe method on the right.

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Figure 2: Optical image of micro-AIM target inserted in-die as shown on the left in Figure 1.

Figure 5: 3sigma precision performance of standard AIM, scribe line micro-AIM, and in-die micro-AIM targets compared with scribe line box in box.

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Figure 3: SEM images of micro-AIM

Figure 4: SEM image of micro-AIM

target in photoresist.

target after second lithography and

Metrology performance on in-die targets

In order to enable metrology target insertion in multiple field locations, target size needs to be substantially reduced. In this study the actual target area was reduced by a factor of four compared with the standard scribe line targets. One of the potential risks associated with this drastic reduction is the possible degradation in overlay mark fidelity (OMF) and precision due to reduced spatial and temporal information content. The data in Figure 5 indicates that although some degradation is observed, the performance is still deep within the specifications of the Archer AIM tool. The in-die optical metrology results were also validated by a correlation study with CD SEM-based overlay results after etch, as shown in Figure 6. A Mandel regression

subsequent etch.

marks (See optical image in Figure 2). An alternative insertion strategy also tested was based on internal scribe lines within a six-die field. These two insertion strategies are shown diagrammatically in Figure 1.

Figure 6: CD SEM overlay versus imaging overlay results from in-die targets.

was performed on the data sets to evaluate linearity and biases, and the results in Table 1 indicate a good linearity with a small but significant bias in the x direction. This is potentially attributed to CD SEM bias as no tool induced shift (TIS) correction is applied, as opposed to the case in optical metrology where TIS is routinely measured and corrected. X overlay

Slope

Offset [nm]

0.99 Âą 0.07

-1.4

0.88

Y overlay

0.94 Âą 0.11

0.2

0.77

Table 1: Orthogonal regression parameters for correlation data in Figure 6.

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Aberration-induced pattern placement errors across the field

Exposure tool optical aberrations have been demonstrated in the past to be a key contributor to in-die PPE. It is also known that the magnitude of PPE is dependent on pitch and feature size1,2. Furthermore, Kye et. al have shown that such errors are also dependent on illumination conditions, such as coherency and illumination shape. Ueno et. al have published a methodology for characterizing with high precision the field dependence of PPE using grating-based simultaneous overlay marks. In the current work, such simultaneous marks have been reduced in size to 13x13 microns in order to fit into the available space at in-die locations while maintaining withinspecification metrology performance. We have also performed full electromagnetic simulations utilizing aberration measurements (taking into account Zernikes Z5 to Z15). The PPE sensitivity of the segmented and non-segmented parts of the grating to individual aberrations was calculated. As expected a near linear response to Zernikes was found with negligible crosstalk between individual aberrations. Figure 7 and Figure 8 display the results of these simulations compared with on-product measurements from wafers from two different generation exposure tools (PAS/1100 & XT1250).

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(Y direction) across the slit for two subsequent generations of scanners.

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Figure 9: CD SEM validation data for PPE in the x direction, measured on the same lot as the data in Figure 6, after etch.

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Figure 7: Simulated and measured pattern placement error dependence (X direction) across the slit for two subsequent generations of scanners.

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These results demonstrate that this effect can be measured and correlated well to simulations. In three out of four cases, the mean discrepancy was less than 0.5 nm and below 1 nm in the fourth case. More significantly, it is also observed that X-PPE peak-to-peak variation across the slit was reduced from 4 nm to 1.5 nm from

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one exposure tool generation to the next. Further validation of the PPE data was also achieved by performing CD SEM measurements. In this case, optical and CD SEM metrology was performed after etch, since photoresist coverage prohibits SEM-based overlay metrology immediately subsequent to lithography. The results are shown in Figure 8 where a mean offset of ~ 0.5 nm is observed between the SEM-based and optical metrology. A bias is also observed between the optically detected PPE before and after etch of about a nanometer. Such etch-induced PPE have been observed in our previous work and will be the subject of further endeavor. As we shall see in the next section, despite the impressive improvement in aberration-induced placement errors, significant high order structure is still observed in the overlay behavior across the scanner field, indicating that we need to continue the search for the dominant in-field contributors.

Full-field modeling

In this phase, the in-die overlay measurements were compared with the predicted overlay based on a model generated using a standard four-corner sampling plan as follows. In a first step, the in-die high density sampled data set was used to generate an interfield (wafer-level) model. This model was removed from the raw data and the remaining intra-field data was averaged over all fields to generate an “in-die map”. This map was then compared with (i.e. subtracted from) the linear intrafield model generated using a standard four-corner sampling plan. This methodology was used on several data sets from production lots on different products and in each case, a high order fingerprint was observed for the in-die map. In some cases, this map displayed systematic deviations from the linear model of up to 5 nm. It was also observed that this signature varied in the scan direction, further supporting the conjecture that aberration-induced PPE is not the primary cause of high order intra-field overlay. In particular, a correlation was observed between the in-die map and the position within the individual chip.

Figure 10: Systematic in-die residuals over scanner field on product, remaining after removal of standard four-corner linear model.

Acknowledgements Conclusions

Aberration-induced pattern placement errors have been characterized on product wafers for two different scanner generations. We observe their magnitude to be reduced to the extent that the systematic residuals of in-die overlay measurements cannot be explained by aberration-induced PPE alone. Other error sources are still a significant contribution to the total residual error and need to be further characterized. In-die micro overlay targets can be used to refine the current overlay models. Sampling plans for overlay measurements with a combination of conventional and in-die overlay structures will become an important compromise between throughput in production and improved feedback and lot dispositioning.

© 2005 IEEE. Bernd Schulz, Rolf Seltmann , Joerg Paufler, Philippe Leray, Aviv Frommer, Pavel Izikson, Elyakim Kassel & Mike Adel, In-chip overlay metrology in 90nm production. Reprinted, with permission, from International Symposium on Semiconductor Manufacturing (ISSM) 2005 Conference. This work was performed with the help of an R&D grant from the European Community under contract # IST-001854 Project OCSLI. References 1. C. Progler, S. Bukofsky, and D. Wheeler, “Method to budget and optimize total device overlay,” in Optical Microlithography XII, Luc Van den hove, Editor, Proceedings of SPIE Vol. 3679, 193-207 (1999). 2. Atsushi Ueno, Kouichirou Tsujita, Hiroyuki Kurita, Yasuhisa Iwata, Mark Ghinovker, Jorge M. Poplawski, Elyakim Kassel, and Mike E. Adel, “Improved overlay metrology device correlation on 90-nm logic processes”, Proc. SPIE vol. 5375, 222 (2004) 3. Jongwook Kye, Mircea Dusa, Harry J. Levinson “Linewidth asymmetry study to predict aberration in lithographic lenses”, Proceedings of, SPIE vol. 4346-134 (2001).

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